1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 //=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
16 // eCos is free software; you can redistribute it and/or modify it under
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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30 // or inline functions from this file, or you compile this file and link it
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40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //===========================================================================
45 #include <pkgconf/system.h> // System-wide configuration info
46 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
47 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
48 #include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
49 #include <cyg/hal/hal_mmu.h> // MMU definitions
50 #include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
52 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
53 #define PLATFORM_SETUP1 _platform_setup1
54 #define CYGHWR_HAL_ARM_HAS_MMU
56 #ifdef CYG_HAL_STARTUP_ROMRAM
57 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
60 #define CYGHWR_HAL_ROM_VADDR 0x0
62 // This macro represents the initial startup code for the platform
63 // r11 is reserved to contain chip rev info in this file
64 .macro _platform_setup1
65 FSL_BOARD_SETUP_START:
66 // invalidate I/D cache/TLB and drain write buffer
68 mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
69 mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
70 mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
75 mov r0, #SDRAM_NON_FLASH_BOOT
76 ldr r1, AVIC_VECTOR0_ADDR_W
77 str r0, [r1] // for checking boot source from nand, nor or sdram
79 // setup System Controls
80 ldr r0, SOC_SYSCTRL_BASE_W
82 str r1, [r0, #(SOC_SYSCTRL_PCSR - SOC_SYSCTRL_BASE)]
84 str r1, [r0, #(SOC_SYSCTRL_FMCR - SOC_SYSCTRL_BASE)]
88 init_drive_strength_start:
96 // check if sdram has been setup
97 cmp pc, #SDRAM_BASE_ADDR
99 cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
100 blo HWInitialise_skip_SDRAM_setup
104 // Now we must boot from Flash
105 mov r0, #NOR_FLASH_BOOT
106 ldr r1, AVIC_VECTOR0_ADDR_W
112 HWInitialise_skip_SDRAM_setup:
115 add r2, r0, #0x800 // 2K window
117 blo Normal_Boot_Continue
119 bhi Normal_Boot_Continue
121 /* Copy image from flash to SDRAM first */
122 ldr r1, MXC_REDBOOT_ROM_START
124 1: ldmia r0!, {r3-r10}
131 and r0, pc, r1 /* offset of pc */
132 ldr r1, MXC_REDBOOT_ROM_START
140 mov r0, #NAND_FLASH_BOOT
141 ldr r1, AVIC_VECTOR0_ADDR_W
144 ldr r1, AVIC_VECTOR1_ADDR_W
147 ldr r0, NFC_BASE_W //r0: nfc base. Reloaded after each page copying
148 mov r1, #0x800 //r1: starting flash addr to be copied. Updated constantly
149 add r2, r0, #0x200 //r2: end of 1st RAM buf. Doesn't change
150 add r12, r0, #0xE00 //r12: NFC register base. Doesn't change
151 ldr r14, MXC_REDBOOT_ROM_START
152 add r13, r14, #REDBOOT_IMAGE_SIZE //r13: end of SDRAM address for copying. Doesn't change
153 add r14, r14, r1 //r14: starting SDRAM address for copying. Updated constantly
155 //unlock internal buffer
160 // writew(FLASH_Read_Mode1, NAND_FLASH_CMD_REG);
162 strh r3, [r12, #NAND_FLASH_CMD_REG_OFF]
163 mov r3, #NAND_FLASH_CONFIG2_FCMD_EN;
164 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
167 // start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, nflash_dev_info->base_mask);
169 do_addr_input //1st addr cycle
171 do_addr_input //2nd addr cycle
173 do_addr_input //3rd addr cycle
176 do_addr_input //4th addr cycle
179 // NFC_DATA_OUTPUT(buf, FDO_PAGE_SPARE_VAL);
180 // writew(NAND_FLASH_CONFIG1_ECC_EN, NAND_FLASH_CONFIG1_REG);
181 mov r3, #(NAND_FLASH_CONFIG1_ECC_EN)
182 strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
184 // writew(buf_no, RAM_BUFFER_ADDRESS_REG);
186 strh r3, [r12, #RAM_BUFFER_ADDRESS_REG_OFF]
187 // writew(FDO_PAGE_SPARE_VAL & 0xFF, NAND_FLASH_CONFIG2_REG);
188 mov r3, #FDO_PAGE_SPARE_VAL
189 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
193 // check for bad block
194 mov r3, r1, lsl #(32-5-9)
195 cmp r3, #(512 << (32-5-9))
197 add r4, r0, #0x800 //r3 -> spare area buf 0
202 // really sucks. Bad block!!!!
205 // even suckier since we already read the first page!
206 sub r14, r14, #512 //rewind 1 page for the sdram pointer
207 sub r1, r1, #512 //rewind 1 page for the flash pointer
209 add r1, r1, #(32*512)
213 1: ldmia r0!, {r3-r10}
218 bge NAND_Copy_Main_done
225 Normal_Boot_Continue:
227 #ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
228 /* Copy image from flash to SDRAM first */
231 ldr r1, MXC_REDBOOT_ROM_START
233 beq HWInitialise_skip_SDRAM_copy
235 add r2, r0, #REDBOOT_IMAGE_SIZE
237 1: ldmia r0!, {r3-r10}
243 and r0, pc, r1 /* offset of pc */
244 ldr r1, =(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000 + 0x8)
250 #endif /* CYG_HAL_STARTUP_ROMRAM */
252 HWInitialise_skip_SDRAM_copy:
258 ldr r1, =(SOC_CRM_BASE)
259 ldr r2, [r1, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
260 /*Get chip ID://eq:i.MX27 TO1; neq:i.MX27 TO2*/
261 ldr r1, =SOC_SI_ID_REG
263 ands r1, r1, #0xF0000000
265 orreq r2, r2, #0xF000
266 orrne r2, r2, #0x01C0
268 ldr r1, =(SOC_CRM_BASE)
269 str r2, [r1, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
271 /* end of NAND clock divider setup */
273 // TLSbo76381: enable USB/PP/DMA burst override bits in GPCR
274 ldr r1, =(SOC_SYSCTRL_GPCR)
279 // Set up a stack [for calling C code]
280 ldr r1, =__startup_stack
281 ldr r2, =RAM_BANK0_BASE
289 mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
290 orr r1, r1, #7 // enable MMU bit
291 mcr MMU_CP, 0, r1, MMU_Control, c0
292 mov pc,r2 /* Change address spaces */
298 // Save shadow copy of BCR, also hardware configuration
302 str r9,[r1] // Saved far above...
304 .endm // _platform_setup1
306 #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
307 #define PLATFORM_SETUP1
311 ldr r0, SOC_CRM_BASE_W
312 // disable MPLL/SPLL first
313 ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
315 str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
317 /* Get the chip version and configure PLLs*/
318 ldr r1, SOC_SI_ID_REG_W
320 ands r1, r1, #0xF0000000
324 ldrh r1, [r1, #PBC_VERSION]
325 ands r1, r1, #CLK_INPUT_27MHZ_SET
328 ldrne r1, CRM_MPCTL0_VAL2_W
329 ldreq r1, CRM_MPCTL0_VAL2_27MHZ_W
330 str r1, [r0, #(SOC_CRM_MPCTL0 - SOC_CRM_BASE)]
332 ldrne r1, CRM_SPCTL0_VAL2_W
333 ldreq r1, CRM_SPCTL0_VAL2_27MHZ_W
334 str r1, [r0, #(SOC_CRM_SPCTL0 - SOC_CRM_BASE)]
337 1: ldr r1, PBC_BASE_W
338 ldrh r1, [r1, #PBC_VERSION]
339 ands r1, r1, #CLK_INPUT_27MHZ_SET
342 ldrne r1, CRM_MPCTL0_VAL_W
343 ldreq r1, CRM_MPCTL0_VAL_27MHZ_W
344 str r1, [r0, #(SOC_CRM_MPCTL0 - SOC_CRM_BASE)]
346 ldrne r1, CRM_SPCTL0_VAL_W
347 ldreq r1, CRM_SPCTL0_VAL_27MHZ_W
348 str r1, [r0, #(SOC_CRM_SPCTL0 - SOC_CRM_BASE)]
350 // enable/restart SPLL/MPLL
351 2: ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
352 #ifdef PLL_REF_CLK_32768HZ
353 // Make sure to use CKIL
354 bic r1, r1, #(3 << 16)
356 orr r1, r1, #(3 << 16) // select 26MHz
358 orr r1, r1, #0x000C0000
359 orr r1, r1, #0x00000003
360 str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
362 // add some delay here
367 //Check The chip version TO1 or TO2
368 ldr r1, SOC_SI_ID_REG_W
370 ands r1, r1, #0xF0000000
372 ldreq r2, SOC_CRM_CSCR_W
373 ldrne r2, SOC_CRM_CSCR2_W
374 str r2, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
376 //for i.MX27 TO2, Set divider of H264_CLK to zero, NFC to 3.
377 ldrne r2, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
378 bicne r2, r2, #0x0000FC00
379 strne r2, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
382 /* Configure PCDR1 */
383 ldr r1, SOC_CRM_PCDR1_W
384 str r1, [r0, #(SOC_CRM_PCDR1 - SOC_CRM_BASE)]
386 // Configure PCCR0 and PCCR1
387 ldr r1, SOC_CRM_PCCR0_W
388 str r1, [r0, #(SOC_CRM_PCCR0 - SOC_CRM_BASE)]
390 ldr r1, [r0, #(SOC_CRM_PCCR1 - SOC_CRM_BASE)]
392 str r1, [r0, #(SOC_CRM_PCCR1 - SOC_CRM_BASE)]
393 // make default CLKO to be FCLK
394 ldr r1, [r0, #(SOC_CRM_CCSR - SOC_CRM_BASE)]
395 and r1, r1, #0xFFFFFFE0
397 str r1, [r0, #(SOC_CRM_CCSR - SOC_CRM_BASE)]
401 ldr r1, SOC_CS0_CTL_BASE_W
402 ldr r2, CS0_0x0000CC03
403 str r2, [r1, #CSCRU_OFFSET]
404 ldr r2, CS0_0xA0330D01
405 str r2, [r1, #CSCRL_OFFSET]
406 ldr r2, CS0_0x00220800
407 str r2, [r1, #CSCRA_OFFSET]
410 /* CS0 sync mode setup */
413 * Sync mode (AHB Clk = 133MHz ; BCLK = 44.3MHz):
415 /* Flash reset command */
416 ldr r0, CS0_BASE_ADDR_W
420 ldr r2, CS0_CMD_0xAAA
425 ldr r2, CS0_CMD_0x554
430 ldr r2, CS0_CMD_0xAAA
434 /* Write flash config register */
435 ldr r1, CS0_CFG_0x66CA
437 /* Flash reset command */
441 ldr r0, =SOC_CS0_CTL_BASE
442 ldr r1, CS0_0x23524E80
443 str r1, [r0, #CSCRU_OFFSET]
444 ldr r1, CS0_0x10000D03
445 str r1, [r0, #CSCRL_OFFSET]
446 ldr r1, CS0_0x00720900
447 str r1, [r0, #CSCRA_OFFSET]
448 .endm /* init_cs0_sync */
450 .macro init_cs4: /* ADS board expanded IOs */
451 ldr r1, SOC_CS4_CTL_BASE_W
452 ldr r2, CS4_CSCRU_0x0000DCF6
453 str r2, [r1, #CSCRU_OFFSET]
454 ldr r2, CS4_CSCRL_0x444A4541
455 str r2, [r1, #CSCRL_OFFSET]
456 ldr r2, CS4_CSCRA_0x44443302
457 str r2, [r1, #CSCRA_OFFSET]
461 // setup AIPI1 and AIPI2
462 mov r0, #SOC_AIPI1_BASE
463 ldr r1, AIPI1_0x20040304
464 str r1, [r0] /* PSR0 */
465 ldr r2, AIPI1_0xDFFBFCFB
466 str r2, [r0, #4] /* PSR1 */
467 // set r0 = AIPI2 base
470 str r1, [r0] /* PSR0 */
472 str r2, [r0, #4] /* PSR1 */
476 ldr r0, SOC_MAX_BASE_W
477 add r1, r0, #MAX_SLAVE_PORT1_OFFSET
478 add r2, r0, #MAX_SLAVE_PORT2_OFFSET
479 add r0, r0, #MAX_SLAVE_PORT0_OFFSET
482 ldr r6, SOC_MAX_0x00302145 /* Priority SLCD>EMMA>DMA>Codec>DAHB>IAHB */
483 str r6, [r0, #MAX_SLAVE_MPR_OFFSET] /* same for all slave ports */
484 str r6, [r0, #MAX_SLAVE_AMPR_OFFSET]
485 str r6, [r1, #MAX_SLAVE_MPR_OFFSET]
486 str r6, [r1, #MAX_SLAVE_AMPR_OFFSET]
487 str r6, [r2, #MAX_SLAVE_MPR_OFFSET]
488 str r6, [r2, #MAX_SLAVE_AMPR_OFFSET]
491 .macro init_drive_strength
492 ldr r0, SOC_SYSCTRL_BASE_W
493 ldr r1, DS_0x55555555
494 str r1, [r0, #(SOC_SYSCTRL_DSCR3 - SOC_SYSCTRL_BASE)]
495 str r1, [r0, #(SOC_SYSCTRL_DSCR5 - SOC_SYSCTRL_BASE)]
496 str r1, [r0, #(SOC_SYSCTRL_DSCR6 - SOC_SYSCTRL_BASE)]
497 ldr r1, DS_0x00005005
498 str r1, [r0, #(SOC_SYSCTRL_DSCR7 - SOC_SYSCTRL_BASE)]
499 ldr r1, DS_0x15555555
500 str r1, [r0, #(SOC_SYSCTRL_DSCR8 - SOC_SYSCTRL_BASE)]
501 .endm // init_drive_strength
503 .macro setup_sdram_ddr
504 ldr r0, SOC_ESDCTL_BASE_W
505 mov r2, #SOC_CSD0_BASE
506 mov r1, #0x8 // initial reset
508 // Hold for more than 200ns
517 //Check The chip version TO1 or TO2
518 ldr r1, SOC_SI_ID_REG_W
520 ands r1, r1, #0xF0000000
521 // add Latency on CAS only for TO2
522 ldreq r1, SDRAM_0x00795729
523 ldrne r1, SDRAM_0x00795429
526 ldr r1, SDRAM_0x92200000
529 ldr r1, SDRAM_0xA2200000
533 ldr r1, SDRAM_0xB2200000
536 add r3, r2, #0x1000000
538 ldr r1, SDRAM_0x82228485
540 .endm // setup_sdram_ddr
542 .macro do_wait_op_done
544 ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
545 ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
548 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
549 .endm // do_wait_op_done
553 strh r3, [r12, #NAND_FLASH_ADD_REG_OFF]
554 mov r3, #NAND_FLASH_CONFIG2_FADD_EN
555 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
557 .endm // do_addr_input
559 #define PLATFORM_VECTORS _platform_vectors
560 .macro _platform_vectors
561 .globl _board_BCR, _board_CFG
562 _board_BCR: .long 0 // Board Control register shadow
563 _board_CFG: .long 0 // Board Configuration (read at RESET)
566 MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
567 CONST_0xFFF: .word 0xFFF
568 AVIC_VECTOR0_ADDR_W: .word MXCBOOT_FLAG_REG
569 AVIC_VECTOR1_ADDR_W: .word MXCFIS_FLAG_REG
570 SOC_SYSCTRL_BASE_W: .word SOC_SYSCTRL_BASE
571 SOC_MAX_BASE_W: .word SOC_MAX_BASE
572 SOC_MAX_0x00302145: .word 0x00302145
573 SOC_CRM_BASE_W: .word SOC_CRM_BASE
574 CRM_MPCTL0_VAL_W: .word CRM_MPCTL0_VAL
575 CRM_SPCTL0_VAL_W: .word CRM_SPCTL0_VAL
576 CRM_MPCTL0_VAL_27MHZ_W: .word CRM_MPCTL0_VAL_27MHZ
577 CRM_SPCTL0_VAL_27MHZ_W: .word CRM_SPCTL0_VAL_27MHZ
578 SOC_CRM_CSCR_W: .word CRM_CSCR_VAL
579 CRM_MPCTL0_VAL2_W: .word CRM_MPCTL0_VAL2
580 CRM_SPCTL0_VAL2_W: .word CRM_SPCTL0_VAL2
581 CRM_MPCTL0_VAL2_27MHZ_W: .word CRM_MPCTL0_VAL2_27MHZ
582 CRM_SPCTL0_VAL2_27MHZ_W: .word CRM_SPCTL0_VAL2_27MHZ
583 SOC_CRM_CSCR2_W: .word CRM_CSCR_VAL2
584 SOC_CRM_PCDR1_W: .word 0x09030913 // p1=20 p2=10 p3=4 p4=10
585 SOC_CRM_PCCR0_W: .word 0x3108480F
586 SOC_CS4_CTL_BASE_W: .word SOC_CS4_CTL_BASE
587 CS4_CSCRU_0x0000DCF6: .word 0x0000DCF6
588 CS4_CSCRL_0x444A4541: .word 0x444A4541
589 CS4_CSCRA_0x44443302: .word 0x44443302
590 NFC_BASE_W: .word NFC_BASE
591 SOC_ESDCTL_BASE_W: .word SOC_ESDCTL_BASE
592 SDRAM_0x00795429: .word 0x00795429
593 SDRAM_0x00795729: .word 0x00795729
594 SDRAM_0x92200000: .word 0x92200000
595 SDRAM_0xA2200000: .word 0xA2200000
596 SDRAM_0xB2200000: .word 0xB2200000
597 SDRAM_0x82228485: .word 0x82228485
598 CS0_0x0000CC03: .word 0x0000CC03
599 CS0_0xA0330D01: .word 0xA0330D01
600 CS0_0x00220800: .word 0x00220800
601 CS0_0x23524E80: .word 0x23524E80
602 CS0_0x10000D03: .word 0x10000D03
603 CS0_0x00720900: .word 0x00720900
604 CS0_CMD_0xAAA: .word 0x0AAA
605 CS0_CMD_0x554: .word 0x0554
606 CS0_CFG_0x66CA: .word 0x66CA
607 CS0_BASE_ADDR_W: .word CS0_BASE_ADDR
608 SOC_CS0_CTL_BASE_W: .word SOC_CS0_CTL_BASE
609 DS_0x55555555: .word 0x55555555
610 DS_0x00005005: .word 0x00005005
611 DS_0x15555555: .word 0x15555555
612 AIPI1_0x20040304: .word 0x20040304
613 AIPI1_0xDFFBFCFB: .word 0xDFFBFCFB
614 PBC_BASE_W: .word PBC_BASE
615 SOC_SI_ID_REG_W: .word SOC_SI_ID_REG
617 /*---------------------------------------------------------------------------*/
618 /* end of hal_platform_setup.h */
619 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */