1 //==========================================================================
5 // HAL misc board support code for the board
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
15 // Software Foundation; either version 2 or (at your option) any later version.
17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
29 // by itself cause the resulting work to be covered by the GNU General Public
30 // License. However the source code for this file must still be made available
31 // in accordance with section (3) of the GNU General Public License.
33 // This exception does not invalidate any other reasons why a work based on
34 // this file might be covered by the GNU General Public License.
36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //========================================================================*/
43 #include <pkgconf/hal.h>
44 #include <pkgconf/system.h>
45 #include CYGBLD_HAL_PLATFORM_H
47 #include <cyg/infra/cyg_type.h> // base types
48 #include <cyg/infra/cyg_trac.h> // tracing macros
49 #include <cyg/infra/cyg_ass.h> // assertion macros
51 #include <cyg/hal/hal_io.h> // IO macros
52 #include <cyg/hal/hal_arch.h> // Register state info
53 #include <cyg/hal/hal_diag.h>
54 #include <cyg/hal/hal_intr.h> // Interrupt names
55 #include <cyg/hal/hal_cache.h>
56 #include <cyg/hal/hal_soc.h> // Hardware definitions
57 #include <cyg/hal/fsl_board.h> // Platform specifics
59 #include <cyg/infra/diag.h> // diag_printf
61 // All the MM table layout is here:
62 #include <cyg/hal/hal_mm.h>
64 externC void* memset(void *, int, size_t);
66 void hal_mmu_init(void)
68 unsigned long ttb_base = RAM_BANK0_BASE + 0x4000;
72 * Set the TTB register
74 asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
77 * Set the Domain Access Control Register
79 i = ARM_ACCESS_DACR_DEFAULT;
80 asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
83 * First clear all TT entries - ie Set them to Faulting
85 memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
87 /* Actual Virtual Size Attributes Function */
88 /* Base Base MB cached? buffered? access permissions */
89 /* xxx00000 xxx00000 */
90 X_ARM_MMU_SECTION(0x000, 0xF00, 0x001, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Boot Rom */
91 X_ARM_MMU_SECTION(0x100, 0x100, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Internal Regsisters */
92 X_ARM_MMU_SECTION(0x800, 0x800, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CSI/ATA Regsisters */
93 X_ARM_MMU_SECTION(0xA00, 0x000, 0x080, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
94 X_ARM_MMU_SECTION(0xA00, 0xA00, 0x080, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
95 X_ARM_MMU_SECTION(0xA00, 0xA80, 0x080, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
96 X_ARM_MMU_SECTION(0xC00, 0xC00, 0x020, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Flash */
97 X_ARM_MMU_SECTION(0xD40, 0xD40, 0x020, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS4 for External I/O */
98 X_ARM_MMU_SECTION(0xD60, 0xD60, 0x020, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS5 PSRAM */
99 X_ARM_MMU_SECTION(0xD80, 0xD80, 0x100, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* EMI control/PCMCIA */
100 X_ARM_MMU_SECTION(0xFFF, 0xFFF, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* VRAM */
104 // Platform specific initialization
106 static void fec_gpio_init(void)
108 unsigned long addr , val;
111 addr = SOC_GPIOF_BASE;
113 HAL_READ_UINT32(addr+GPIO_OCR2, val);
114 val = val & (~(0x00000003<<(13)));
115 HAL_WRITE_UINT32(addr+GPIO_OCR2, val);
118 HAL_READ_UINT32(addr+GPIO_DDIR, val);
119 val = val | (0x00000001<<(23));
120 HAL_WRITE_UINT32(addr+GPIO_DDIR, val);
123 HAL_READ_UINT32(addr+GPIO_GIUS, val);
124 val = val | (0x00000001<<23);
125 HAL_WRITE_UINT32(addr+GPIO_GIUS, val);
128 addr = SOC_GPIOD_BASE;
129 /* PD16 OCR2: AIN=0x00 */
130 HAL_READ_UINT32(addr+GPIO_OCR2, val);
131 val = val & ~0x00000003;
132 HAL_WRITE_UINT32(addr+GPIO_OCR2, val);
134 /* PD9, 3-0 OCR1: AIN=0x00 */
135 HAL_READ_UINT32(addr+GPIO_OCR1, val);
136 val = val & ~(0x000C00FF);
137 HAL_WRITE_UINT32(addr+GPIO_OCR1, val);
139 /* PD15~10, P7~4 ICONFIGA1: AOUT=0x00 */
140 HAL_READ_UINT32(addr+GPIO_ICONFA1, val);
141 val = val & ~(0xFFF0FF00);
142 HAL_WRITE_UINT32(addr+GPIO_ICONFA1, val);
145 HAL_READ_UINT32(addr+GPIO_GPR, val);
146 val = val | 0x00000100;
147 HAL_WRITE_UINT32(addr+GPIO_GPR, val);
150 HAL_READ_UINT32(addr+GPIO_DDIR, val);
151 val = (val & 0xFFFE0000) | 0x0001020F;
152 HAL_WRITE_UINT32(addr+GPIO_DDIR, val);
155 HAL_READ_UINT32(addr+GPIO_GIUS, val);
156 val = (val & 0xFFFE0000) | 0x0001FEFF;
157 HAL_WRITE_UINT32(addr+GPIO_GIUS, val);
161 void fec_cpld_init(void)
163 unsigned long addr, val;
167 //Select FEC data through data path
169 HAL_WRITE_UINT16(addr+0x10, val);
171 //Enable CPLD FEC data path
173 HAL_WRITE_UINT16(addr+0x14, val);
177 // Platform specific initialization
180 unsigned int g_clock_src;
181 unsigned int g_board_type = BOARD_TYPE_UNKNOWN;
183 void plf_hardware_init(void)
185 unsigned long val = readl(SOC_CRM_CSCR);
187 if ((val & (1 << 16)) != 0) {
188 if ((readw(PBC_BASE + PBC_VERSION) & CLK_INPUT_27MHZ_SET) == 0) {
189 g_clock_src = FREQ_27MHZ;
191 g_clock_src = FREQ_26MHZ;
194 g_clock_src = FREQ_32768HZ;
197 if ((BOARD_PBC_VERSION & 0x80) != 0) {
198 g_board_type = BOARD_TYPE_ADS;
200 if ((BOARD_PBC_VERSION & 0x40) != 0) {
201 g_board_type = BOARD_TYPE_EVB_B;
203 g_board_type = BOARD_TYPE_EVB_A;
211 static void board_raise_voltage(void)
213 #if defined (CLOCK_399_133_66)
214 /* Increase core voltage to 1.45 */
215 setCoreVoltage(0x16);
219 RedBoot_init(board_raise_voltage, RedBoot_INIT_PRIO(101));
221 #include CYGHWR_MEMORY_LAYOUT_H
223 typedef void code_fun(void);
225 void board_program_new_stack(void *func)
227 register CYG_ADDRESS stack_ptr asm("sp");
228 register CYG_ADDRESS old_stack asm("r4");
229 register code_fun *new_func asm("r0");
230 old_stack = stack_ptr;
231 stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
232 new_func = (code_fun*)func;
234 stack_ptr = old_stack;
237 static void display_clock_src(void)
239 if (g_clock_src == FREQ_27MHZ) {
240 diag_printf("Clock input: 27 MHz");
241 } else if (g_clock_src == FREQ_26MHZ) {
242 diag_printf("Clock input: 26 MHz");
243 } else if (g_clock_src == FREQ_32768HZ) {
244 diag_printf("Clock input: 32KHz");
246 diag_printf("Unknown clock input source. Something is wrong!");
250 static void display_board_type(void)
252 if (g_board_type == BOARD_TYPE_ADS) {
253 diag_printf("\nBoard Type: ADS\n");
254 } else if (g_board_type == BOARD_TYPE_EVB_A) {
255 diag_printf("\nBoard Type: EVB [rev A] (external UART doesn't work)\n");
256 } else if (g_board_type == BOARD_TYPE_EVB_B) {
257 diag_printf("\nBoard Type: EVB [rev AA/B]\n");
259 diag_printf("\nBoard Type: Unknown val %d\n", g_board_type);
263 static void display_board_info(void)
265 display_board_type();
269 RedBoot_init(display_board_info, RedBoot_INIT_LAST);
270 // ------------------------------------------------------------------------