1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 //=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
16 // eCos is free software; you can redistribute it and/or modify it under
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30 // or inline functions from this file, or you compile this file and link it
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41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //===========================================================================
45 #include <pkgconf/system.h> // System-wide configuration info
46 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
47 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
48 #include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
49 #include <cyg/hal/hal_mmu.h> // MMU definitions
50 #include <cyg/hal/karo_tx27.h> // Platform specific hardware definitions
51 #include CYGHWR_MEMORY_LAYOUT_H
53 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
54 #define PLATFORM_SETUP1 _platform_setup1
55 #define CYGHWR_HAL_ARM_HAS_MMU
57 #ifdef CYG_HAL_STARTUP_ROMRAM
58 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
61 #define TX27_NAND_PAGE_SIZE 2048
62 #define TX27_NAND_BLKS_PER_PAGE 64
64 #define CYGHWR_HAL_ROM_VADDR 0x0
66 #ifndef CYGOPT_HAL_ARM_TX27_DEBUG
76 #define CYGHWR_LED_MACRO LED_BLINK #\x
77 #define LED_ON bl led_on
78 #define LED_OFF bl led_off
94 // switch user LED (PF13) on STK5
99 movne r9, #(1 << 13) // LED ON
100 moveq r9, #0 // LED OFF
101 str r9, [r10, #GPIO_DR]
120 // initialize GPIO PF13 for LED on STK5
123 mov r9, #(3 << (2 * 13))
124 str r9, [r10, #GPIO_OCR1]
126 ldr r9, [r10, #GPIO_GIUS]
127 orr r9, r9, #(1 << 13)
128 str r9, [r10, #GPIO_GIUS]
131 str r9, [r10, #GPIO_DDIR]
134 // This macro represents the initial startup code for the platform
135 // r11 is reserved to contain chip rev info in this file
136 .macro _platform_setup1
137 KARO_TX27_SETUP_START:
138 // invalidate I/D cache/TLB
140 mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
141 mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
142 mcr 15, 0, r0, c7, c10, 4 /* Data Write Barrier */
147 /* configure GPIO PB22 (OSC26M enable) as output high */
151 mov r9, #(3 << (2 * (22 - 16)))
152 str r9, [r10, #GPIO_OCR2]
154 ldr r9, [r10, #GPIO_DR]
155 orr r9, r9, #(1 << 22)
156 str r9, [r10, #GPIO_DR]
158 ldr r9, [r10, #GPIO_GIUS]
159 orr r9, r9, #(1 << 22)
160 str r9, [r10, #GPIO_GIUS]
163 str r9, [r10, #GPIO_DDIR]
167 // setup System Controls
168 ldr r0, SOC_SYSCTRL_BASE_W
170 str r1, [r0, #(SOC_SYSCTRL_PCSR - SOC_SYSCTRL_BASE)]
171 // select 2kpage NAND (NF_FMS), CSD0, CS3
172 mvn r1, #(FMCR_SDCS1_SEL | FMCR_NF_16BIT | FMCR_SLCDC_SEL)
173 str r1, [r0, #(SOC_SYSCTRL_FMCR - SOC_SYSCTRL_BASE)]
177 init_drive_strength_start:
180 // check if sdram has been setup
181 cmp pc, #SDRAM_BASE_ADDR
183 cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
184 blo HWInitialise_skip_SDRAM_setup
192 HWInitialise_skip_SDRAM_setup:
194 add r2, r0, #0x800 // 2K window
196 blo Normal_Boot_Continue
198 bhi Normal_Boot_Continue
201 /* Copy image from flash to SDRAM first */
202 ldr r1, MXC_REDBOOT_RAM_START
210 ldr r1, MXC_REDBOOT_RAM_START
231 ldr r0, NFC_BASE_W //r0: nfc base. Reloaded after each page copying
232 mov r1, #TX27_NAND_PAGE_SIZE //r1: starting flash addr to be copied. Updated constantly
233 add r2, r0, #TX27_NAND_PAGE_SIZE //r2: end of 1st RAM buf. Doesn't change
234 add r4, r0, #0xE00 //r4: NFC register base. Doesn't change
235 ldr r5, MXC_REDBOOT_RAM_START
236 add r6, r5, #REDBOOT_IMAGE_SIZE //r6: end of SDRAM address for copying. Doesn't change
237 add r5, r5, r1 //r5: starting SDRAM address for copying. Updated constantly
239 // enable ECC, disable interrupts
240 mov r3, #(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN)
241 strh r3, [r4, #NAND_FLASH_CONFIG1_REG_OFF]
243 //unlock internal buffer
250 strh r8, [r4, #RAM_BUFFER_ADDRESS_REG_OFF]
260 bl nfc_addr_input //2nd addr cycle
263 bl nfc_addr_input //3rd addr cycle
266 bl nfc_addr_input //4th addr cycle
275 strh r8, [r4, #RAM_BUFFER_ADDRESS_REG_OFF]
278 strh r8, [r4, #RAM_BUFFER_ADDRESS_REG_OFF]
281 strh r8, [r4, #RAM_BUFFER_ADDRESS_REG_OFF]
284 // check for bad block
285 mov r3, r1, lsl #(32-17) // get rid of block number
286 cmp r3, #(TX27_NAND_PAGE_SIZE << (32-17)) // check if not first or second page in block
291 add r9, r0, #TX27_NAND_PAGE_SIZE //r3 -> spare area buf 0
296 // really sucks. Bad block!!!!
299 // even suckier since we already read the first page!
300 sub r5, r5, #TX27_NAND_PAGE_SIZE //rewind 1 page for the sdram pointer
301 sub r1, r1, #TX27_NAND_PAGE_SIZE //rewind 1 page for the flash pointer
303 #ifdef CYGOPT_HAL_ARM_TX27_DEBUG
307 add r1, r1, #(TX27_NAND_BLKS_PER_PAGE*TX27_NAND_PAGE_SIZE)
321 bge NAND_Copy_Main_done
323 add r1, r1, #TX27_NAND_PAGE_SIZE
328 Normal_Boot_Continue:
330 // Code and all data used up to here must fit within the first 2KiB of FLASH ROM!
331 #ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
332 /* Copy image from flash to SDRAM first */
335 ldr r1, MXC_REDBOOT_RAM_START
337 beq HWInitialise_skip_SDRAM_copy
339 add r2, r0, #REDBOOT_IMAGE_SIZE
349 #endif /* CYG_HAL_STARTUP_ROMRAM */
351 HWInitialise_skip_SDRAM_copy:
358 ldr r1, =(SOC_CRM_BASE)
359 ldr r2, [r1, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
362 ldr r1, =(SOC_CRM_BASE)
363 str r2, [r1, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
365 /* end of NAND clock divider setup */
367 // TLSbo76381: enable USB/PP/DMA burst override bits in GPCR
368 ldr r1, =(SOC_SYSCTRL_GPCR)
373 // Set up a stack [for calling C code]
374 ldr r1, =__startup_stack
375 ldr r2, =RAM_BANK0_BASE
385 mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
386 orr r1, r1, #7 // enable MMU bit
387 mcr MMU_CP, 0, r1, MMU_Control, c0
391 mov pc,r2 /* Change address spaces */
394 .endm // _platform_setup1
396 #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
397 #define PLATFORM_SETUP1
401 ldr r0, SOC_CRM_BASE_W
402 // disable MPLL/SPLL first
403 ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
405 str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
408 ldr r1, CRM_MPCTL0_VAL2_W
409 str r1, [r0, #(SOC_CRM_MPCTL0 - SOC_CRM_BASE)]
412 ldr r1, CRM_SPCTL0_VAL2_W
413 str r1, [r0, #(SOC_CRM_SPCTL0 - SOC_CRM_BASE)]
415 ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
416 #ifdef PLL_REF_CLK_32768HZ
417 // Make sure to use CKIL
418 bic r1, r1, #(3 << 16)
420 orr r1, r1, #(3 << 16) // select 26MHz
422 orr r1, r1, #0x000C0000 // restart SPLL and MPLL
423 orr r1, r1, #0x00000003 // enable SPLL and MPLL
424 str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
426 // add some delay here
432 ldr r1, SOC_CRM_CSCR2_W
433 str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
435 // Set divider of H264_CLK to zero, NFC to 3.
436 ldr r1, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
437 bic r1, r1, #0x0000FC00
438 str r1, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
440 /* Configure PCDR1 */
441 ldr r1, SOC_CRM_PCDR1_W
442 str r1, [r0, #(SOC_CRM_PCDR1 - SOC_CRM_BASE)]
444 // Configure PCCR0 and PCCR1
445 ldr r1, SOC_CRM_PCCR0_W
446 str r1, [r0, #(SOC_CRM_PCCR0 - SOC_CRM_BASE)]
448 ldr r1, [r0, #(SOC_CRM_PCCR1 - SOC_CRM_BASE)]
450 str r1, [r0, #(SOC_CRM_PCCR1 - SOC_CRM_BASE)]
451 // make default CLKO to be FCLK
452 ldr r1, [r0, #(SOC_CRM_CCSR - SOC_CRM_BASE)]
453 and r1, r1, #0xFFFFFFE0
455 str r1, [r0, #(SOC_CRM_CCSR - SOC_CRM_BASE)]
459 ldr r1, SOC_CS0_CTL_BASE_W
460 ldr r2, CS0_CSCRU_VAL
461 str r2, [r1, #CSCRU_OFFSET]
462 ldr r2, CS0_CSCRL_VAL
463 str r2, [r1, #CSCRL_OFFSET]
464 ldr r2, CS0_CSCRA_VAL
465 str r2, [r1, #CSCRA_OFFSET]
468 /* CS0 sync mode setup */
471 * Sync mode (AHB Clk = 133MHz ; BCLK = 44.3MHz):
473 ldr r0, =SOC_CS0_CTL_BASE
474 ldr r1, CS0_CSCRU_SYNC_VAL
475 str r1, [r0, #CSCRU_OFFSET]
476 ldr r1, CS0_CSCRL_SYNC_VAL
477 str r1, [r0, #CSCRL_OFFSET]
478 ldr r1, CS0_CSCRA_SYNC_VAL
479 str r1, [r0, #CSCRA_OFFSET]
480 .endm /* init_cs0_sync */
482 .macro init_cs4 /* ADS board expanded IOs */
483 ldr r1, SOC_CS4_CTL_BASE_W
484 ldr r2, CS4_CSCRU_VAL
485 str r2, [r1, #CSCRU_OFFSET]
486 ldr r2, CS4_CSCRL_VAL
487 str r2, [r1, #CSCRL_OFFSET]
488 ldr r2, CS4_CSCRA_VAL
489 str r2, [r1, #CSCRA_OFFSET]
493 // setup AIPI1 and AIPI2
494 mov r0, #SOC_AIPI1_BASE
495 ldr r1, AIPI1_PSR0_VAL
496 str r1, [r0] /* PSR0 */
497 ldr r2, AIPI1_PSR1_VAL
498 str r2, [r0, #4] /* PSR1 */
499 // set r0 = AIPI2 base
502 str r1, [r0] /* PSR0 */
504 str r2, [r0, #4] /* PSR1 */
508 ldr r0, SOC_MAX_BASE_W
509 add r1, r0, #MAX_SLAVE_PORT1_OFFSET
510 add r2, r0, #MAX_SLAVE_PORT2_OFFSET
511 add r0, r0, #MAX_SLAVE_PORT0_OFFSET
514 ldr r6, SOC_MAX_MPR_VAL /* Priority SLCD>EMMA>DMA>Codec>DAHB>IAHB */
515 str r6, [r0, #MAX_SLAVE_MPR_OFFSET] /* same for all slave ports */
516 str r6, [r0, #MAX_SLAVE_AMPR_OFFSET]
517 str r6, [r1, #MAX_SLAVE_MPR_OFFSET]
518 str r6, [r1, #MAX_SLAVE_AMPR_OFFSET]
519 str r6, [r2, #MAX_SLAVE_MPR_OFFSET]
520 str r6, [r2, #MAX_SLAVE_AMPR_OFFSET]
523 .macro init_drive_strength
524 ldr r0, SOC_SYSCTRL_BASE_W
526 str r1, [r0, #(SOC_SYSCTRL_DSCR3 - SOC_SYSCTRL_BASE)]
527 str r1, [r0, #(SOC_SYSCTRL_DSCR5 - SOC_SYSCTRL_BASE)]
528 str r1, [r0, #(SOC_SYSCTRL_DSCR6 - SOC_SYSCTRL_BASE)]
530 str r1, [r0, #(SOC_SYSCTRL_DSCR7 - SOC_SYSCTRL_BASE)]
532 str r1, [r0, #(SOC_SYSCTRL_DSCR8 - SOC_SYSCTRL_BASE)]
533 .endm // init_drive_strength
535 .macro setup_sdram_ddr
536 // SDRAM controller base address
537 ldr r0, SOC_ESDCTL_BASE_W
538 // base address of SDRAM for SET MODE commands written to SDRAM via address lines
539 mov r2, #SOC_CSD0_BASE
541 mov r1, #(1 << 1) // SDRAM controller reset
542 str r1, [r0, #ESDCTL_ESDMISC]
544 // wait until SDRAMRDY bit is set indicating SDRAM is usable
545 ldr r1, [r0, #ESDCTL_ESDMISC]
549 mov r1, #(1 << 3) @ delay line soft reset
550 str r1, [r0, #ESDCTL_ESDMISC]
552 // wait until SDRAMRDY bit is set indicating SDRAM is usable
553 ldr r1, [r0, #ESDCTL_ESDMISC]
557 mov r1, #(1 << 2) @ enable DDR pipeline
558 str r1, [r0, #ESDCTL_ESDMISC]
560 ldr r1, SDRAM_ESDCFG0_VAL
561 str r1, [r0, #ESDCTL_ESDCFG0]
563 ldr r1, SDRAM_DLY_VAL
564 str r1, [r0, #ESDCTL_ESDCDLY1]
565 str r1, [r0, #ESDCTL_ESDCDLY2]
566 str r1, [r0, #ESDCTL_ESDCDLY3]
567 str r1, [r0, #ESDCTL_ESDCDLY4]
568 str r1, [r0, #ESDCTL_ESDCDLY5]
570 ldr r1, SDRAM_PRE_ALL_CMD
571 str r1, [r0, #ESDCTL_ESDCTL0]
573 str r1, [r2, #(1 << 10)] @ contents of r1 irrelevant, data written via A0-A11
575 ldr r1, SDRAM_AUTO_REF_CMD
576 str r1, [r0, #ESDCTL_ESDCTL0]
577 @ initiate 2 auto refresh cycles
582 ldr r1, SDRAM_SET_MODE_REG_CMD
583 str r1, [r0, #ESDCTL_ESDCTL0]
585 @ address offset for extended mode register
586 add r3, r2, #(2 << 24)
587 @ select drive strength via extended mode register:
588 @ 0=full 1=half 2=quarter 3=3-quarter
589 ldrb r1, [r2, #(0 << 5)]
591 ldrb r1, [r2, #0x033] @ write to SDRAM MODE register (via A0-A12)
593 ldr r1, SDRAM_NORMAL_MODE
594 str r1, [r0, #ESDCTL_ESDCTL0]
597 mov r1, #((1 << 3) | (1 << 2) | (1 << 5))
598 str r1, [r0, #ESDCTL_ESDMISC]
599 .endm // setup_sdram_ddr
601 #ifdef CYGOPT_HAL_ARM_TX27_DEBUG
605 mov r9, #(1 << 13) // LED ON
606 str r9, [r10, #GPIO_DR]
612 mov r9, #0 // LED OFF
613 str r9, [r10, #GPIO_DR]
618 strh r3, [r4, #NAND_FLASH_CMD_REG_OFF]
619 mov r3, #NAND_FLASH_CONFIG2_FCMD_EN
620 strh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
625 strh r3, [r4, #NAND_FLASH_ADD_REG_OFF]
626 mov r3, #NAND_FLASH_CONFIG2_FADD_EN
627 strh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
631 mov r3, #FDO_PAGE_SPARE_VAL
632 strh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
638 ldrh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
639 ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
641 strneh r3, [r4, #NAND_FLASH_CONFIG2_REG_OFF]
649 mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
650 mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
651 mcr 15, 0, r0, c7, c10, 4 /* Data Write Barrier */
652 ldr r0, SDRAM_ADDR_MASK
653 ldr r1, MXC_REDBOOT_RAM_START
659 #define PLATFORM_VECTORS _platform_vectors
660 .macro _platform_vectors
664 .globl _KARO_STRUCT_SIZE
666 .word 0 // reserve space structure length
668 .globl _KARO_CECFG_START
671 .word 0 // reserve space for CE configuration
674 .globl _KARO_CECFG_END
679 .ascii "KARO TX27 " __DATE__ " " __TIME__
682 /* SDRAM configuration */
683 #define RA_BITS 2 /* row addr bits - 11 */
684 #define CA_BITS (SDRAM_SIZE / SZ_64M) /* 0-2: col addr bits - 8 3: rsrvd */
685 #define DSIZ 2 /* 0: D[31..16] 1: D[15..D0] 2: D[31..0] 3: rsrvd */
686 #define SREFR 3 /* 0: disabled 1-5: 2^n rows/clock *: rsrvd */
687 #define PWDT 1 /* 0: disabled 1: precharge pwdn
688 2: pwdn after 64 clocks 3: pwdn after 128 clocks */
689 #define FP 0 /* 0: not full page 1: full page */
690 #define BL 1 /* 0: 4(not for LPDDR) 1: 8 */
691 #define PRCT 5 /* 0: disabled *: clks / 2 (0..63) */
692 #define ESDCTLVAL (0x80000000 | (RA_BITS << 24) | (CA_BITS << 20) | \
693 (DSIZ << 16) | (SREFR << 13) | (PWDT << 10) | (FP << 8) | \
694 (BL << 7) | (PRCT << 0))
696 /* SDRAM timing definitions */
697 #define SDRAM_CLK 133
698 #define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
700 .macro CK_VAL, name, clks, offs
705 .set \name, \clks - \offs
712 .macro NS_VAL, name, ns, offs
716 CK_VAL \name, NS_TO_CK(\ns), \offs
720 #if SDRAM_SIZE <= SZ_64M
721 /* MT46H16M32LF-75 */
722 CK_VAL tXP, 2, 1 /* clks - 1 (0..7) */
723 CK_VAL tWTR, 2, 1 /* clks - 1 (0..1) */
724 NS_VAL tRP, 23, 2 /* clks - 2 (0..3) */
725 CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */
726 NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */
727 NS_VAL tRAS, 45, 1 /* clks - 1 (0..15) */
728 CK_VAL tCAS, 3, 0 /* clks - 1 (0..3) */
729 NS_VAL tRRD, 15, 1 /* clks - 1 (0..3) */
730 NS_VAL tRCD, 23, 1 /* clks - 1 (0..7) */
731 /* tRC is actually max(tRC,tRFC,tXSR) */
732 NS_VAL tRC, 120, 1 /* 0: 20 *: clks - 1 (0..15) */
734 /* MT46H32M32LF-6 or -75 */
735 NS_VAL tXP, 25, 1 /* clks - 1 (0..7) */
736 CK_VAL tWTR, 1, 1 /* clks - 1 (0..1) */
737 NS_VAL tRP, 23, 2 /* clks - 2 (0..3) */
738 CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */
739 NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */
740 NS_VAL tRAS, 45, 1 /* clks - 1 (0..15) */
741 CK_VAL tCAS, 3, 0 /* clks - 1 (0..3) */
742 NS_VAL tRRD, 15, 1 /* clks - 1 (0..3) */
743 NS_VAL tRCD, 23, 1 /* clks - 1 (0..7) */
744 NS_VAL tRC, 138, 1 /* 0: 20 *: clks - 1 (0..15) */
747 #define ESDCFGVAL ((tXP << 21) | (tWTR << 20) | (tRP << 18) | (tMRD << 16) | \
748 (tWR << 15) | (tRAS << 12) | (tRRD << 10) | (tCAS << 8) | \
749 (tRCD << 4) | (tRC << 0))
751 // All these constants need to be in the first 2KiB of FLASH
752 GPIOB_BASE: .word 0x10015100
753 GPIOF_BASE: .word 0x10015500
754 SDRAM_ADDR_MASK: .word 0xffff0000
755 MXC_REDBOOT_RAM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - REDBOOT_OFFSET
756 SOC_SYSCTRL_BASE_W: .word SOC_SYSCTRL_BASE
757 SOC_MAX_BASE_W: .word SOC_MAX_BASE
758 SOC_MAX_MPR_VAL: .word 0x00302145
759 SOC_CRM_BASE_W: .word SOC_CRM_BASE
760 CRM_MPCTL0_VAL2_W: .word CRM_MPCTL0_VAL2
761 CRM_SPCTL0_VAL2_W: .word CRM_SPCTL0_VAL2
762 SOC_CRM_CSCR2_W: .word CRM_CSCR_VAL2
763 SOC_CRM_PCDR1_W: .word 0x09030913 // p1=20 p2=10 p3=4 p4=10
764 SOC_CRM_PCCR0_W: .word 0x3108480F
765 SOC_CS4_CTL_BASE_W: .word SOC_CS4_CTL_BASE
766 CS4_CSCRU_VAL: .word 0x0000DCF6
767 CS4_CSCRL_VAL: .word 0x444A4541
768 CS4_CSCRA_VAL: .word 0x44443302
769 NFC_BASE_W: .word NFC_BASE
770 SOC_ESDCTL_BASE_W: .word SOC_ESDCTL_BASE
771 SDRAM_ESDCFG0_VAL: .word ESDCFGVAL
772 SDRAM_DLY_VAL: .word 0x002c0000
773 SDRAM_PRE_ALL_CMD: .word 0x92120000
774 SDRAM_AUTO_REF_CMD: .word 0xA2120000
775 SDRAM_SET_MODE_REG_CMD: .word 0xB2120000
776 SDRAM_NORMAL_MODE: .word ESDCTLVAL
777 CS0_CSCRU_VAL: .word 0x0000CC03
778 CS0_CSCRL_VAL: .word 0xA0330D01
779 CS0_CSCRA_VAL: .word 0x00220800
780 CS0_CSCRU_SYNC_VAL: .word 0x23524E80
781 CS0_CSCRL_SYNC_VAL: .word 0x10000D03
782 CS0_CSCRA_SYNC_VAL: .word 0x00720900
783 CS0_BASE_ADDR_W: .word CS0_BASE_ADDR
784 SOC_CS0_CTL_BASE_W: .word SOC_CS0_CTL_BASE
785 DS_DSCR_VAL: .word 0x55555555
786 DS_DSCR7_VAL: .word 0x00005005
787 DS_DSCR8_VAL: .word 0x15555555
788 AIPI1_PSR0_VAL: .word 0x20040304
789 AIPI1_PSR1_VAL: .word 0xDFFBFCFB
791 /*----------------------------------------------------------------------*/
792 /* end of hal_platform_setup.h */
793 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */