1 //==========================================================================
5 // HAL misc board support code for the tx27
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
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38 // -------------------------------------------
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40 //========================================================================*/
44 #include <pkgconf/hal.h>
45 #include <pkgconf/system.h>
46 #include CYGBLD_HAL_PLATFORM_H
48 #include <cyg/infra/cyg_type.h> // base types
49 #include <cyg/infra/cyg_trac.h> // tracing macros
50 #include <cyg/infra/cyg_ass.h> // assertion macros
52 #include <cyg/hal/hal_io.h> // IO macros
53 #include <cyg/hal/hal_arch.h> // Register state info
54 #include <cyg/hal/hal_diag.h>
55 #include <cyg/hal/hal_intr.h> // Interrupt names
56 #include <cyg/hal/hal_cache.h>
57 #include <cyg/hal/hal_soc.h> // Hardware definitions
58 #include <cyg/hal/karo_tx27.h> // Platform specifics
60 #include <cyg/infra/diag.h> // diag_printf
62 // All the MM table layout is here:
63 #include <cyg/hal/hal_mm.h>
65 void hal_mmu_init(void)
67 unsigned long ttb_base = RAM_BANK0_BASE + 0x4000;
71 * Set the TTB register
73 asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
76 * Set the Domain Access Control Register
78 i = ARM_ACCESS_DACR_DEFAULT;
79 asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
82 * First clear all TT entries - ie Set them to Faulting
84 memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
86 /* Actual Virtual Size Attributes Function */
87 /* Base Base MB cached? buffered? access permissions */
88 /* xxx00000 xxx00000 */
89 X_ARM_MMU_SECTION(0x000, 0xF00, 0x001, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Boot Rom */
90 X_ARM_MMU_SECTION(0x100, 0x100, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Internal Registers */
91 X_ARM_MMU_SECTION(0x800, 0x800, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CSI/ATA Registers */
92 X_ARM_MMU_SECTION(0xA00, 0x000, TX27_SDRAM_SIZE >> 20, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
93 X_ARM_MMU_SECTION(0xA00, 0xA00, TX27_SDRAM_SIZE >> 20, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
94 X_ARM_MMU_SECTION(0xA00, 0xA80, TX27_SDRAM_SIZE >> 20, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
95 // X_ARM_MMU_SECTION(0xC00, 0xC00, 0x020, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Flash */
96 X_ARM_MMU_SECTION(0xD40, 0xD40, 0x020, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS4 for External I/O */
97 X_ARM_MMU_SECTION(0xD60, 0xD60, 0x020, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS5 PSRAM */
98 X_ARM_MMU_SECTION(0xD80, 0xD80, 0x100, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* EMI control/PCMCIA */
99 X_ARM_MMU_SECTION(0xFFF, 0xFFF, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* VRAM */
102 static inline void set_reg(unsigned long addr, CYG_WORD32 set, CYG_WORD32 clr)
105 HAL_READ_UINT32(addr, val);
106 val = (val & ~clr) | set;
107 HAL_WRITE_UINT32(addr, val);
111 // Platform specific initialization
113 static void fec_gpio_init(void)
115 /* GPIOs to set up for TX27/Starterkit-5:
116 Function GPIO Dir act. FCT
118 FEC_RESET PB30 OUT LOW GPIO
119 FEC_ENABLE PB27 OUT HIGH GPIO
120 OSCM26_ENABLE PB22 OUT HIGH GPIO
121 EXT_WAKEUP PB24 IN HIGH GPIO
122 FEC_TXEN PF23 OUT OUT AIN
123 FEC_TXCLK PD11 OUT IN AOUT
126 #define OCR_SHIFT(bit) (((bit) * 2) % 32)
127 #define OCR_MASK(bit) (3 << (OCR_SHIFT(bit)))
128 #define OCR_VAL(bit,val) (((val) << (OCR_SHIFT(bit))) & (OCR_MASK(bit)))
129 #define GPR_SHIFT(bit) (bit)
130 #define GPR_MASK(bit) (1 << (GPR_SHIFT(bit)))
131 #define GPR_VAL(bit,val) (((val) << (GPR_SHIFT(bit))) & (GPR_MASK(bit)))
132 #define ICONF_SHIFT(bit) (((bit) * 2) % 32)
133 #define ICONF_MASK(bit) (3 << (ICONF_SHIFT(bit)))
134 #define ICONF_VAL(bit,val) (((val) << (ICONF_SHIFT(bit))) & (ICONF_MASK(bit)))
137 * make sure the ETH PHY strap pins are pulled to the right voltage
138 * before deasserting the PHY reset GPIO
141 set_reg(SOC_GPIOD_BASE + GPIO_OCR1, 0xffffffff, 0);
142 set_reg(SOC_GPIOD_BASE + GPIO_DR, 0, 0xffff);
143 set_reg(SOC_GPIOD_BASE + GPIO_DDIR, 0xffff, 0);
144 set_reg(SOC_GPIOD_BASE + GPIO_GIUS, 0xffff, 0);
147 set_reg(SOC_GPIOD_BASE + GPIO_OCR2, OCR_MASK(16), 0);
148 set_reg(SOC_GPIOD_BASE + GPIO_DR, 0, GPR_MASK(16));
149 set_reg(SOC_GPIOD_BASE + GPIO_DDIR, GPR_MASK(16), 0);
150 set_reg(SOC_GPIOD_BASE + GPIO_GIUS, GPR_MASK(16), 0);
153 set_reg(SOC_GPIOF_BASE + GPIO_OCR2, OCR_MASK(23), 0);
154 set_reg(SOC_GPIOF_BASE + GPIO_DR, 0, GPR_MASK(23));
155 set_reg(SOC_GPIOF_BASE + GPIO_DDIR, GPR_MASK(23), 0);
156 set_reg(SOC_GPIOF_BASE + GPIO_GIUS, GPR_MASK(23), 0);
158 // assert FEC PHY Reset (PB30) and switch PHY power off
159 /* PB22, PB27, PB30 => GPIO out */
160 set_reg(SOC_GPIOB_BASE + GPIO_OCR2, OCR_MASK(27) | OCR_MASK(30), 0);
161 set_reg(SOC_GPIOB_BASE + GPIO_DR, 0, GPR_MASK(27) | GPR_MASK(30));
162 set_reg(SOC_GPIOB_BASE + GPIO_DDIR, GPR_MASK(27) | GPR_MASK(30), 0);
163 set_reg(SOC_GPIOB_BASE + GPIO_GIUS, GPR_MASK(27) | GPR_MASK(30), 0);
167 // Platform specific initialization
170 unsigned int g_clock_src;
171 unsigned int g_board_type = BOARD_TYPE_TX27KARO;
173 void plf_hardware_init(void)
175 g_clock_src = PLL_REF_CLK;
179 static void tx27_raise_voltage(void)
181 #if defined (CLOCK_399_133_66)
182 /* Increase core voltage to 1.45 */
183 setCoreVoltage(0x16);
187 RedBoot_init(tx27_raise_voltage, RedBoot_INIT_PRIO(101));
189 #include CYGHWR_MEMORY_LAYOUT_H
191 typedef void code_fun(void);
193 void tx27_program_new_stack(void *func)
195 register CYG_ADDRESS stack_ptr asm("sp");
196 register CYG_ADDRESS old_stack asm("r4");
197 register code_fun *new_func asm("r0");
198 old_stack = stack_ptr;
199 stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
200 new_func = (code_fun*)func;
202 stack_ptr = old_stack;
205 static void display_clock_src(void)
207 if (g_clock_src == FREQ_32000HZ) {
208 diag_printf("Clock input: 32kHz\n");
209 } else if (g_clock_src == FREQ_26MHZ) {
210 diag_printf("Clock input: 26MHz\n");
211 } else if (g_clock_src == FREQ_32768HZ) {
212 diag_printf("Clock input: 32.768kHz\n");
214 diag_printf("Unknown clock input source. Something is wrong!\n");
218 static void display_board_type(void)
220 diag_printf("\nBoard Type: Ka-Ro TX27\n");
223 static void display_board_info(void)
225 display_board_type();
229 RedBoot_init(display_board_info, RedBoot_INIT_LAST);
230 // ------------------------------------------------------------------------