1 //==-*- c-basic-offset: 4; tab-width: 4; -*-================================
5 // SoC chip definitions
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12 // Copyright (C) 2002 Gary Thomas
14 // eCos is free software; you can redistribute it and/or modify it under
15 // the terms of the GNU General Public License as published by the Free
16 // Software Foundation; either version 2 or (at your option) any later version.
18 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
23 // You should have received a copy of the GNU General Public License along
24 // with eCos; if not, write to the Free Software Foundation, Inc.,
25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 // As a special exception, if other files instantiate templates or use macros
28 // or inline functions from this file, or you compile this file and link it
29 // with other works to produce a work based on this file, this file does not
30 // by itself cause the resulting work to be covered by the GNU General Public
31 // License. However the source code for this file must still be made available
32 // in accordance with section (3) of the GNU General Public License.
34 // This exception does not invalidate any other reasons why a work based on
35 // this file might be covered by the GNU General Public License.
37 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
38 // at http://sources.redhat.com/ecos/ecos-license/
39 // -------------------------------------------
40 //####ECOSGPLCOPYRIGHTEND####
41 //========================================================================*/
46 #include <cyg/hal/mx27_pins.h>
50 #define REG8_VAL(a) (a)
51 #define REG16_VAL(a) (a)
52 #define REG32_VAL(a) (a)
54 #define REG8_PTR(a) (a)
55 #define REG16_PTR(a) (a)
56 #define REG32_PTR(a) (a)
58 #else /* __ASSEMBLER__ */
60 extern char HAL_PLATFORM_EXTRA[];
61 #define REG8_VAL(a) ((unsigned char)(a))
62 #define REG16_VAL(a) ((unsigned short)(a))
63 #define REG32_VAL(a) ((unsigned int)(a))
65 #define REG8_PTR(a) ((volatile unsigned char *)(a))
66 #define REG16_PTR(a) ((volatile unsigned short *)(a))
67 #define REG32_PTR(a) ((volatile unsigned int *)(a))
68 #define readb(a) (*(volatile unsigned char *)(a))
69 #define readw(a) (*(volatile unsigned short *)(a))
70 #define readl(a) (*(volatile unsigned int *)(a))
71 #define writeb(v,a) (*(volatile unsigned char *)(a) = (v))
72 #define writew(v,a) (*(volatile unsigned short *)(a) = (v))
73 #define writel(v,a) (*(volatile unsigned int *)(a) = (v))
75 #endif /* __ASSEMBLER__ */
77 // Default Memory Layout Definitions
79 #define SOC_AIPI1_BASE 0x10000000
80 #define SOC_AIPI2_BASE 0x10020000
82 #define SOC_AIPI_PAR_OFF 8
84 #define CSPI1_BASE_ADDR (SOC_AIPI1_BASE + 0x0E000)
85 #define CSPI2_BASE_ADDR (SOC_AIPI1_BASE + 0x0F000)
86 #define CSPI3_BASE_ADDR (SOC_AIPI1_BASE + 0x17000)
88 #define SOC_CRM_BASE 0x10027000
89 #define SOC_CRM_CSCR (SOC_CRM_BASE + 0x0)
90 #define SOC_CRM_MPCTL0 (SOC_CRM_BASE + 0x4)
91 #define SOC_CRM_MPCTL1 (SOC_CRM_BASE + 0x8)
92 #define SOC_CRM_SPCTL0 (SOC_CRM_BASE + 0xC)
93 #define SOC_CRM_SPCTL1 (SOC_CRM_BASE + 0x10)
94 #define SOC_CRM_OSC26MCTL (SOC_CRM_BASE + 0x14)
95 #define SOC_CRM_PCDR0 (SOC_CRM_BASE + 0x18)
96 #define SOC_CRM_PCDR1 (SOC_CRM_BASE + 0x1C)
97 #define SOC_CRM_PCCR0 (SOC_CRM_BASE + 0x20)
98 #define SOC_CRM_PCCR1 (SOC_CRM_BASE + 0x24)
99 #define SOC_CRM_CCSR (SOC_CRM_BASE + 0x28)
100 #define SOC_CRM_PMCTL (SOC_CRM_BASE + 0x2C)
101 #define SOC_CRM_PMCOUNT (SOC_CRM_BASE + 0x30)
102 #define SOC_CRM_WKGDCTL (SOC_CRM_BASE + 0x34)
104 #define CRM_CSCR_IPDIV_OFFSET 8
105 #define CRM_CSCR_BCLKDIV_OFFSET 9
106 #define CRM_CSCR_PRESC_OFFSET 13
107 #define CRM_CSCR_SSI1_SEL_OFFSET 22
108 #define CRM_CSCR_SSI2_SEL_OFFSET 23
109 #define CRM_CSCR_USB_DIV_OFFSET 28
111 #define CRM_CSCR_ARM_OFFSET 12
112 #define CRM_CSCR_ARM_SRC (1<<15)
113 #define CRM_CSCR_AHB_OFFSET 8
115 #define FREQ_26MHZ 26000000
116 #define FREQ_27MHZ 27000000
117 #define FREQ_32768HZ (32768 * 512 * 2)
118 #define FREQ_32000HZ (32000 * 512 * 2)
121 /* These should be defined in platform specific files */
122 //#define CLOCK_266_133_66
123 #define CLOCK_399_133_66
124 //#define CLOCK_399_100_50
126 //#define PLL_REF_CLK FREQ_32768HZ
127 #define PLL_REF_CLK FREQ_26MHZ
128 //#define PLL_REF_CLK FREQ_32000HZ
130 #define PLL_REF_CLK CYGHWR_HAL_ARM_SOC_PLL_REF_CLOCK
131 #if (CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK == 399)
132 #if (CYGHWR_HAL_ARM_SOC_SYSTEM_CLOCK == 133)
133 #define CLOCK_399_133_66
134 #elif (CYGHWR_HAL_ARM_SOC_SYSTEM_CLOCK == 100)
135 #define CLOCK_399_100_50
137 #error Invalid SYSTEM clock (CYGHWR_HAL_ARM_SOC_SYSTEM_CLOCK) defined
139 #elif (CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK == 266)
140 #define CLOCK_266_133_66
142 #error Invalid processor clock (CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK) defined
147 #define CRM_PLL_PCTL_PARAM(pd, fd, fi, fn) (((pd-1)<<26) + ((fd-1)<<16) + (fi<<10) + (fn<<0))
148 #if (PLL_REF_CLK == FREQ_32768HZ)
149 #define PLL_REF_CLK_32768HZ
150 // SPCTL0 for 240 MHz
151 #define CRM_SPCTL0_VAL CRM_PLL_PCTL_PARAM(2, 124, 7, 19)
152 #define CRM_SPCTL0_VAL_27MHZ CRM_SPCTL0_VAL
153 #define CRM_SPCTL0_VAL2 CRM_PLL_PCTL_PARAM(2, 59, 7, 9)
154 #define CRM_SPCTL0_VAL2_27MHZ CRM_SPCTL0_VAL2
155 #if defined (CLOCK_266_133_66)
156 #define CRM_MPCTL0_VAL CRM_PLL_PCTL_PARAM(2, 400, 7, 371)
157 #define CRM_MPCTL0_VAL_27MHZ CRM_MPCTL0_VAL
158 #define CRM_CSCR_VAL 0x33F00307
159 #define CRM_MPCTL0_VAL2 CRM_PLL_PCTL_PARAM(1, 496, 5, 469)
160 #define CRM_MPCTL0_VAL2_27MHZ CRM_MPCTL0_VAL2
161 #define CRM_CSCR_VAL2 0x33F00107
162 #elif defined (CLOCK_399_133_66)
163 #define CRM_MPCTL0_VAL CRM_PLL_PCTL_PARAM(2, 100, 11, 89)
164 #define CRM_MPCTL0_VAL_27MHZ CRM_MPCTL0_VAL
165 #define CRM_CSCR_VAL 0x33F00507
166 #define CRM_MPCTL0_VAL2 CRM_PLL_PCTL_PARAM(1, 496, 5, 469)
167 #define CRM_MPCTL0_VAL2_27MHZ CRM_MPCTL0_VAL2
168 #define CRM_CSCR_VAL2 0x33F08107
169 #elif defined (CLOCK_399_100_50)
170 #define CRM_MPCTL0_VAL CRM_PLL_PCTL_PARAM(2, 100, 11, 89)
171 #define CRM_MPCTL0_VAL_27MHZ CRM_MPCTL0_VAL
172 #define CRM_CSCR_VAL 0x33F00307
173 #define CRM_MPCTL0_VAL2 CRM_PLL_PCTL_PARAM(1, 100, 11, 94)
174 #define CRM_MPCTL0_VAL2_27MHZ CRM_MPCTL0_VAL2
175 #define CRM_CSCR_VAL2 0x33F00307
177 #error This clock is not supported !!!!
178 #endif // CLOCK_266_133_66
180 // SPCTL0 for 240 MHz
181 #define CRM_SPCTL0_VAL CRM_PLL_PCTL_PARAM(2, 13, 9, 3)
182 #define CRM_SPCTL0_VAL_27MHZ CRM_PLL_PCTL_PARAM(2, 9, 8, 8)
183 #define CRM_SPCTL0_VAL2 CRM_SPCTL0_VAL
184 #define CRM_SPCTL0_VAL2_27MHZ CRM_SPCTL0_VAL_27MHZ
186 #if defined (CLOCK_266_133_66)
187 #define CRM_MPCTL0_VAL CRM_PLL_PCTL_PARAM(2, 26, 10, 6)
188 #define CRM_MPCTL0_VAL_27MHZ CRM_PLL_PCTL_PARAM(2, 15, 9, 13) // 266.4MHz
189 #define CRM_CSCR_VAL 0x33F30307
190 #define CRM_MPCTL0_VAL2 CRM_PLL_PCTL_PARAM(1, 52, 7, 35)
191 #define CRM_MPCTL0_VAL2_27MHZ CRM_PLL_PCTL_PARAM(1, 5, 7, 2) // 399.6MHz
192 #define CRM_CSCR_VAL2 0x33F30107
193 #elif defined (CLOCK_399_133_66)
194 #define CRM_MPCTL0_VAL CRM_PLL_PCTL_PARAM(1, 52, 7, 35)
195 #define CRM_MPCTL0_VAL_27MHZ CRM_PLL_PCTL_PARAM(1, 5, 7, 2) // 399.6MHz
196 #define CRM_CSCR_VAL 0x33F30507
197 #define CRM_MPCTL0_VAL2 CRM_MPCTL0_VAL
198 #define CRM_MPCTL0_VAL2_27MHZ CRM_MPCTL0_VAL_27MHZ
199 #define CRM_CSCR_VAL2 0x33F38107
200 #elif defined (CLOCK_399_100_50)
201 #define CRM_MPCTL0_VAL CRM_PLL_PCTL_PARAM(1, 52, 7, 35)
202 #define CRM_MPCTL0_VAL_27MHZ CRM_PLL_PCTL_PARAM(1, 5, 7, 2) // 399.6MHz
203 #define CRM_CSCR_VAL 0x33F30307
204 #define CRM_MPCTL0_VAL2 CRM_PLL_PCTL_PARAM(1, 52, 11, 28)
205 #define CRM_MPCTL0_VAL2_27MHZ CRM_MPCTL0_VAL_27MHZ
206 #define CRM_CSCR_VAL2 0x33F30307
208 #error This clock is not supported !!!!
209 #endif // CLOCK_266_133_66
211 #endif // PLL_REF_CLK == FREQ_26MHZ
214 #define SOC_SYSCTRL_BASE 0x10027800
215 #define SOC_SYSCTRL_CID (SOC_SYSCTRL_BASE + 0x00)
216 #define SOC_SYSCTRL_FMCR (SOC_SYSCTRL_BASE + 0x14)
217 #define FMCR_FMS (1 << 5)
218 #define FMCR_NF_16BIT (1 << 4)
219 #define FMCR_SLCDC_SEL (1 << 2)
220 #define FMCR_SDCS1_SEL (1 << 1)
221 #define FMCR_SDCS0_SEL (1 << 0)
222 #define SOC_SYSCTRL_GPCR (SOC_SYSCTRL_BASE + 0x18)
223 #define SOC_SYSCTRL_WBCR (SOC_SYSCTRL_BASE + 0x1C)
224 #define SOC_SYSCTRL_DSCR1 (SOC_SYSCTRL_BASE + 0x20)
225 #define SOC_SYSCTRL_DSCR2 (SOC_SYSCTRL_BASE + 0x24)
226 #define SOC_SYSCTRL_DSCR3 (SOC_SYSCTRL_BASE + 0x28)
227 #define SOC_SYSCTRL_DSCR4 (SOC_SYSCTRL_BASE + 0x2C)
228 #define SOC_SYSCTRL_DSCR5 (SOC_SYSCTRL_BASE + 0x30)
229 #define SOC_SYSCTRL_DSCR6 (SOC_SYSCTRL_BASE + 0x34)
230 #define SOC_SYSCTRL_DSCR7 (SOC_SYSCTRL_BASE + 0x38)
231 #define SOC_SYSCTRL_DSCR8 (SOC_SYSCTRL_BASE + 0x3C)
232 #define SOC_SYSCTRL_DSCR9 (SOC_SYSCTRL_BASE + 0x40)
233 #define SOC_SYSCTRL_DSCR10 (SOC_SYSCTRL_BASE + 0x44)
234 #define SOC_SYSCTRL_DSCR11 (SOC_SYSCTRL_BASE + 0x48)
235 #define SOC_SYSCTRL_DSCR12 (SOC_SYSCTRL_BASE + 0x4C)
236 #define SOC_SYSCTRL_DSCR13 (SOC_SYSCTRL_BASE + 0x50)
237 #define SOC_SYSCTRL_PSCR (SOC_SYSCTRL_BASE + 0x54)
238 #define SOC_SYSCTRL_PCSR (SOC_SYSCTRL_BASE + 0x58)
239 #define SOC_SYSCTRL_PMCR (SOC_SYSCTRL_BASE + 0x60)
240 #define SOC_SYSCTRL_DCVR0 (SOC_SYSCTRL_BASE + 0x64)
241 #define SOC_SYSCTRL_DCVR1 (SOC_SYSCTRL_BASE + 0x68)
242 #define SOC_SYSCTRL_DCVR2 (SOC_SYSCTRL_BASE + 0x6C)
243 #define SOC_SYSCTRL_DCVR3 (SOC_SYSCTRL_BASE + 0x70)
245 // Interrupt Controller Register Definitions.
246 #define SOC_AITC_BASE 0x10040000
247 #define SOC_AITC_INTCNTL (SOC_AITC_BASE + 0x00)
248 #define SOC_AITC_NIMASK (SOC_AITC_BASE + 0x04)
249 #define SOC_AITC_INTENNUM (SOC_AITC_BASE + 0x08)
250 #define SOC_AITC_INTDISNUM (SOC_AITC_BASE + 0x0C)
251 #define SOC_AITC_INTENABLEH (SOC_AITC_BASE + 0x10)
252 #define SOC_AITC_INTENABLEL (SOC_AITC_BASE + 0x14)
253 #define SOC_AITC_INTTYPEH (SOC_AITC_BASE + 0x18)
254 #define SOC_AITC_INTTYPEL (SOC_AITC_BASE + 0x1C)
255 #define SOC_AITC_NIPRIORITY7 (SOC_AITC_BASE + 0x20)
256 #define SOC_AITC_NIPRIORITY6 (SOC_AITC_BASE + 0x24)
257 #define SOC_AITC_NIPRIORITY5 (SOC_AITC_BASE + 0x28)
258 #define SOC_AITC_NIPRIORITY4 (SOC_AITC_BASE + 0x2C)
259 #define SOC_AITC_NIPRIORITY3 (SOC_AITC_BASE + 0x30)
260 #define SOC_AITC_NIPRIORITY2 (SOC_AITC_BASE + 0x34)
261 #define SOC_AITC_NIPRIORITY1 (SOC_AITC_BASE + 0x38)
262 #define SOC_AITC_NIPRIORITY0 (SOC_AITC_BASE + 0x3C)
264 #define UART_WIDTH_32
266 // UART Base Addresses
267 #define SOC_UART1_BASE 0x1000A000
268 #define SOC_UART2_BASE 0x1000B000
269 #define SOC_UART3_BASE 0x1000C000
270 #define SOC_UART4_BASE 0x1000D000
271 #define SOC_UART5_BASE 0x1001B000
272 #define SOC_UART6_BASE 0x1001C000
274 #define SOC_MAX_BASE 0x1003F000
275 // Slave port base offset
276 #define MAX_SLAVE_PORT0_OFFSET 0x0
277 #define MAX_SLAVE_PORT1_OFFSET 0x100
278 #define MAX_SLAVE_PORT2_OFFSET 0x200
279 // Register offset for slave port
280 #define MAX_SLAVE_MPR_OFFSET 0x0 /* Master Priority register */
281 #define MAX_SLAVE_AMPR_OFFSET 0x4 /* Alternate Master Priority register */
282 #define MAX_SLAVE_SGPCR_OFFSET 0x10 /* Slave General Purpose Control register */
283 #define MAX_SLAVE_ASGPCR_OFFSET 0x14 /* Alternate Slave General Purpose control register */
284 // Master port base offset
285 #define MAX_MASTER_PORT0_OFFSET 0x800
286 #define MAX_MASTER_PORT1_OFFSET 0x900
287 #define MAX_MASTER_PORT2_OFFSET 0xA00
288 #define MAX_MASTER_PORT3_OFFSET 0xB00
289 #define MAX_MASTER_PORT4_OFFSET 0xC00
290 #define MAX_MASTER_PORT5_OFFSET 0xD00
291 // Register offset for master port
292 #define MAX_MASTER_MGPCR_OFFSET 0x0 /* Master General Purpose Control Register */
294 * MX27 GPIO Register Definitions
296 #define SOC_GPIOA_BASE 0x10015000
297 #define SOC_GPIOB_BASE 0x10015100
298 #define SOC_GPIOC_BASE 0x10015200
299 #define SOC_GPIOD_BASE 0x10015300
300 #define SOC_GPIOE_BASE 0x10015400
301 #define SOC_GPIOF_BASE 0x10015500
302 #define SOC_GPIO_PMASK 0x10015600
303 #define GPIO_DDIR 0x0 /* Data direction reg */
304 #define GPIO_OCR1 0x4 /* Output config reg 1 */
305 #define GPIO_OCR2 0x8 /* Output config reg 2 */
306 #define GPIO_ICONFA1 0xC /* Input config reg A1 */
307 #define GPIO_ICONFA2 0x10 /* Input config reg A2 */
308 #define GPIO_ICONFB1 0x14 /* Input config reg B1 */
309 #define GPIO_ICONFB2 0x18 /* Input config reg B2 */
310 #define GPIO_DR 0x1C /* Data reg */
311 #define GPIO_GIUS 0x20 /* GPIO in use reg */
312 #define GPIO_SSR 0x24 /* Sample status reg */
313 #define GPIO_ICR1 0x28 /* Int config reg 1 */
314 #define GPIO_ICR2 0x2C /* Int config reg 2 */
315 #define GPIO_IMR 0x30 /* Int mask reg */
316 #define GPIO_ISR 0x34 /* Int status reg */
317 #define GPIO_GPR 0x38 /* Gen purpose reg */
318 #define GPIO_SWR 0x3C /* Software reset reg */
319 #define GPIO_PUEN 0x40 /* Pull-up enable reg */
321 #define GPIO_OCR_A 0 /* External input a_IN */
322 #define GPIO_OCR_B 1 /* External input b_IN */
323 #define GPIO_OCR_C 2 /* External input c_IN */
324 #define GPIO_OCR_DR 3 /* Data register */
325 #define GPIO_ICONF_In 0 /* GPIO-in */
326 #define GPIO_ICONF_Isr 1 /* Interrupt status register */
327 #define GPIO_ICONF_0 2 /* 0 */
328 #define GPIO_ICONF_1 3 /* 1 */
329 #define GPIO_ICR_PosEdge 0 /* Positive edge */
330 #define GPIO_ICR_NegEdge 1 /* Negative edge */
331 #define GPIO_ICR_PosLvl 2 /* Positive level */
332 #define GPIO_ICR_NegLvl 3 /* Negative level */
333 #define GPIO_SWR_SWR 1 /* Software reset */
338 #define HAL_DELAY_TIMER SOC_GPT2_BASE // use timer2 for hal_delay_us()
340 #define SOC_GPT1_BASE 0x10003000
341 #define SOC_GPT2_BASE 0x10004000
342 #define SOC_GPT3_BASE 0x10005000
343 #define SOC_GPT4_BASE 0x10019000
344 #define SOC_GPT5_BASE 0x1001A000
345 #define SOC_GPT6_BASE 0x1001F000
346 #define GPT_TCTL_OFFSET 0x0
347 #define GPT_TPRER_OFFSET 0x4
348 #define GPT_TCMP_OFFSET 0x8
349 #define GPT_TCR_OFFSET 0xC
350 #define GPT_TCN_OFFSET 0x10
351 #define GPT_TSTAT_OFFSET 0x14
352 #define MX_STARTUP_DELAY (1000000 / 10) // 0.1s delay to get around the ethernet reset failure problem
354 #define TIMER_PRESCALER 3
355 #define SOC_SI_ID_REG 0x10027800
356 #define SOC_SILICONID_Rev1_0 0x0
357 #define SOC_SILICONID_Rev2_0 0x1
358 #define SOC_SILICONID_Rev2_1 0x2
359 #define CHIP_REV_1_x 1
360 #define CHIP_REV_2_x 2
361 #define CHIP_REV_3_0 3
362 #define CHIP_REV_3_1 4
363 #define CHIP_REV_unknown 0x100
365 #define SOC_WDOG_BASE 0x10002000
366 #define WDOG_BASE_ADDR SOC_WDOG_BASE
368 #define NFC_BASE 0xD8000000
369 #define SOC_ESDCTL_BASE 0xD8001000
370 #define SOC_EIM_BASE 0xD8002000
371 #define SOC_M3IF_BASE 0xD8003000
372 #define SOC_PCMCIA_BASE 0xD8004000
374 #define SOC_CS0_CTL_BASE SOC_EIM_BASE
375 #define SOC_CS1_CTL_BASE (SOC_EIM_BASE + 0x10)
376 #define SOC_CS2_CTL_BASE (SOC_EIM_BASE + 0x20)
377 #define SOC_CS3_CTL_BASE (SOC_EIM_BASE + 0x30)
378 #define SOC_CS4_CTL_BASE (SOC_EIM_BASE + 0x40)
379 #define SOC_CS5_CTL_BASE (SOC_EIM_BASE + 0x50)
382 #define CSCRU_OFFSET 0x00
383 #define CSCRL_OFFSET 0x04
384 #define CSCRA_OFFSET 0x08
385 #define CSWCR_OFFSET 0x60
388 #define SOC_CSD0_BASE 0xA0000000
389 #define SOC_CSD1_BASE 0xB0000000
390 #define SOC_CS0_BASE 0xC0000000
391 #define CS0_BASE_ADDR SOC_CS0_BASE
392 #define SOC_CS1_BASE 0xC8000000
393 #define SOC_CS2_BASE 0xD0000000
394 #define SOC_CS3_BASE 0xD2000000
395 #define SOC_CS4_BASE 0xD4000000
396 #define SOC_CS5_BASE 0xD6000000
397 #define NAND_REG_BASE (NFC_BASE + 0xE00)
399 #define SOC_IIM_BASE 0x10028000
400 #define SOC_FEC_MAC_BASE 0x10028C04
401 #define SOC_FEC_MAC_BASE2 0x10028814
402 #define SOC_FEC_BASE 0x1002B000
403 #define IIM_BASE_ADDR SOC_IIM_BASE
405 #define CHIP_REV_1_0 0x0 /* PASS 1.0 */
406 #define CHIP_REV_2_0 0x1 /* PASS 2.0 */
408 #define IIM_STAT_OFF 0x00
409 #define IIM_STAT_BUSY (1 << 7)
410 #define IIM_STAT_PRGD (1 << 1)
411 #define IIM_STAT_SNSD (1 << 0)
412 #define IIM_STATM_OFF 0x04
413 #define IIM_ERR_OFF 0x08
414 #define IIM_ERR_PRGE (1 << 7)
415 #define IIM_ERR_WPE (1 << 6)
416 #define IIM_ERR_OPE (1 << 5)
417 #define IIM_ERR_RPE (1 << 4)
418 #define IIM_ERR_WLRE (1 << 3)
419 #define IIM_ERR_SNSE (1 << 2)
420 #define IIM_ERR_PARITYE (1 << 1)
421 #define IIM_EMASK_OFF 0x0C
422 #define IIM_FCTL_OFF 0x10
423 #define IIM_UA_OFF 0x14
424 #define IIM_LA_OFF 0x18
425 #define IIM_SDAT_OFF 0x1C
426 #define IIM_PREV_OFF 0x20
427 #define IIM_SREV_OFF 0x24
428 #define IIM_PREG_P_OFF 0x28
429 #define IIM_SCS0_OFF 0x2C
430 #define IIM_SCS1_P_OFF 0x30
431 #define IIM_SCS2_OFF 0x34
432 #define IIM_SCS3_P_OFF 0x38
434 #define ESDCTL_ESDCTL0 0x00
435 #define ESDCTL_ESDCFG0 0x04
436 #define ESDCTL_ESDCTL1 0x08
437 #define ESDCTL_ESDCFG1 0x0C
438 #define ESDCTL_ESDMISC 0x10
440 #define NFC_BUFSIZE_REG_OFF (0 + 0x00)
441 #define RAM_BUFFER_ADDRESS_REG_OFF (0 + 0x04)
442 #define NAND_FLASH_ADD_REG_OFF (0 + 0x06)
443 #define NAND_FLASH_CMD_REG_OFF (0 + 0x08)
444 #define NFC_CONFIGURATION_REG_OFF (0 + 0x0A)
445 #define ECC_STATUS_RESULT_REG_OFF (0 + 0x0C)
446 #define ECC_RSLT_MAIN_AREA_REG_OFF (0 + 0x0E)
447 #define ECC_RSLT_SPARE_AREA_REG_OFF (0 + 0x10)
448 #define NF_WR_PROT_REG_OFF (0 + 0x12)
449 #define UNLOCK_START_BLK_ADD_REG_OFF (0 + 0x14)
450 #define UNLOCK_END_BLK_ADD_REG_OFF (0 + 0x16)
451 #define NAND_FLASH_WR_PR_ST_REG_OFF (0 + 0x18)
452 #define NAND_FLASH_CONFIG1_REG_OFF (0 + 0x1A)
453 #define NAND_FLASH_CONFIG2_REG_OFF (0 + 0x1C)
454 #define RAM_BUFFER_ADDRESS_RBA_3 0x3
455 #define NFC_BUFSIZE_1KB 0x0
456 #define NFC_BUFSIZE_2KB 0x1
457 #define NFC_CONFIGURATION_UNLOCKED 0x2
458 #define ECC_STATUS_RESULT_NO_ERR 0x0
459 #define ECC_STATUS_RESULT_1BIT_ERR 0x1
460 #define ECC_STATUS_RESULT_2BIT_ERR 0x2
461 #define NF_WR_PROT_UNLOCK 0x4
462 #define NAND_FLASH_CONFIG1_FORCE_CE (1 << 7)
463 #define NAND_FLASH_CONFIG1_RST (1 << 6)
464 #define NAND_FLASH_CONFIG1_BIG (1 << 5)
465 #define NAND_FLASH_CONFIG1_INT_MSK (1 << 4)
466 #define NAND_FLASH_CONFIG1_ECC_EN (1 << 3)
467 #define NAND_FLASH_CONFIG1_SP_EN (1 << 2)
468 #define NAND_FLASH_CONFIG2_INT_DONE (1 << 15)
469 #define NAND_FLASH_CONFIG2_FDO_PAGE (0 << 3)
470 #define NAND_FLASH_CONFIG2_FDO_ID (2 << 3)
471 #define NAND_FLASH_CONFIG2_FDO_STATUS (4 << 3)
472 #define NAND_FLASH_CONFIG2_FDI_EN (1 << 2)
473 #define NAND_FLASH_CONFIG2_FADD_EN (1 << 1)
474 #define NAND_FLASH_CONFIG2_FCMD_EN (1 << 0)
475 #define FDO_PAGE_SPARE_VAL 0x8
477 #define MXC_NAND_BASE_DUMMY 0xE0000000
478 #define NOR_FLASH_BOOT 0
479 #define NAND_FLASH_BOOT 0x10
480 #define SDRAM_NON_FLASH_BOOT 0x20
481 #define MXCBOOT_FLAG_REG SOC_AITC_NIPRIORITY7
483 #define MXCFIS_NOTHING 0x00000000
484 #define MXCFIS_NAND 0x10000000
485 #define MXCFIS_NOR 0x20000000
486 #define MXCFIS_FLAG_REG SOC_AITC_NIPRIORITY6
487 #ifndef MXCFLASH_SELECT_NAND
488 #define IS_BOOTING_FROM_NAND() 0
490 #define IS_BOOTING_FROM_NAND() (readl(MXCBOOT_FLAG_REG) == NAND_FLASH_BOOT)
492 #ifndef MXCFLASH_SELECT_NOR
493 #define IS_BOOTING_FROM_NOR() 0
495 #define IS_BOOTING_FROM_NOR() (readl(MXCBOOT_FLAG_REG) == NOR_FLASH_BOOT)
497 #ifndef IS_BOOTING_FROM_SDRAM
498 #define IS_BOOTING_FROM_SDRAM() (readl(MXCBOOT_FLAG_REG) == SDRAM_NON_FLASH_BOOT)
501 #ifndef MXCFLASH_SELECT_NAND
502 #define IS_FIS_FROM_NAND() 0
504 #ifndef MXCFLASH_SELECT_NOR
505 #define IS_FIS_FROM_NAND() 1
507 #define IS_FIS_FROM_NAND() (readl(MXCFIS_FLAG_REG) == MXCFIS_NAND)
511 #ifndef MXCFLASH_SELECT_NOR
512 #define IS_FIS_FROM_NOR() 0
514 #define IS_FIS_FROM_NOR() (!IS_FIS_FROM_NAND())
517 #define MXC_ASSERT_NOR_BOOT() writel(MXCFIS_NOR, MXCFIS_FLAG_REG)
518 #define MXC_ASSERT_NAND_BOOT() writel(MXCFIS_NAND, MXCFIS_FLAG_REG)
520 #define SERIAL_DOWNLOAD_MAGIC 0x000000AA
521 #define SERIAL_DOWNLOAD_MAGIC_REG SOC_AITC_NIPRIORITY3
522 #define SERIAL_DOWNLOAD_SRC_REG SOC_AITC_NIPRIORITY2
523 #define SERIAL_DOWNLOAD_TGT_REG SOC_AITC_NIPRIORITY1
524 #define SERIAL_DOWNLOAD_SZ_REG SOC_AITC_NIPRIORITY0
526 #if !defined(__ASSEMBLER__)
527 void cyg_hal_plf_serial_init(void);
528 void cyg_hal_plf_serial_stop(void);
529 void hal_delay_us(unsigned int usecs);
530 #define HAL_DELAY_US(n) hal_delay_us(n)
533 MCU_PLL = SOC_CRM_MPCTL0,
534 SER_PLL = SOC_CRM_SPCTL0,
554 SPI1_CLK = CSPI1_BASE_ADDR,
555 SPI2_CLK = CSPI2_BASE_ADDR,
558 unsigned int pll_clock(enum plls pll);
560 unsigned int get_main_clock(enum main_clocks clk);
562 unsigned int get_peri_clock(enum peri_clocks clk);
563 #define GPIO_PORT_NUM 6
564 #define GPIO_NUM_PIN 32
565 #define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM)
567 #define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * GPIO_NUM_PIN) + ((pin >> MUX_IO_I) & ((1 << (MUX_IO_P - MUX_IO_I)) -1)))
568 #define IOMUX_TO_IRQ(pin) (MXC_GPIO_BASE + IOMUX_TO_GPIO(pin))
569 #define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN)
570 #define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN)
583 int gpio_request_mux(iomux_pin_name_t pin, gpio_mux_mode_t mode);
584 void clock_spi_enable(unsigned int spi_clk);
591 typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int);
593 #endif //#if !defined(__ASSEMBLER__)
595 #define HAL_MMU_OFF() \
599 "mrc p15, 0, r15, c7, c14, 3;" /*test clean and inval*/ \
602 "mcr p15,0,r0,c7,c10,4;" /* Data Write Barrier */ \
603 "mcr p15,0,r0,c7,c5,0;" /* invalidate I cache */ \
604 "mrc p15,0,r0,c1,c0,0;" /* read c1 */ \
605 "bic r0,r0,#0x7;" /* disable DCache and MMU */ \
606 "bic r0,r0,#0x1000;" /* disable ICache */ \
607 "mcr p15,0,r0,c1,c0,0;" /* */ \
608 "nop;" /* flush i+d-TLBs */ \
609 "nop;" /* flush i+d-TLBs */ \
610 "nop;" /* flush i+d-TLBs */ \
613 : "r0","memory" /* clobber list */); \
616 #endif /* __HAL_SOC_H__ */
projects / karo-tx-redboot.git / blob