1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 //=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 // You should have received a copy of the GNU General Public License along
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
31 // with other works to produce a work based on this file, this file does not
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33 // License. However the source code for this file must still be made available
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40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //===========================================================================
45 #include <pkgconf/system.h> // System-wide configuration info
46 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
47 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
48 #include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
49 #include <cyg/hal/hal_mmu.h> // MMU definitions
50 #include CYGBLD_HAL_PLF_DEFS_H // Platform specific hardware definitions
52 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
53 #define PLATFORM_SETUP1 _platform_setup1
54 #define CYGHWR_HAL_ARM_HAS_MMU
56 #ifdef CYG_HAL_STARTUP_ROMRAM
57 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
60 //#define NFC_2K_BI_SWAP
61 #define SDRAM_FULL_PAGE_BIT 0x100
62 #define SDRAM_FULL_PAGE_MODE 0x37
63 #define SDRAM_BURST_MODE 0x33
65 #define CYGHWR_HAL_ROM_VADDR 0x0
68 #define UNALIGNED_ACCESS_ENABLE
69 #define SET_T_BIT_DISABLE
70 #define BRANCH_PREDICTION_ENABLE
74 #define TX37_NAND_PAGE_SIZE 2048
75 #define TX37_NAND_BLKS_PER_PAGE 64
77 #ifndef CYGOPT_HAL_ARM_TX37_DEBUG
84 #define CYGHWR_LED_MACRO LED_BLINK #\x
100 // switch user LED (GPIO2_19) on STK5
101 ldr r10, GPIO2_BASE_ADDR_W
104 movne r9, #(1 << 19) // LED ON
105 moveq r9, #0 // LED OFF
106 str r9, [r10, #0x00] @ GPIO_DR
125 // initialize GPIO2[19] for LED on STK5
126 ldr r10, IOMUXC_BASE_ADDR_W
127 @ AUD5_RXC = ALT4 (GPIO2[19])
129 str r9, [r10, #0x120]
130 ldr r10, GPIO2_BASE_ADDR_W
133 str r9, [r10, #0x00] @ GPIO_DR
136 str r9, [r10, #0x04] @ GPIO_GDIR
139 //#define ENABLE_IMPRECISE_ABORT
142 #define PLATFORM_PREAMBLE flash_header
144 //flash header & DCD @ 0x400
148 app_code_jump_v: .long reset_vector
149 app_code_barker: .long 0xB1
150 app_code_csf: .long 0
151 dcd_ptr_ptr: .long dcd_ptr
152 super_root_key: .long 0
153 dcd_ptr: .long dcd_data
154 app_dest_ptr: .long CYGMEM_REGION_rom - REDBOOT_OFFSET
156 dcd_data: .long 0xB17219E9
157 dcd_len: .long (49 * 12)
161 // KEY_ROW0 -> EMI_DRAM_D[16]
166 // KEY_ROW1 -> EMI_DRAM_D[17]
171 // KEY_ROW2 -> EMI_DRAM_D[18]
176 // KEY_ROW3 -> EMI_DRAM_D[19]
181 // KEY_ROW4 -> EMI_DRAM_D[20]
186 // KEY_ROW5 -> EMI_DRAM_D[21]
191 // KEY_ROW6 -> EMI_DRAM_D[22]
196 // KEY_ROW7 -> EMI_DRAM_D[23]
202 // IETM_D0 -> EMI_DRAM_D[24]
208 // IETM_D1 -> EMI_DRAM_D[25]
214 // IETM_D2 -> EMI_DRAM_D[26]
220 // IETM_D3 -> EMI_DRAM_D[27]
226 // IETM_D4 -> EMI_DRAM_D[28]
232 // IETM_D5 -> EMI_DRAM_D[29]
238 // IETM_D6 -> EMI_DRAM_D[30]
244 // IETM_D7 -> EMI_DRAM_D[31]
250 // EIM_EB0 -> DRAM_DQM[2]
256 // EIM_EB1 -> DRAM_DQM[3]
262 // EIM_ECB -> DRAM_SDQS[2]
268 // SW_PAD_CTL_PAD_EIM_ECB -> DDR input type / Pull/Keeper Enabled / Pull / 100KOhm Pull Down / High Drive Strength
274 // EIM_LBA -> DRAM_SDQS[3]
280 // SW_PAD_CTL_PAD_EIM_LBA -> DDR input type / Pull/Keeper Enabled / Pull / 100KOhm Pull Down / High Drive Strength
286 // SW_PAD_CTL_GRP_S7 -> Medium Drive Strength
292 // SW_PAD_CTL_GRP_S8 -> Medium Drive Strength
298 // SW_PAD_CTL_GRP_S9 -> Medium Drive Strength
304 // SW_PAD_CTL_GRP_S10 -> Medium Drive Strength
310 // SW_PAD_CTL_PAD_DRAM_DQM0 -> Medium Drive Strength
316 // SW_PAD_CTL_PAD_DRAM_DQM1 -> Medium Drive Strength
322 // DRAM_SDQS0 -> Medium Drive Strength
328 // DRAM_SDQS1 -> Medium Drive Strength
334 // SW_PAD_CTL_GRP_S3 -> Medium Drive Strength
340 // SW_PAD_CTL_GRP_S4 -> Medium Drive Strength
346 // SW_PAD_CTL_GRP_S5 -> Medium Drive Strength
352 // SW_PAD_CTL_GRP_S6 -> Medium Drive Strength
358 // DRAM_SDCLK -> Medium Drive Strength
364 // SW_PAD_CTL_PAD_DRAM_RAS -> Medium Drive Strength
370 // SW_PAD_CTL_PAD_DRAM_CAS -> Medium Drive Strength
376 // SW_PAD_CTL_PAD_DRAM_SDWE -> Medium Drive Strength
382 // SW_PAD_CTL_PAD_DRAM_SDCKE0 -> Medium Drive Strength
388 // SW_PAD_CTL_PAD_DRAM_SDCKE1 -> Medium Drive Strength
399 // Precharge command 2
404 // refresh commands 3
414 // LMR with CAS=3 BL=3 5
420 // 13row 9 col 32 bit sref=4 micro model 6
426 // timing parameter 7
432 // mddr enable RLAT=2 8
444 image_len: .long REDBOOT_IMAGE_SIZE
448 // This macro represents the initial startup code for the platform
449 .macro _platform_setup1
450 KARO_TX37_SETUP_START:
453 * - invalidate I/D cache/TLB and drain write buffer;
454 * - invalidate L2 cache
456 * - branch predictions
458 // mrc p15, 0, r0, c1, c1, 0 // Read Secure Configuration Register data. Why doesn't work???
459 // mcr p15, 0, <Rd>, c1, c1, 0 ; Write Secure Configuration Register data
460 #ifdef ENABLE_IMPRECISE_ABORT
461 mrs r1, spsr // save old spsr
462 mrs r0, cpsr // read out the cpsr
463 bic r0, r0, #0x100 // clear the A bit
464 msr spsr, r0 // update spsr
465 add lr, pc, #0x8 // update lr
466 movs pc, lr // update cpsr
471 msr spsr, r1 // restore old spsr
474 mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
475 mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
476 mcr 15, 0, r0, c7, c10, 4 /* Data write barrier */
478 /* Also setup the Peripheral Port Remap register inside the core */
479 ldr r0, ARM_PPMRR /* start from AIPS 2GB region */
480 mcr p15, 0, r0, c15, c2, 4
482 cmp pc, #SDRAM_BASE_ADDR
484 cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
487 /*** L2 Cache setup/invalidation/disable ***/
488 /* Disable L2 cache first */
489 mov r0, #L2CC_BASE_ADDR
491 str r2, [r0, #L2_CACHE_CTL_REG]
493 * Configure L2 Cache:
494 * - 128k size(16k way)
495 * - 8-way associativity
496 * - 0 ws TAG/VALID/DIRTY
500 add r2, r2, #0x00F00000
501 ldr r1, [r0, #L2_CACHE_AUX_CTL_REG]
503 ldr r2, L2CACHE_PARAM
505 str r1, [r0, #L2_CACHE_AUX_CTL_REG]
509 str r1, [r0, #L2_CACHE_INV_WAY_REG]
511 /* Poll Invalidate By Way register */
512 ldr r2, [r0, #L2_CACHE_INV_WAY_REG]
515 /*** End of L2 operations ***/
520 * End of ARM1136 init
541 /* If SDRAM has been setup, bypass clock/WEIM setup */
542 cmp pc, #SDRAM_BASE_ADDR
543 blo external_boot_cont
544 cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
545 blo internal_boot_cont
555 HWInitialise_skip_SDRAM_setup:
557 add r2, r0, #0x1000 // 4K window
559 blo Normal_Boot_Continue
561 bhs Normal_Boot_Continue
564 /* Copy image from flash to SDRAM first */
565 ldr r1, MXC_REDBOOT_RAM_START
574 and r0, pc, r1 /* offset of pc */
575 ldr r1, MXC_REDBOOT_RAM_START
582 // Check if x16/2kb page
583 // ldr r7, CCM_BASE_ADDR_W
584 // ldr r7, [r7, #0xC]
585 // ands r7, r7, #(1 << 30)
586 ldr r0, NFC_BASE_W //r0: nfc base. Reloaded after each page copying
587 mov r1, #TX37_NAND_PAGE_SIZE //r1: starting flash addr to be copied. Updated constantly
588 // ???? should be dynamic based on the page size kevin todo
589 add r2, r0, #TX37_NAND_PAGE_SIZE //r2: end of 3rd RAM buf. Doesn't change ?? dynamic
591 ldr r11, NFC_IP_BASE_W //r11: NFC IP register base. Doesn't change
592 add r12, r0, #0x1E00 //r12: NFC AXI register base. Doesn't change
593 ldr r14, MXC_REDBOOT_RAM_START
594 add r13, r14, #REDBOOT_IMAGE_SIZE //r13: end of SDRAM address for copying. Doesn't change
595 add r14, r14, r1 //r14: starting SDRAM address for copying. Updated constantly
597 //unlock internal buffer
599 add r3, r3, #0x00FF0000
604 mov r3, #0x20000 // BLS = 2 -> Buffer Lock Set = unlocked
605 add r3, r3, #0x4 // WPC = 4 -> write protection command = unlock blocks
606 str r3, [r11, #0x0] // kevin - revist for multiple CS ??
613 mov r3, #NAND_LAUNCH_FCMD
617 // start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, nflash_dev_info->base_mask);
620 do_addr_input //1st addr cycle
623 do_addr_input //2nd addr cycle
628 do_addr_input //3rd addr cycle
633 do_addr_input //4th addr cycle
637 mov r3, #NAND_LAUNCH_FCMD
641 // write RBA=0 to NFC_CONFIGURATION1
645 // writel(mode & 0xFF, NAND_LAUNCH_REG)
658 bge NAND_Copy_Main_done
659 add r1, r1, #TX37_NAND_PAGE_SIZE
665 Normal_Boot_Continue:
666 #ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
667 /* Copy image from flash to SDRAM first */
668 ldr r0, SDRAM_ADDR_MASK
670 ldr r1, MXC_REDBOOT_RAM_START
672 beq HWInitialise_skip_SDRAM_copy
674 add r2, r0, #REDBOOT_IMAGE_SIZE
682 #endif /* CYG_HAL_STARTUP_ROMRAM */
684 HWInitialise_skip_SDRAM_copy:
687 * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity
690 // Set up a stack [for calling C code]
691 ldr r1, =__startup_stack
692 ldr r2, =RAM_BANK0_BASE
700 mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
701 orr r1, r1, #7 // enable MMU bit
702 orr r1, r1, #0x800 // enable z bit
706 mcr MMU_CP, 0, r1, MMU_Control, c0
707 mov pc,r2 /* Change address spaces */
710 .endm // _platform_setup1
713 ldr r0, SDRAM_ADDR_MASK
714 ldr r1, MXC_REDBOOT_RAM_START
720 #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
721 #define PLATFORM_SETUP1
725 .endm /* init_spba */
727 /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
730 * Set all MPROTx to be non-bufferable, trusted for R/W,
731 * not forced to user-mode.
733 ldr r0, AIPS1_CTRL_BASE_ADDR_W
734 ldr r1, AIPS1_PARAM_W
737 ldr r0, AIPS2_CTRL_BASE_ADDR_W
740 .endm /* init_aips */
742 /* MAX (Multi-Layer AHB Crossbar Switch) setup */
744 ldr r0, MAX_BASE_ADDR_W
746 /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
748 str r1, [r0, #0x000] /* for S0 */
749 str r1, [r0, #0x100] /* for S1 */
750 str r1, [r0, #0x200] /* for S2 */
751 str r1, [r0, #0x300] /* for S3 */
752 str r1, [r0, #0x400] /* for S4 */
753 /* SGPCR - always park on last master */
755 str r1, [r0, #0x010] /* for S0 */
756 str r1, [r0, #0x110] /* for S1 */
757 str r1, [r0, #0x210] /* for S2 */
758 str r1, [r0, #0x310] /* for S3 */
759 str r1, [r0, #0x410] /* for S4 */
760 /* MGPCR - restore default values */
762 str r1, [r0, #0x800] /* for M0 */
763 str r1, [r0, #0x900] /* for M1 */
764 str r1, [r0, #0xA00] /* for M2 */
765 str r1, [r0, #0xB00] /* for M3 */
766 str r1, [r0, #0xC00] /* for M4 */
767 str r1, [r0, #0xD00] /* for M5 */
777 ===========================
783 * All other clocks can be figured out based on this.
786 * Step 1: Switch to step clock
788 ldr r0, CCM_BASE_ADDR_W
790 str r1, [r0, #CLKCTL_CCSR]
792 /* Step 2: Setup PLL's */
793 /* Set PLL1 to be 532MHz */
794 ldr r0, PLL1_BASE_ADDR_W
797 str r2, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */
799 str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
802 str r1, [r0, #PLL_DP_OP]
804 str r1, [r0, #PLL_DP_MFD]
806 str r1, [r0, #PLL_DP_MFN]
809 str r1, [r0, #PLL_DP_HFS_OP]
811 str r1, [r0, #PLL_DP_HFS_MFD]
813 str r1, [r0, #PLL_DP_HFS_MFN]
815 /* Now restart PLL 1 */
817 str r1, [r0, #PLL_DP_CTL]
819 ldr r1, [r0, #PLL_DP_CTL]
824 * Step 2: Setup PLL2 to 665 MHz.
826 ldr r0, PLL2_BASE_ADDR_W
829 str r2, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */
831 str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
834 str r1, [r0, #PLL_DP_OP]
836 str r1, [r0, #PLL_DP_MFD]
838 str r1, [r0, #PLL_DP_MFN]
841 str r1, [r0, #PLL_DP_HFS_OP]
843 str r1, [r0, #PLL_DP_HFS_MFD]
845 str r1, [r0, #PLL_DP_HFS_MFN]
847 /* Now restart PLL 2 */
849 str r1, [r0, #PLL_DP_CTL]
851 ldr r1, [r0, #PLL_DP_CTL]
856 * Set PLL 3 to 216MHz
858 ldr r0, PLL3_BASE_ADDR_W
861 str r2, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */
863 str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
866 str r1, [r0, #PLL_DP_OP]
868 str r1, [r0, #PLL_DP_MFD]
870 str r1, [r0, #PLL_DP_MFN]
873 str r1, [r0, #PLL_DP_HFS_OP]
875 str r1, [r0, #PLL_DP_HFS_MFD]
877 str r1, [r0, #PLL_DP_HFS_MFN]
879 /* Now restart PLL 3 */
881 str r1, [r0, #PLL_DP_CTL]
883 ldr r1, [r0, #PLL_DP_CTL]
886 /* End of PLL 3 setup */
888 /* Setup the ARM platform clock dividers */
889 ldr r0, PLATFORM_BASE_ADDR_W
890 ldr r1, PLATFORM_CLOCK_DIV_W
894 * Step 3: switching to PLL 1 and restore default register values.
896 ldr r0, CCM_BASE_ADDR_W
898 str r1, [r0, #CLKCTL_CCSR]
901 add r1, r1, #0x00000F0
902 str r1, [r0, #CLKCTL_CCOSR]
903 /* Use 133MHz for DDR clock */
905 str r1, [r0, #CLKCTL_CAMR]
906 /* Use PLL 2 for UART's, get 66.5MHz from it */
907 ldr r1, CCM_CSCMR1_VAL
908 str r1, [r0, #CLKCTL_CSCMR1]
909 ldr r1, CCM_CSCDR1_VAL
910 str r1, [r0, #CLKCTL_CSCDR1]
913 str r1, [r0, #CLKCTL_CBCDR7]
916 .endm /* init_clock */
920 /* Configure M4IF registers, VPU and IPU given higher priority (=0x4)
921 IPU accesses with ID=0x1 given highest priority (=0xA) */
923 ldr r0, M4IF_0x00000a01
924 str r0, [r1, #M4IF_FIDBP]
926 ldr r0, M4IF_0x00000404
927 str r0, [r1, #M4IF_FBPM0]
928 .endm /* init_m4if */
931 ldr r0, ESDCTL_BASE_W
934 str r1, [r0, #ESDCTL_ESDCTL0]
936 @ wait for SDRAM ready
937 ldr r2, [r0, #ESDCTL_ESDMISC]
941 /* Precharge command */
942 ldr r1, SDRAM_CMD_PRECHG
943 str r1, [r0, #ESDCTL_ESDSCR]
945 /* 2 refresh commands */
946 ldr r1, SDRAM_CMD_SLFRFSH
948 str r1, [r0, #ESDCTL_ESDSCR]
951 /* LMR with CAS Latency=3 and BurstLength=3->8words */
952 ldr r1, SDRAM_CMD_MODEREG
953 str r1, [r0, #ESDCTL_ESDSCR]
955 /* 13 ROW, 9 COL, 32Bit, SREF=4 */
956 ldr r1, SDRAM_ESDCTL0_VAL
957 str r1, [r0, #ESDCTL_ESDCTL0]
959 /* Timing parameters */
960 ldr r1, SDRAM_ESDCFG0_VAL
961 str r1, [r0, #ESDCTL_ESDCFG0]
963 /* MDDR enable, RALAT=1 */
964 ldr r1, SDRAM_ESDMISC_VAL
965 str r1, [r0, #ESDCTL_ESDMISC]
969 str r1, [r0, #ESDCTL_ESDSCR]
972 .macro do_wait_op_done
975 ands r3, r3, #NFC_IPC_INT
979 .endm // do_wait_op_done
983 mov r3, #NAND_LAUNCH_FADD
986 .endm // do_addr_input
988 /* To support 133MHz DDR */
990 ldr r0, IOMUXC_BASE_ADDR_W
992 // DDR signal setup for D16-D31 and drive strength
1010 str r8, [r0, #0x4A8]
1011 str r8, [r0, #0x4B0]
1012 str r8, [r0, #0x4B4]
1013 str r8, [r0, #0x4E0]
1014 str r8, [r0, #0x4FC]
1015 str r8, [r0, #0x504]
1016 str r8, [r0, #0x48C]
1017 str r8, [r0, #0x49C]
1025 .endm /* init_iomux */
1027 #define PLATFORM_VECTORS _platform_vectors
1028 .macro _platform_vectors
1032 .globl _KARO_STRUCT_SIZE
1034 .word 0 // reserve space structure length
1036 .globl _KARO_CECFG_START
1039 .word 0 // reserve space for CE configuration
1042 .globl _KARO_CECFG_END
1046 KaRo_MSG: .asciz "KARO TX37 " __DATE__ " " __TIME__ "\n"
1047 ARM_PPMRR: .word 0x80000016
1048 L2CACHE_PARAM: .word 0x0003001B
1049 WDOG1_BASE_W: .word WDOG1_BASE_ADDR
1050 IIM_SREV_REG_VAL: .word IIM_BASE_ADDR + IIM_SREV_OFF
1051 AIPS1_CTRL_BASE_ADDR_W: .word AIPS1_CTRL_BASE_ADDR
1052 AIPS2_CTRL_BASE_ADDR_W: .word AIPS2_CTRL_BASE_ADDR
1053 AIPS1_PARAM_W: .word 0x77777777
1054 MAX_BASE_ADDR_W: .word MAX_BASE_ADDR
1055 MAX_PARAM1: .word 0x00302154
1056 ESDCTL_BASE_W: .word ESDCTL_BASE
1057 M4IF_BASE_W: .word M4IF_BASE
1058 M4IF_0x00000a01: .word 0x00000a01
1059 M4IF_0x00000404: .word 0x00000404
1060 NFC_BASE_W: .word NFC_BASE
1061 NFC_IP_BASE_W: .word NFC_IP_BASE
1062 SDRAM_CMD_PRECHG: .word 0x04008008
1063 SDRAM_CMD_SLFRFSH: .word 0x00008010
1064 SDRAM_CMD_MODEREG: .word 0x00338018
1065 #if SDRAM_SIZE > SZ_64M
1066 SDRAM_ESDCTL0_VAL: .word 0xB2220000
1068 SDRAM_ESDCTL0_VAL: .word 0xB2120000
1070 SDRAM_ESDCFG0_VAL: .word 0x70395729
1071 SDRAM_ESDMISC_VAL: .word 0x000A0084
1072 IOMUXC_BASE_ADDR_W: .word IOMUXC_BASE_ADDR
1073 GPIO2_BASE_ADDR_W: .word GPIO2_BASE_ADDR
1074 MXC_REDBOOT_RAM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - REDBOOT_OFFSET
1075 SDRAM_ADDR_MASK: .word 0xFFFFF000
1076 CONST_0x0FFF: .word 0x0FFF
1077 CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
1078 PLATFORM_BASE_ADDR_W: .word PLATFORM_BASE_ADDR
1079 PLATFORM_CLOCK_DIV_W: .word 0x00077713
1080 CCM_CSCDR1_VAL: .word 0x01450B21
1081 CCM_CSCMR1_VAL: .word 0xA5A6A020
1082 PLL1_BASE_ADDR_W: .word PLL1_BASE_ADDR
1083 PLL2_BASE_ADDR_W: .word PLL2_BASE_ADDR
1084 PLL3_BASE_ADDR_W: .word PLL3_BASE_ADDR
1085 PLL_1_2_VAL: .word 0x1222
1086 PLL_3_VAL: .word 0x222
1088 /*--------------------------------------------------------------------------*/
1089 /* end of hal_platform_setup.h */
1090 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */