1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 //=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
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41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //===========================================================================
45 #include <pkgconf/system.h> // System-wide configuration info
46 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
47 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
48 #include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
49 #include <cyg/hal/hal_mmu.h> // MMU definitions
50 #include <cyg/hal/karo_tx37.h> // Platform specific hardware definitions
52 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
53 #define PLATFORM_SETUP1 _platform_setup1
54 #define CYGHWR_HAL_ARM_HAS_MMU
56 #ifdef CYG_HAL_STARTUP_ROMRAM
57 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
60 //#define NFC_2K_BI_SWAP
61 #define SDRAM_FULL_PAGE_BIT 0x100
62 #define SDRAM_FULL_PAGE_MODE 0x37
63 #define SDRAM_BURST_MODE 0x33
65 #define CYGHWR_HAL_ROM_VADDR 0x0
68 #define UNALIGNED_ACCESS_ENABLE
69 #define SET_T_BIT_DISABLE
70 #define BRANCH_PREDICTION_ENABLE
74 #define TX37_NAND_PAGE_SIZE 2048
75 #define TX37_NAND_BLKS_PER_PAGE 64
88 #define CYGHWR_LED_MACRO LED_BLINK #\x
89 #define LED_ON bl led_on
90 #define LED_OFF bl led_off
106 // switch user LED (PF13) on STK5
107 ldr r10, GPIO2_BASE_ADDR_W
110 movne r9, #(1 << 19) // LED ON
111 moveq r9, #0 // LED OFF
112 str r9, [r10, #0x00] @ GPIO_DR
131 // initialize GPIO2[19] for LED on STK5
132 ldr r10, IOMUXC_BASE_ADDR_W
133 @ AUD5_RXC = ALT4 (GPIO2[19])
135 str r9, [r10, #0x120]
136 ldr r10, GPIO2_BASE_ADDR_W
139 str r9, [r10, #0x00] @ GPIO_DR
142 str r9, [r10, #0x04] @ GPIO_GDIR
145 //#define ENABLE_IMPRECISE_ABORT
148 #define PLATFORM_PREAMBLE flash_header
150 //flash header & DCD @ 0x400
154 app_code_jump_v: .long reset_vector
155 app_code_barker: .long 0xB1
156 app_code_csf: .long 0
157 dcd_ptr_ptr: .long dcd_ptr
158 super_root_key: .long 0
159 dcd_ptr: .long dcd_data
160 app_dest_ptr: .long CYGMEM_REGION_rom - REDBOOT_OFFSET
162 dcd_data: .long 0xB17219E9
163 dcd_len: .long (49 * 12)
167 // KEY_ROW0 -> EMI_DRAM_D[16]
172 // KEY_ROW1 -> EMI_DRAM_D[17]
177 // KEY_ROW2 -> EMI_DRAM_D[18]
182 // KEY_ROW3 -> EMI_DRAM_D[19]
187 // KEY_ROW4 -> EMI_DRAM_D[20]
192 // KEY_ROW5 -> EMI_DRAM_D[21]
197 // KEY_ROW6 -> EMI_DRAM_D[22]
202 // KEY_ROW7 -> EMI_DRAM_D[23]
208 // IETM_D0 -> EMI_DRAM_D[24]
214 // IETM_D1 -> EMI_DRAM_D[25]
220 // IETM_D2 -> EMI_DRAM_D[26]
226 // IETM_D3 -> EMI_DRAM_D[27]
232 // IETM_D4 -> EMI_DRAM_D[28]
238 // IETM_D5 -> EMI_DRAM_D[29]
244 // IETM_D6 -> EMI_DRAM_D[30]
250 // IETM_D7 -> EMI_DRAM_D[31]
256 // EIM_EB0 -> DRAM_DQM[2]
262 // EIM_EB1 -> DRAM_DQM[3]
268 // EIM_ECB -> DRAM_SDQS[2]
274 // SW_PAD_CTL_PAD_EIM_ECB -> DDR input type / Pull/Keeper Enabled / Pull / 100KOhm Pull Down / High Drive Strength
280 // EIM_LBA -> DRAM_SDQS[3]
286 // SW_PAD_CTL_PAD_EIM_LBA -> DDR input type / Pull/Keeper Enabled / Pull / 100KOhm Pull Down / High Drive Strength
292 // SW_PAD_CTL_GRP_S7 -> Medium Drive Strength
298 // SW_PAD_CTL_GRP_S8 -> Medium Drive Strength
304 // SW_PAD_CTL_GRP_S9 -> Medium Drive Strength
310 // SW_PAD_CTL_GRP_S10 -> Medium Drive Strength
316 // SW_PAD_CTL_PAD_DRAM_DQM0 -> Medium Drive Strength
322 // SW_PAD_CTL_PAD_DRAM_DQM1 -> Medium Drive Strength
328 // DRAM_SDQS0 -> Medium Drive Strength
334 // DRAM_SDQS1 -> Medium Drive Strength
340 // SW_PAD_CTL_GRP_S3 -> Medium Drive Strength
346 // SW_PAD_CTL_GRP_S4 -> Medium Drive Strength
352 // SW_PAD_CTL_GRP_S5 -> Medium Drive Strength
358 // SW_PAD_CTL_GRP_S6 -> Medium Drive Strength
364 // DRAM_SDCLK -> Medium Drive Strength
370 // SW_PAD_CTL_PAD_DRAM_RAS -> Medium Drive Strength
376 // SW_PAD_CTL_PAD_DRAM_CAS -> Medium Drive Strength
382 // SW_PAD_CTL_PAD_DRAM_SDWE -> Medium Drive Strength
388 // SW_PAD_CTL_PAD_DRAM_SDCKE0 -> Medium Drive Strength
394 // SW_PAD_CTL_PAD_DRAM_SDCKE1 -> Medium Drive Strength
405 // Precharge command 2
410 // refresh commands 3
420 // LMR with CAS=3 BL=3 5
426 // 13row 9 col 32 bit sref=4 micro model 6
432 // timing parameter 7
438 // mddr enable RLAT=2 8
450 image_len: .long REDBOOT_IMAGE_SIZE
454 // This macro represents the initial startup code for the platform
455 .macro _platform_setup1
456 KARO_TX32_SETUP_START:
459 * - invalidate I/D cache/TLB and drain write buffer;
460 * - invalidate L2 cache
462 * - branch predictions
464 // mrc p15, 0, r0, c1, c1, 0 // Read Secure Configuration Register data. Why doesn't work???
465 // mcr p15, 0, <Rd>, c1, c1, 0 ; Write Secure Configuration Register data
466 #ifdef ENABLE_IMPRECISE_ABORT
467 mrs r1, spsr // save old spsr
468 mrs r0, cpsr // read out the cpsr
469 bic r0, r0, #0x100 // clear the A bit
470 msr spsr, r0 // update spsr
471 add lr, pc, #0x8 // update lr
472 movs pc, lr // update cpsr
477 msr spsr, r1 // restore old spsr
480 mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
481 mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
482 mcr 15, 0, r0, c7, c10, 4 /* Data write barrier */
484 /* Also setup the Peripheral Port Remap register inside the core */
485 ldr r0, ARM_PPMRR /* start from AIPS 2GB region */
486 mcr p15, 0, r0, c15, c2, 4
488 /* Reload data from spare area to 0x400 of main area if booting from NAND */
494 #ifdef BARKER_CODE_SWAP_LOC
495 #if BARKER_CODE_SWAP_LOC != 0x404
496 #error FIXME: the following depends on barker code to be 0x404
498 // Recover the word at 0x404 offset using the one stored in the spare area 0
508 /*** L2 Cache setup/invalidation/disable ***/
509 /* Disable L2 cache first */
510 mov r0, #L2CC_BASE_ADDR
512 str r2, [r0, #L2_CACHE_CTL_REG]
514 * Configure L2 Cache:
515 * - 128k size(16k way)
516 * - 8-way associativity
517 * - 0 ws TAG/VALID/DIRTY
521 add r2, r2, #0x00F00000
522 ldr r1, [r0, #L2_CACHE_AUX_CTL_REG]
524 ldr r2, L2CACHE_PARAM
526 str r1, [r0, #L2_CACHE_AUX_CTL_REG]
530 str r1, [r0, #L2_CACHE_INV_WAY_REG]
532 /* Poll Invalidate By Way register */
533 ldr r2, [r0, #L2_CACHE_INV_WAY_REG]
536 /*** End of L2 operations ***/
540 * End of ARM1136 init
561 /* If SDRAM has been setup, bypass clock/WEIM setup */
562 cmp pc, #SDRAM_BASE_ADDR
563 blo external_boot_cont
564 cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
565 blo internal_boot_cont
575 HWInitialise_skip_SDRAM_setup:
577 add r2, r0, #0x1000 // 4K window
579 blo Normal_Boot_Continue
581 bhs Normal_Boot_Continue
584 /* Copy image from flash to SDRAM first */
585 ldr r1, MXC_REDBOOT_ROM_START
594 and r0, pc, r1 /* offset of pc */
595 ldr r1, MXC_REDBOOT_ROM_START
602 // Check if x16/2kb page
603 // ldr r7, CCM_BASE_ADDR_W
604 // ldr r7, [r7, #0xC]
605 // ands r7, r7, #(1 << 30)
606 ldr r0, NFC_BASE_W //r0: nfc base. Reloaded after each page copying
607 mov r1, #TX37_NAND_PAGE_SIZE //r1: starting flash addr to be copied. Updated constantly
608 // ???? should be dynamic based on the page size kevin todo
609 add r2, r0, #TX37_NAND_PAGE_SIZE //r2: end of 3rd RAM buf. Doesn't change ?? dynamic
611 ldr r11, NFC_IP_BASE_W //r11: NFC IP register base. Doesn't change
612 add r12, r0, #0x1E00 //r12: NFC AXI register base. Doesn't change
613 ldr r14, MXC_REDBOOT_ROM_START
614 add r13, r14, #REDBOOT_IMAGE_SIZE //r13: end of SDRAM address for copying. Doesn't change
615 add r14, r14, r1 //r14: starting SDRAM address for copying. Updated constantly
617 //unlock internal buffer
619 add r3, r3, #0x00FF0000
624 mov r3, #0x20000 // BLS = 2 -> Buffer Lock Set = unlocked
625 add r3, r3, #0x4 // WPC = 4 -> write protection command = unlock blocks
626 str r3, [r11, #0x0] // kevin - revist for multiple CS ??
633 mov r3, #NAND_LAUNCH_FCMD
637 // start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, nflash_dev_info->base_mask);
640 do_addr_input //1st addr cycle
643 do_addr_input //2nd addr cycle
648 do_addr_input //3rd addr cycle
653 do_addr_input //4th addr cycle
657 mov r3, #NAND_LAUNCH_FCMD
661 // write RBA=0 to NFC_CONFIGURATION1
665 // writel(mode & 0xFF, NAND_LAUNCH_REG)
678 bge NAND_Copy_Main_done
679 add r1, r1, #TX37_NAND_PAGE_SIZE
685 Normal_Boot_Continue:
686 #ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
687 /* Copy image from flash to SDRAM first */
690 ldr r1, MXC_REDBOOT_ROM_START
692 beq HWInitialise_skip_SDRAM_copy
694 add r2, r0, #REDBOOT_IMAGE_SIZE
703 and r0, pc, r1 /* offset of pc */
704 ldr r1, MXC_REDBOOT_ROM_START
708 #endif /* CYG_HAL_STARTUP_ROMRAM */
710 HWInitialise_skip_SDRAM_copy:
713 * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity
716 // Set up a stack [for calling C code]
717 ldr r1, =__startup_stack
718 ldr r2, =RAM_BANK0_BASE
726 mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
727 orr r1, r1, #7 // enable MMU bit
728 orr r1, r1, #0x800 // enable z bit
732 mcr MMU_CP, 0, r1, MMU_Control, c0
733 mov pc,r2 /* Change address spaces */
736 .endm // _platform_setup1
738 #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
739 #define PLATFORM_SETUP1
743 .endm /* init_spba */
745 /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
748 * Set all MPROTx to be non-bufferable, trusted for R/W,
749 * not forced to user-mode.
751 ldr r0, AIPS1_CTRL_BASE_ADDR_W
752 ldr r1, AIPS1_PARAM_W
755 ldr r0, AIPS2_CTRL_BASE_ADDR_W
758 .endm /* init_aips */
760 /* MAX (Multi-Layer AHB Crossbar Switch) setup */
762 ldr r0, MAX_BASE_ADDR_W
764 /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
766 str r1, [r0, #0x000] /* for S0 */
767 str r1, [r0, #0x100] /* for S1 */
768 str r1, [r0, #0x200] /* for S2 */
769 str r1, [r0, #0x300] /* for S3 */
770 str r1, [r0, #0x400] /* for S4 */
771 /* SGPCR - always park on last master */
773 str r1, [r0, #0x010] /* for S0 */
774 str r1, [r0, #0x110] /* for S1 */
775 str r1, [r0, #0x210] /* for S2 */
776 str r1, [r0, #0x310] /* for S3 */
777 str r1, [r0, #0x410] /* for S4 */
778 /* MGPCR - restore default values */
780 str r1, [r0, #0x800] /* for M0 */
781 str r1, [r0, #0x900] /* for M1 */
782 str r1, [r0, #0xA00] /* for M2 */
783 str r1, [r0, #0xB00] /* for M3 */
784 str r1, [r0, #0xC00] /* for M4 */
785 str r1, [r0, #0xD00] /* for M5 */
795 ===========================
801 * All other clocks can be figured out based on this.
804 * Step 1: Switch to step clock
806 ldr r0, CCM_BASE_ADDR_W
808 str r1, [r0, #CLKCTL_CCSR]
810 /* Step 2: Setup PLL's */
811 /* Set PLL1 to be 532MHz */
812 ldr r0, PLL1_BASE_ADDR_W
816 str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */
818 str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
821 str r1, [r0, #PLL_DP_OP]
823 str r1, [r0, #PLL_DP_MFD]
825 str r1, [r0, #PLL_DP_MFN]
828 str r1, [r0, #PLL_DP_HFS_OP]
830 str r1, [r0, #PLL_DP_HFS_MFD]
832 str r1, [r0, #PLL_DP_HFS_MFN]
834 /* Now restart PLL 1 */
835 ldr r1, PLL_VAL_0x1232
836 str r1, [r0, #PLL_DP_CTL]
838 ldr r1, [r0, #PLL_DP_CTL]
843 * Step 2: Setup PLL2 to 665 MHz.
845 ldr r0, PLL2_BASE_ADDR_W
849 str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */
851 str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
854 str r1, [r0, #PLL_DP_OP]
856 str r1, [r0, #PLL_DP_MFD]
858 str r1, [r0, #PLL_DP_MFN]
861 str r1, [r0, #PLL_DP_HFS_OP]
863 str r1, [r0, #PLL_DP_HFS_MFD]
865 str r1, [r0, #PLL_DP_HFS_MFN]
867 /* Now restart PLL 2 */
868 ldr r1, PLL_VAL_0x1232
869 str r1, [r0, #PLL_DP_CTL]
871 ldr r1, [r0, #PLL_DP_CTL]
876 * Set PLL 3 to 216MHz
878 ldr r0, PLL3_BASE_ADDR_W
880 ldr r1, PLL_VAL_0x222
881 str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */
883 str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
886 str r1, [r0, #PLL_DP_OP]
888 str r1, [r0, #PLL_DP_MFD]
890 str r1, [r0, #PLL_DP_MFN]
893 str r1, [r0, #PLL_DP_HFS_OP]
895 str r1, [r0, #PLL_DP_HFS_MFD]
897 str r1, [r0, #PLL_DP_HFS_MFN]
899 /* Now restart PLL 3 */
900 ldr r1, PLL_VAL_0x232
901 str r1, [r0, #PLL_DP_CTL]
904 ldr r1, [r0, #PLL_DP_CTL]
907 /* End of PLL 3 setup */
909 /* Setup the ARM platform clock dividers */
910 ldr r0, PLATFORM_BASE_ADDR_W
911 ldr r1, PLATFORM_CLOCK_DIV_W
915 * Step 3: switching to PLL 1 and restore default register values.
917 ldr r0, CCM_BASE_ADDR_W
919 str r1, [r0, #CLKCTL_CCSR]
922 add r1, r1, #0x00000F0
923 str r1, [r0, #CLKCTL_CCOSR]
924 /* Use 133MHz for DDR clock */
926 str r1, [r0, #CLKCTL_CAMR]
927 /* Use PLL 2 for UART's, get 66.5MHz from it */
928 ldr r1, CCM_VAL_0xA5A6A020
929 str r1, [r0, #CLKCTL_CSCMR1]
930 ldr r1, CCM_VAL_0x01450B21
931 str r1, [r0, #CLKCTL_CSCDR1]
934 str r1, [r0, #CLKCTL_CBCDR7]
937 .endm /* init_clock */
941 /* Configure M4IF registers, VPU and IPU given higher priority (=0x4)
942 IPU accesses with ID=0x1 given highest priority (=0xA) */
944 ldr r0, M4IF_0x00000a01
945 str r0, [r1, #M4IF_FIDBP]
947 ldr r0, M4IF_0x00000404
948 str r0, [r1, #M4IF_FBPM0]
949 .endm /* init_m4if */
952 ldr r0, ESDCTL_BASE_W
955 str r1, [r0, #ESDCTL_ESDCTL0]
957 @ wait for SDRAM ready
958 ldr r2, [r0, #ESDCTL_ESDMISC]
962 /* Precharge command */
963 ldr r1, SDRAM_CMD_PRECHG
964 str r1, [r0, #ESDCTL_ESDSCR]
966 /* 2 refresh commands */
967 ldr r1, SDRAM_CMD_SLFRFSH
969 str r1, [r0, #ESDCTL_ESDSCR]
972 /* LMR with CAS Latency=3 and BurstLength=3->8words */
973 ldr r1, SDRAM_CMD_MODEREG
974 str r1, [r0, #ESDCTL_ESDSCR]
976 /* 13 ROW, 9 COL, 32Bit, SREF=4 */
977 ldr r1, SDRAM_ESDCTL0_VAL
978 str r1, [r0, #ESDCTL_ESDCTL0]
980 /* Timing parameters */
981 ldr r1, SDRAM_ESDCFG0_VAL
982 str r1, [r0, #ESDCTL_ESDCFG0]
984 /* MDDR enable, RALAT=1 */
985 ldr r1, SDRAM_ESDMISC_VAL
986 str r1, [r0, #ESDCTL_ESDMISC]
990 str r1, [r0, #ESDCTL_ESDSCR]
993 .macro do_wait_op_done
996 ands r3, r3, #NFC_IPC_INT
1000 .endm // do_wait_op_done
1002 .macro do_addr_input
1004 mov r3, #NAND_LAUNCH_FADD
1007 .endm // do_addr_input
1009 /* To support 133MHz DDR */
1011 ldr r0, IOMUXC_BASE_ADDR_W
1013 // DDR signal setup for D16-D31 and drive strength
1031 str r8, [r0, #0x4A8]
1032 str r8, [r0, #0x4B0]
1033 str r8, [r0, #0x4B4]
1034 str r8, [r0, #0x4E0]
1035 str r8, [r0, #0x4FC]
1036 str r8, [r0, #0x504]
1037 str r8, [r0, #0x48C]
1038 str r8, [r0, #0x49C]
1046 .endm /* init_iomux */
1048 #define PLATFORM_VECTORS _platform_vectors
1049 .macro _platform_vectors
1050 .globl _board_BCR, _board_CFG
1051 _board_BCR: .long 0 // Board Control register shadow
1052 _board_CFG: .long 0 // Board Configuration (read at RESET)
1055 KaRo_MSG: .asciz "KARO TX37 " __DATE__ " " __TIME__ "\n"
1056 ARM_PPMRR: .word 0x80000016
1057 L2CACHE_PARAM: .word 0x0003001B
1058 WDOG1_BASE_W: .word WDOG1_BASE_ADDR
1059 IIM_SREV_REG_VAL: .word IIM_BASE_ADDR + IIM_SREV_OFF
1060 AIPS1_CTRL_BASE_ADDR_W: .word AIPS1_CTRL_BASE_ADDR
1061 AIPS2_CTRL_BASE_ADDR_W: .word AIPS2_CTRL_BASE_ADDR
1062 AIPS1_PARAM_W: .word 0x77777777
1063 MAX_BASE_ADDR_W: .word MAX_BASE_ADDR
1064 MAX_PARAM1: .word 0x00302154
1065 ESDCTL_BASE_W: .word ESDCTL_BASE
1066 M4IF_BASE_W: .word M4IF_BASE
1067 M4IF_0x00000a01: .word 0x00000a01
1068 M4IF_0x00000404: .word 0x00000404
1069 NFC_BASE_W: .word NFC_BASE
1070 NFC_IP_BASE_W: .word NFC_IP_BASE
1071 SDRAM_CMD_PRECHG: .word 0x04008008
1072 SDRAM_CMD_SLFRFSH: .word 0x00008010
1073 SDRAM_CMD_MODEREG: .word 0x00338018
1074 SDRAM_ESDCTL0_VAL: .word 0xB2120000
1075 SDRAM_0x899F6BBA: .word 0x899F6BBA
1076 SDRAM_0x000A1104: .word 0x000A1104
1077 SDRAM_ESDCFG0_VAL: .word 0x70395729
1078 SDRAM_ESDMISC_VAL: .word 0x000A0084
1079 IOMUXC_BASE_ADDR_W: .word IOMUXC_BASE_ADDR
1080 GPIO2_BASE_ADDR_W: .word GPIO2_BASE_ADDR
1081 MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - REDBOOT_OFFSET
1082 SDRAM_ADDR_MASK: .word 0xfff00000
1083 CONST_0x0FFF: .word 0x0FFF
1084 CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
1085 PLATFORM_BASE_ADDR_W: .word PLATFORM_BASE_ADDR
1086 PLATFORM_CLOCK_DIV_W: .word 0x00077713
1087 CCM_VAL_0x01450B21: .word 0x01450B21
1088 CCM_VAL_0xA5A6A020: .word 0xA5A6A020
1089 PLL_VAL_0x222: .word 0x222
1090 PLL_VAL_0x232: .word 0x232
1091 PLL1_BASE_ADDR_W: .word PLL1_BASE_ADDR
1092 PLL2_BASE_ADDR_W: .word PLL2_BASE_ADDR
1093 PLL3_BASE_ADDR_W: .word PLL3_BASE_ADDR
1094 PLL_VAL_0x1232: .word 0x1232
1096 /*--------------------------------------------------------------------------*/
1097 /* end of hal_platform_setup.h */
1098 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */