1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 //=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 // You should have received a copy of the GNU General Public License along
26 // with eCos; if not, write to the Free Software Foundation, Inc.,
27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
31 // with other works to produce a work based on this file, this file does not
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33 // License. However the source code for this file must still be made available
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40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //===========================================================================
45 #include <pkgconf/system.h> // System-wide configuration info
46 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
47 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
48 #include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
49 #include <cyg/hal/hal_mmu.h> // MMU definitions
50 #include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
52 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
53 #define PLATFORM_SETUP1 _platform_setup1
54 #define CYGHWR_HAL_ARM_HAS_MMU
56 #ifdef CYG_HAL_STARTUP_ROMRAM
57 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
60 //#define NFC_2K_BI_SWAP
61 #define SDRAM_FULL_PAGE_BIT 0x100
62 #define SDRAM_FULL_PAGE_MODE 0x37
63 #define SDRAM_BURST_MODE 0x33
65 #define CYGHWR_HAL_ROM_VADDR 0x0
68 #define UNALIGNED_ACCESS_ENABLE
69 #define SET_T_BIT_DISABLE
70 #define BRANCH_PREDICTION_ENABLE
73 #define DCDGEN(i,type, addr, data) \
79 #define PLATFORM_PREAMBLE flash_header
80 //flash header & DCD @ 0x400
84 app_code_jump_v: .long reset_vector
85 app_code_barker: .long 0xB1 // barker code
86 app_code_csf: .long (0x97f40000 - 0x1000) // reserve 4K for csf
87 dcd_ptr_ptr: .long dcd_ptr
88 super_root_key: .long hab_super_root_key
89 dcd_ptr: .long dcd_data
90 app_dest_ptr: .long 0x97f00000
92 dcd_data: .long 0xB17219E9 // Fixed. can't change.
96 dcd_len: .long (38*12)
97 // DDR IOMUX configuration
98 // Control, Data, Address pads are in their default state: HIGH DS, FAST SR.
99 DCDGEN(1, 4, IOMUXC_BASE_ADDR + 0x4b8, 0x000000e7) // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS
100 DCDGEN(2, 4, IOMUXC_BASE_ADDR + 0x4d4, 0x000000e4) // DQM0 DS high, slew rate slow
101 DCDGEN(3, 4, IOMUXC_BASE_ADDR + 0x4d8, 0x000000e4) // DQM1 DS high, slew rate slow
102 DCDGEN(4, 4, IOMUXC_BASE_ADDR + 0x4dc, 0x000000e4) // DQM2 DS high, slew rate slow
103 DCDGEN(5, 4, IOMUXC_BASE_ADDR + 0x4e0, 0x000000e4) // DQM3 DS high, slew rate slow
104 DCDGEN(6, 4, IOMUXC_BASE_ADDR + 0x4bc, 0x000000c4) // SDQS0 DS high, slew rate slow
105 DCDGEN(7, 4, IOMUXC_BASE_ADDR + 0x4c0, 0x000000c4) // SDQS1 DS high, slew rate slow
106 DCDGEN(8, 4, IOMUXC_BASE_ADDR + 0x4c4, 0x000000c4) // SDQS2 DS high, slew rate slow
107 DCDGEN(9, 4, IOMUXC_BASE_ADDR + 0x4c8, 0x000000c4) // SDQS3 DS high, slew rate slow
108 DCDGEN(10, 4, IOMUXC_BASE_ADDR + 0x8a4, 0x00000004) // DRAM_B0
109 DCDGEN(11, 4, IOMUXC_BASE_ADDR + 0x8ac, 0x00000004) // DRAM_B1
110 DCDGEN(12, 4, IOMUXC_BASE_ADDR + 0x8b8, 0x00000004) // DRAM_B2
111 DCDGEN(13, 4, IOMUXC_BASE_ADDR + 0x82c, 0x00000004) // DRAM_B3
112 DCDGEN(14, 4, IOMUXC_BASE_ADDR + 0x878, 0x00000000) // DRAM_B0_SR
113 DCDGEN(15, 4, IOMUXC_BASE_ADDR + 0x880, 0x00000000) // DRAM_B1_SR
114 DCDGEN(16, 4, IOMUXC_BASE_ADDR + 0x88c, 0x00000000) // DRAM_B2_SR
115 DCDGEN(17, 4, IOMUXC_BASE_ADDR + 0x89c, 0x00000000) // DRAM_B3_SR
117 DCDGEN(18, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x83220000) // ESDCTL0: Enable controller
118 DCDGEN(19, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008) // ESDSCR: Precharge command
119 DCDGEN(20, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010) // ESDSCR: Refresh command
120 DCDGEN(21, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010) // ESDSCR: Refresh command
121 DCDGEN(22, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00338018) // ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8)
122 DCDGEN(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0060801a) // ESDSCR: EMR with Half Drive strength
123 DCDGEN(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000) // ESDSCR
124 DCDGEN(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xC3220000) // ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8
125 // ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
126 // tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
127 DCDGEN(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0xC33574AA)
128 DCDGEN(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000a1700) // ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2
130 DCDGEN(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x83220000) // ESDCTL1: Enable controller
131 DCDGEN(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c) // ESDSCR: Precharge command
132 DCDGEN(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014) // ESDSCR: Refresh command
133 DCDGEN(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014) // ESDSCR: Refresh command
134 DCDGEN(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0033801c) // ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8)
135 DCDGEN(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0060801e) // ESDSCR: EMR with Half Drive strength
136 DCDGEN(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004) // ESDSCR
137 DCDGEN(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xC3220000) // ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8
138 // ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
139 // tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
140 DCDGEN(36, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0xC33574AA)
141 DCDGEN(37, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000) // ESDSCR - clear "configuration request" bit
142 DCDGEN(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY5, 0x00f58000) //Delay line write - -11
145 dcd_len: .long (57*12)
148 //DDR2 IOMUX configuration
149 DCDGEN(1, 4, IOMUXC_BASE_ADDR + 0x8a0, 0x200)
150 DCDGEN(2, 4, IOMUXC_BASE_ADDR + 0x50c, 0x20c5)
151 DCDGEN(3, 4, IOMUXC_BASE_ADDR + 0x510, 0x20c5)
152 DCDGEN(4, 4, IOMUXC_BASE_ADDR + 0x83c, 0x2)
153 DCDGEN(5, 4, IOMUXC_BASE_ADDR + 0x848, 0x2)
154 DCDGEN(6, 4, IOMUXC_BASE_ADDR + 0x4b8, 0xe7)
155 DCDGEN(7, 4, IOMUXC_BASE_ADDR + 0x4bc, 0x45)
156 DCDGEN(8, 4, IOMUXC_BASE_ADDR + 0x4c0, 0x45)
157 DCDGEN(9, 4, IOMUXC_BASE_ADDR + 0x4c4, 0x45)
158 DCDGEN(10, 4, IOMUXC_BASE_ADDR + 0x4c8, 0x45)
159 DCDGEN(11, 4, IOMUXC_BASE_ADDR + 0x820, 0x0)
160 DCDGEN(12, 4, IOMUXC_BASE_ADDR + 0x4a4, 0x3)
161 DCDGEN(13, 4, IOMUXC_BASE_ADDR + 0x4a8, 0x3)
162 DCDGEN(14, 4, IOMUXC_BASE_ADDR + 0x4ac, 0xe3)
163 DCDGEN(15, 4, IOMUXC_BASE_ADDR + 0x4b0, 0xe3)
164 DCDGEN(16, 4, IOMUXC_BASE_ADDR + 0x4b4, 0xe3)
165 DCDGEN(17, 4, IOMUXC_BASE_ADDR + 0x4cc, 0xe3)
166 DCDGEN(18, 4, IOMUXC_BASE_ADDR + 0x4d0, 0xe2)
167 //13 ROW, 10 COL, 32Bit, SREF=4 Micron Model
169 DCDGEN(19, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x82a20000)
170 DCDGEN(20, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x82a20000)
171 DCDGEN(21, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad0d0)
172 DCDGEN(22, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0x333574aa)
173 DCDGEN(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0x333574aa)
175 DCDGEN(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
176 DCDGEN(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801a)
177 DCDGEN(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801b)
178 DCDGEN(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008019)
179 DCDGEN(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x07328018)
180 DCDGEN(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
181 DCDGEN(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
182 DCDGEN(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
183 DCDGEN(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x06328018)
184 DCDGEN(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x03808019)
185 DCDGEN(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00428019)
186 DCDGEN(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000)
189 DCDGEN(36, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
190 DCDGEN(37, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801e)
191 DCDGEN(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801f)
192 DCDGEN(39, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801d)
193 DCDGEN(40, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0732801c)
194 DCDGEN(41, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
195 DCDGEN(42, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
196 DCDGEN(43, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
197 DCDGEN(44, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0632801c)
198 DCDGEN(45, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0380801d)
199 DCDGEN(46, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0042801d)
200 DCDGEN(47, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004)
202 DCDGEN(48, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xb2a20000)
203 DCDGEN(49, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xb2a20000)
204 DCDGEN(50, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad6d0)
205 DCDGEN(51, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDGPR, 0x90000000)
206 DCDGEN(52, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
209 DCDGEN(53, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY1, 0x00048000)
210 DCDGEN(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY2, 0x000e8000)
211 DCDGEN(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY3, 0x00ff8000)
212 DCDGEN(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY4, 0x00fa8000)
213 DCDGEN(57, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY5, 0x00ed8000)
215 image_len: .long 256 * 1024 // 256K for Redboot and csf
219 //#define ENABLE_IMPRECISE_ABORT
221 // This macro represents the initial startup code for the platform
222 .macro _platform_setup1
223 FSL_BOARD_SETUP_START:
224 ldr r1, =ROM_BASE_ADDR
225 ldr r3, [r1, #ROM_SI_REV_OFFSET]
229 ldr r0, =GPC_BASE_ADDR
230 cmp r3, #0x10 // r3 contains the silicon rev
231 ldrls r1, =0x1FC00000
232 ldrhi r1, =0x1A800000
235 #ifdef ENABLE_IMPRECISE_ABORT
236 mrs r1, spsr // save old spsr
237 mrs r0, cpsr // read out the cpsr
238 bic r0, r0, #0x100 // clear the A bit
239 msr spsr, r0 // update spsr
240 add lr, pc, #0x8 // update lr
241 movs pc, lr // update cpsr
246 msr spsr, r1 // restore old spsr
249 // explicitly disable L2 cache
250 mrc 15, 0, r0, c1, c0, 1
252 mcr 15, 0, r0, c1, c0, 1
254 // reconfigure L2 cache aux control reg
255 mov r0, #0xC0 // tag RAM
256 add r0, r0, #0x4 // data RAM
257 orr r0, r0, #(1 << 24) // disable write allocate delay
258 orr r0, r0, #(1 << 23) // disable write allocate combine
259 orr r0, r0, #(1 << 22) // disable write allocate
261 cmp r3, #0x10 // r3 contains the silicon rev
262 orrls r0, r0, #(1 << 25) // disable write combine for TO 2 and lower revs
264 mcr 15, 1, r0, c9, c0, 2
271 #ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
272 /* Check if need to copy image to Redboot ROM space */
275 ldr r1, MXC_REDBOOT_ROM_START
279 add r2, r0, #REDBOOT_IMAGE_SIZE
281 1: ldmia r0!, {r3-r10}
287 and r0, pc, r1 /* offset of pc */
288 ldr r1, =(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000 + 0x8)
294 #endif /* CYG_HAL_STARTUP_ROMRAM */
297 /* Skip clock setup if already booted up */
298 ldr r0, =IRAM_BASE_ADDR
300 ldr r1, =FROM_SPI_NOR_FLASH
302 beq Normal_Boot_Continue
303 ldr r1, =FROM_MMC_FLASH
305 beq Normal_Boot_Continue
306 ldr r1, =FROM_NAND_FLASH
308 beq Normal_Boot_Continue
313 Normal_Boot_Continue:
317 * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity
320 // Set up a stack [for calling C code]
321 ldr r1, =__startup_stack
322 ldr r2, =RAM_BANK0_BASE
328 /* Workaround for arm errata #709718 */
329 //Setup PRRR so device is always mapped to non-shared
330 mrc MMU_CP, 0, r1, c10, c2, 0 // Read Primary Region Remap Register
332 mcr MMU_CP, 0, r1, c10, c2, 0 // Write Primary Region Remap Register
336 mrc MMU_CP, 0, r1, MMU_Control, c0
337 orr r1, r1, #7 // enable MMU bit
338 orr r1, r1, #0x800 // enable z bit
339 orr r1, r1, #(1 << 28) // Enable TEX remap
340 mcr MMU_CP, 0, r1, MMU_Control, c0
342 /* Workaround for arm errata #621766 */
343 mrc MMU_CP, 0, r1, MMU_Control, c0, 1
344 orr r1, r1, #(1 << 5) // enable L1NEON bit
345 mcr MMU_CP, 0, r1, MMU_Control, c0, 1
347 mov pc,r2 /* Change address spaces */
353 // Save shadow copy of BCR, also hardware configuration
357 str r9, [r1] // Saved far above...
359 .endm // _platform_setup1
361 #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
362 #define PLATFORM_SETUP1
365 /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
368 * Set all MPROTx to be non-bufferable, trusted for R/W,
369 * not forced to user-mode.
371 ldr r0, AIPS1_CTRL_BASE_ADDR_W
372 ldr r1, AIPS1_PARAM_W
375 ldr r0, AIPS2_CTRL_BASE_ADDR_W
379 .endm /* init_aips */
382 ldr r0, CCM_BASE_ADDR_W
384 /* Gate of clocks to the peripherals first */
386 str r1, [r0, #CLKCTL_CCGR0]
388 str r1, [r0, #CLKCTL_CCGR1]
389 str r1, [r0, #CLKCTL_CCGR2]
390 str r1, [r0, #CLKCTL_CCGR3]
393 str r1, [r0, #CLKCTL_CCGR4]
395 str r1, [r0, #CLKCTL_CCGR5]
397 str r1, [r0, #CLKCTL_CCGR6]
399 /* Disable IPU and HSC dividers */
401 str r1, [r0, #CLKCTL_CCDR]
403 /* Make sure to switch the DDR away from PLL 1 */
404 ldr r1, CCM_VAL_0x19239145
405 str r1, [r0, #CLKCTL_CBCDR]
406 /* make sure divider effective */
407 1: ldr r1, [r0, #CLKCTL_CDHIPR]
411 /* Switch ARM to step clock */
413 str r1, [r0, #CLKCTL_CCSR]
417 /* Switch peripheral to PLL 3 */
418 ldr r0, CCM_BASE_ADDR_W
419 ldr r1, CCM_VAL_0x000010C0
420 str r1, [r0, #CLKCTL_CBCMR]
421 ldr r1, CCM_VAL_0x13239145
422 str r1, [r0, #CLKCTL_CBCDR]
424 /* Switch peripheral to PLL 2 */
425 ldr r0, CCM_BASE_ADDR_W
426 ldr r1, CCM_VAL_0x19239145
427 str r1, [r0, #CLKCTL_CBCDR]
428 ldr r1, CCM_VAL_0x000020C0
429 str r1, [r0, #CLKCTL_CBCMR]
433 /* Set the platform clock dividers */
434 ldr r0, PLATFORM_BASE_ADDR_W
435 ldr r1, PLATFORM_CLOCK_DIV_W
436 str r1, [r0, #PLATFORM_ICGC]
438 ldr r0, CCM_BASE_ADDR_W
439 /* Run TO 3.0 at Full speed, for other TO's wait till we increase VDDGP */
440 ldr r1, =ROM_BASE_ADDR
441 ldr r3, [r1, #ROM_SI_REV_OFFSET]
445 str r1, [r0, #CLKCTL_CACRR]
447 /* Switch ARM back to PLL 1. */
449 str r1, [r0, #CLKCTL_CCSR]
452 /* Use lp_apm (24MHz) source for perclk */
453 ldr r1, CCM_VAL_0x000020C2
454 str r1, [r0, #CLKCTL_CBCMR]
455 // ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz
457 ldr r1, CCM_VAL_0x61E35100
459 ldr r1, CCM_VAL_0x59E35100
461 str r1, [r0, #CLKCTL_CBCDR]
463 /* Restore the default values in the Gate registers */
465 str r1, [r0, #CLKCTL_CCGR0]
466 str r1, [r0, #CLKCTL_CCGR1]
467 str r1, [r0, #CLKCTL_CCGR2]
468 str r1, [r0, #CLKCTL_CCGR3]
469 str r1, [r0, #CLKCTL_CCGR4]
470 str r1, [r0, #CLKCTL_CCGR5]
471 str r1, [r0, #CLKCTL_CCGR6]
473 /* Use PLL 2 for UART's, get 66.5MHz from it */
474 ldr r1, CCM_VAL_0xA5A2A020
475 str r1, [r0, #CLKCTL_CSCMR1]
476 ldr r1, CCM_VAL_0x00C30321
477 str r1, [r0, #CLKCTL_CSCDR1]
479 /* make sure divider effective */
480 1: ldr r1, [r0, #CLKCTL_CDHIPR]
485 str r1, [r0, #CLKCTL_CCDR]
487 // for cko - for ARM div by 8
489 add r1, r1, #0x00000F0
490 str r1, [r0, #CLKCTL_CCOSR]
491 .endm /* init_clock */
493 .macro setup_pll pll_nr, mhz
494 ldr r0, BASE_ADDR_W_\pll_nr
495 ldr r1, PLL_VAL_0x1232
496 str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */
498 str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
501 str r1, [r0, #PLL_DP_OP]
502 str r1, [r0, #PLL_DP_HFS_OP]
504 ldr r1, W_DP_MFD_\mhz
505 str r1, [r0, #PLL_DP_MFD]
506 str r1, [r0, #PLL_DP_HFS_MFD]
508 ldr r1, W_DP_MFN_\mhz
509 str r1, [r0, #PLL_DP_MFN]
510 str r1, [r0, #PLL_DP_HFS_MFN]
512 /* Now restart PLL */
513 ldr r1, PLL_VAL_0x1232
514 str r1, [r0, #PLL_DP_CTL]
515 wait_pll_lock\pll_nr\mhz:
516 ldr r1, [r0, #PLL_DP_CTL]
518 beq wait_pll_lock\pll_nr\mhz
524 ldr r0, M4IF_0x00000203
525 str r0, [r1, #M4IF_FBPM0]
528 str r0, [r1, #M4IF_FBPM1]
530 ldr r0, M4IF_0x00120125
531 str r0, [r1, #M4IF_FPWC]
533 ldr r0, M4IF_0x001901A3
534 str r0, [r1, #M4IF_MIF4]
536 .endm /* init_m4if */
539 cmp r3, #0x10 // r3 contains the silicon rev
541 /* Decrease the DRAM SDCLK to HIGH Drive strength */
542 ldr r0, IOMUXC_BASE_ADDR_W
545 /* Change the delay line configuration */
546 ldr r0, ESDCTL_BASE_W
548 str r1, [r0, #ESDCTL_ESDCDLY1]
550 str r1, [r0, #ESDCTL_ESDCDLY2]
552 str r1, [r0, #ESDCTL_ESDCDLY3]
554 str r1, [r0, #ESDCTL_ESDCDLY4]
556 str r1, [r0, #ESDCTL_ESDCDLY5]
560 #define PLATFORM_VECTORS _platform_vectors
561 .macro _platform_vectors
562 .globl _board_BCR, _board_CFG
563 _board_BCR: .long 0 // Board Control register shadow
564 _board_CFG: .long 0 // Board Configuration (read at RESET)
568 .globl _KARO_STRUCT_SIZE
570 .word 0 // reserve space structure length
572 .globl _KARO_CECFG_START
575 .word 0 // reserve space for CE configuration
578 .globl _KARO_CECFG_END
582 IIM_SREV_REG_VAL: .word IIM_BASE_ADDR + IIM_SREV_OFF
583 AIPS1_CTRL_BASE_ADDR_W: .word AIPS1_CTRL_BASE_ADDR
584 AIPS2_CTRL_BASE_ADDR_W: .word AIPS2_CTRL_BASE_ADDR
585 AIPS1_PARAM_W: .word 0x77777777
586 MAX_BASE_ADDR_W: .word MAX_BASE_ADDR
587 MAX_PARAM1: .word 0x00302154
588 ESDCTL_BASE_W: .word ESDCTL_BASE_ADDR
589 M4IF_BASE_W: .word M4IF_BASE_ADDR
590 M4IF_0x00120125: .word 0x00120125
591 M4IF_0x001901A3: .word 0x001901A3
592 M4IF_0x00000203: .word 0x00000203
593 SDRAM_0x04008008: .word 0x04008008
594 SDRAM_0x00008010: .word 0x00008010
595 SDRAM_0x00338018: .word 0x00338018
596 SDRAM_0xB2220000: .word 0xB2220000
597 SDRAM_0x899F6BBA: .word 0x899F6BBA
598 SDRAM_0xB02567A9: .word 0xB02567A9
599 SDRAM_0x000A0104: .word 0x000A0104
600 IOMUXC_BASE_ADDR_W: .word IOMUXC_BASE_ADDR
601 MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
602 CONST_0x0FFF: .word 0x0FFF
603 CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
604 CCM_VAL_0x0000E3C2: .word 0x0000E3C2
605 CCM_VAL_0x000020C2: .word 0x000020C2
606 CCM_VAL_0x013B9100: .word 0x013B9100
607 CCM_VAL_0x59E35100: .word 0x59E35100
608 CCM_VAL_0x61E35100: .word 0x61E35100
609 CCM_VAL_0x19239145: .word 0x19239145
610 CCM_VAL_0xA5A2A020: .word 0xA5A2A020
611 CCM_VAL_0x00C30321: .word 0x00C30321
612 CCM_VAL_0x000010C0: .word 0x000010C0
613 CCM_VAL_0x13239145: .word 0x13239145
614 CCM_VAL_0x000020C0: .word 0x000020C0
615 PLL_VAL_0x222: .word 0x222
616 PLL_VAL_0x232: .word 0x232
617 BASE_ADDR_W_PLL1: .word PLL1_BASE_ADDR
618 BASE_ADDR_W_PLL2: .word PLL2_BASE_ADDR
619 BASE_ADDR_W_PLL3: .word PLL3_BASE_ADDR
620 PLL_VAL_0x1232: .word 0x1232
621 W_DP_OP_800: .word DP_OP_800
622 W_DP_MFD_800: .word DP_MFD_800
623 W_DP_MFN_800: .word DP_MFN_800
624 W_DP_OP_700: .word DP_OP_700
625 W_DP_MFD_700: .word DP_MFD_700
626 W_DP_MFN_700: .word DP_MFN_700
627 W_DP_OP_400: .word DP_OP_400
628 W_DP_MFD_400: .word DP_MFD_400
629 W_DP_MFN_400: .word DP_MFN_400
630 W_DP_OP_532: .word DP_OP_532
631 W_DP_MFD_532: .word DP_MFD_532
632 W_DP_MFN_532: .word DP_MFN_532
633 W_DP_OP_665: .word DP_OP_665
634 W_DP_MFD_665: .word DP_MFD_665
635 W_DP_MFN_665: .word DP_MFN_665
636 W_DP_OP_216: .word DP_OP_216
637 W_DP_MFD_216: .word DP_MFD_216
638 W_DP_MFN_216: .word DP_MFN_216
639 PLATFORM_BASE_ADDR_W: .word PLATFORM_BASE_ADDR
640 PLATFORM_CLOCK_DIV_W: .word 0x00000124
642 /*---------------------------------------------------------------------------*/
643 /* end of hal_platform_setup.h */
644 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */