packages/hal/arm/mx51/3stack/v2_0/src/board_misc.c

   1 //==========================================================================
   2 //
   3 //      board_misc.c
   4 //
   5 //      HAL misc board support code for the board
   6 //
   7 //==========================================================================
   8 //####ECOSGPLCOPYRIGHTBEGIN####
   9 // -------------------------------------------
  10 // This file is part of eCos, the Embedded Configurable Operating System.
  11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  12 //
  13 // eCos is free software; you can redistribute it and/or modify it under
  14 // the terms of the GNU General Public License as published by the Free
  15 // Software Foundation; either version 2 or (at your option) any later version.
  16 //
  17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  20 // for more details.
  21 //
  22 // You should have received a copy of the GNU General Public License along
  23 // with eCos; if not, write to the Free Software Foundation, Inc.,
  24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  25 //
  26 // As a special exception, if other files instantiate templates or use macros
  27 // or inline functions from this file, or you compile this file and link it
  28 // with other works to produce a work based on this file, this file does not
  29 // by itself cause the resulting work to be covered by the GNU General Public
  30 // License. However the source code for this file must still be made available
  31 // in accordance with section (3) of the GNU General Public License.
  32 //
  33 // This exception does not invalidate any other reasons why a work based on
  34 // this file might be covered by the GNU General Public License.
  35 //
  36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  37 // at http://sources.redhat.com/ecos/ecos-license/
  38 // -------------------------------------------
  39 //####ECOSGPLCOPYRIGHTEND####
  40 //========================================================================*/
  41
  42 #include <pkgconf/hal.h>
  43 #include <pkgconf/system.h>
  44 #include <redboot.h>
  45 #include CYGBLD_HAL_PLATFORM_H
  46
  47 #include <cyg/infra/cyg_type.h>         // base types
  48 #include <cyg/infra/cyg_trac.h>         // tracing macros
  49 #include <cyg/infra/cyg_ass.h>          // assertion macros
  50
  51 #include <cyg/hal/hal_io.h>             // IO macros
  52 #include <cyg/hal/hal_arch.h>           // Register state info
  53 #include <cyg/hal/hal_diag.h>
  54 #include <cyg/hal/hal_intr.h>           // Interrupt names
  55 #include <cyg/hal/hal_cache.h>
  56 #include <cyg/hal/hal_soc.h>         // Hardware definitions
  57 #include <cyg/hal/fsl_board.h>             // Platform specifics
  58 #include <cyg/hal/mx51_iomux.h>
  59 #include <cyg/io/mxc_i2c.h>
  60 #include <cyg/io/imx_nfc.h>
  61 #include <cyg/infra/diag.h>             // diag_printf
  62
  63 // All the MM table layout is here:
  64 #include <cyg/hal/hal_mm.h>
  65 #include <cyg/io/imx_spi.h>
  66
  67 externC void* memset(void *, int, size_t);
  68 extern nfc_iomuxsetup_func_t *nfc_iomux_setup;
  69
  70 unsigned int cpld_base_addr;
  71
  72 struct spi_v2_3_reg spi_nor_reg;
  73 struct imx_spi_dev imx_spi_nor = {
  74     base : CSPI2_BASE_ADDR,
  75     freq : 25000000,
  76     ss_pol : IMX_SPI_ACTIVE_LOW,
  77     ss : 1,
  78     fifo_sz : 32,
  79     us_delay: 0,
  80     reg : &spi_nor_reg,
  81 };
  82
  83 imx_spi_init_func_t *spi_nor_init;
  84 imx_spi_xfer_func_t *spi_nor_xfer;
  85
  86 void hal_mmu_init(void)
  87 {
  88     unsigned long ttb_base = RAM_BANK0_BASE + 0x4000;
  89     unsigned long i;
  90
  91     /*
  92      * Set the TTB register
  93      */
  94     asm volatile ("mcr  p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
  95
  96     /*
  97      * Set the Domain Access Control Register
  98      */
  99     i = ARM_ACCESS_DACR_DEFAULT;
 100     asm volatile ("mcr  p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
 101
 102     /*
 103      * First clear all TT entries - ie Set them to Faulting
 104      */
 105     memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
 106
 107     /*              Actual   Virtual  Size   Attributes                                                    Function  */
 108     /*              Base     Base     MB     cached?           buffered?        access permissions                 */
 109     /*              xxx00000 xxx00000                                                                                */
 110     X_ARM_MMU_SECTION(0x000, 0x200,   0x1,   ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* ROM */
 111     X_ARM_MMU_SECTION(0x1FF, 0x1FF,   0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IRAM */
 112     X_ARM_MMU_SECTION(0x300, 0x300,   0x100, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* GPU */
 113     X_ARM_MMU_SECTION(0x400, 0x400,   0x200, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IPUv3D */
 114     X_ARM_MMU_SECTION(0x600, 0x600,   0x300, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* periperals */
 115     X_ARM_MMU_SECTION(0x900, 0x000,   0x080, ARM_CACHEABLE, ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* SDRAM */
 116     X_ARM_MMU_SECTION(0x900, 0x900,   0x080, ARM_CACHEABLE, ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* SDRAM */
 117     X_ARM_MMU_SECTION(0x900, 0x980,   0x080, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
 118     X_ARM_MMU_SECTION(0xA00, 0xA00,   0x100, ARM_CACHEABLE, ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* SDRAM */
 119     X_ARM_MMU_SECTION(0xB80, 0xB80,   0x10,  ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/
 120     X_ARM_MMU_SECTION(0xCC0, 0xCC0,   0x040, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS4/5/NAND Flash buffer */
 121 }
 122
 123 void mxc_i2c_init(unsigned int module_base)
 124 {
 125     unsigned int reg;
 126
 127     switch (module_base) {
 128     case I2C_BASE_ADDR:
 129         reg = IOMUXC_BASE_ADDR + 0x210; // i2c SDA
 130         writel(0x11, reg);
 131         reg = IOMUXC_BASE_ADDR + 0x600;
 132         writel(0x1ad, reg);
 133         reg = IOMUXC_BASE_ADDR + 0x9B4;
 134         writel(0x1, reg);
 135
 136         reg = IOMUXC_BASE_ADDR + 0x224; // i2c SCL
 137         writel(0x11, reg);
 138         reg = IOMUXC_BASE_ADDR + 0x614;
 139         writel(0x1ad, reg);
 140         reg = IOMUXC_BASE_ADDR + 0x9B0;
 141         writel(0x1, reg);
 142         break;
 143     case I2C2_BASE_ADDR:
 144         /* Workaround for Atlas Lite */
 145         writel(0x0, IOMUXC_BASE_ADDR + 0x3CC); // i2c SCL
 146         writel(0x0, IOMUXC_BASE_ADDR + 0x3D0); // i2c SDA
 147         reg = readl(GPIO1_BASE_ADDR + 0x0);
 148         reg |= 0xC;  // write a 1 on the SCL and SDA lines
 149         writel(reg, GPIO1_BASE_ADDR + 0x0);
 150         reg = readl(GPIO1_BASE_ADDR + 0x4);
 151         reg |= 0xC;  // configure GPIO lines as output
 152         writel(reg, GPIO1_BASE_ADDR + 0x4);
 153         reg = readl(GPIO1_BASE_ADDR + 0x0);
 154         reg &= ~0x4 ; // set SCL low for a few milliseconds
 155         writel(reg, GPIO1_BASE_ADDR + 0x0);
 156         hal_delay_us(20000);
 157         reg |= 0x4;
 158         writel(reg, GPIO1_BASE_ADDR + 0x0);
 159         hal_delay_us(10);
 160         reg = readl(GPIO1_BASE_ADDR + 0x4);
 161         reg &= ~0xC;  // configure GPIO lines back as input
 162         writel(reg, GPIO1_BASE_ADDR + 0x4);
 163         writel(0x12, IOMUXC_BASE_ADDR + 0x3CC);  // i2c SCL
 164         writel(0x3, IOMUXC_BASE_ADDR + 0x9B8);
 165         writel(0x1ed, IOMUXC_BASE_ADDR + 0x7D4);
 166
 167         writel(0x12, IOMUXC_BASE_ADDR + 0x3D0); // i2c SDA
 168         writel(0x3, IOMUXC_BASE_ADDR + 0x9BC);
 169         writel(0x1ed, IOMUXC_BASE_ADDR + 0x7D8);
 170         break;
 171     default:
 172         diag_printf("Invalid I2C base: 0x%x\n", module_base);
 173         return;
 174     }
 175 }
 176
 177 void mxc_ata_iomux_setup(void)
 178 {
 179     // config NANDF_WE_B pad for pata instance DIOW port
 180     // config_pad_mode(NANDF_WE_B, ALT1);
 181     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_WE_B);
 182     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_WE_B);
 183
 184     // config NANDF_RE_B pad for pata instance DIOR port
 185     // config_pad_mode(NANDF_RE_B, ALT1);
 186     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_RE_B);
 187     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_RE_B);
 188
 189     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_ALE);
 190     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_ALE);
 191
 192     // config NANDF_CLE pad for pata instance PATA_RESET_B port
 193     // config_pad_mode(NANDF_CLE, ALT1);
 194     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CLE);
 195     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CLE);
 196
 197     // config NANDF_WP_B pad for pata instance DMACK port
 198     // config_pad_mode(NANDF_WP_B, ALT1);
 199     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_WP_B);
 200     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_WP_B);
 201
 202     // config NANDF_RB0 pad for pata instance DMARQ port
 203     // config_pad_mode(NANDF_RB0, 0x1);
 204     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_RB0);
 205     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_RB0);
 206
 207     // config NANDF_RB1 pad for pata instance IORDY port
 208     // config_pad_mode(NANDF_RB1, 0x1);
 209     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_RB1);
 210     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_RB1);
 211
 212     // config NANDF_RB5 pad for pata instance INTRQ port
 213     // config_pad_mode(NANDF_RB5, 0x1);
 214     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_GPIO_NAND);
 215     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_GPIO_NAND);
 216
 217     // config NANDF_CS2 pad for pata instance CS_0 port
 218     // config_pad_mode(NANDF_CS2, 0x1);
 219     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2);
 220     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS2);
 221
 222     // config NANDF_CS3 pad for pata instance CS_1 port
 223     // config_pad_mode(NANDF_CS3, 0x1);
 224     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3);
 225     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS3);
 226
 227     // config NANDF_CS4 pad for pata instance DA_0 port
 228     // config_pad_mode(NANDF_CS4, 0x1);
 229     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS4);
 230     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS4);
 231
 232     // config NANDF_CS5 pad for pata instance DA_1 port
 233     // config_pad_mode(NANDF_CS5, 0x1);
 234     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS5);
 235     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS5);
 236
 237     // config NANDF_CS6 pad for pata instance DA_2 port
 238     // config_pad_mode(NANDF_CS6, 0x1);
 239     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS6);
 240     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS6);
 241
 242     // config NANDF_D15 pad for pata instance PATA_DATA[15] port
 243     // config_pad_mode(NANDF_D15, 0x1);
 244     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D15);
 245     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D15);
 246
 247     // config NANDF_D14 pad for pata instance PATA_DATA[14] port
 248     // config_pad_mode(NANDF_D14, 0x1);
 249     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D14);
 250     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D14);
 251
 252     // config NANDF_D13 pad for pata instance PATA_DATA[13] port
 253     // config_pad_mode(NANDF_D13, 0x1);
 254     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D13);
 255     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D13);
 256
 257     // config NANDF_D12 pad for pata instance PATA_DATA[12] port
 258     // config_pad_mode(NANDF_D12, 0x1);
 259     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D12);
 260     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D12);
 261
 262     // config NANDF_D11 pad for pata instance PATA_DATA[11] port
 263     // config_pad_mode(NANDF_D11, 0x1);
 264     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D11);
 265     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D11);
 266
 267     // config NANDF_D10 pad for pata instance PATA_DATA[10] port
 268     // config_pad_mode(NANDF_D10, 0x1);
 269     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D10);
 270     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D10);
 271
 272     // config NANDF_D9 pad for pata instance PATA_DATA[9] port
 273     // config_pad_mode(NANDF_D9, 0x1);
 274     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D9);
 275     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D9);
 276
 277     // config NANDF_D8 pad for pata instance PATA_DATA[8] port
 278     // config_pad_mode(NANDF_D8, 0x1);
 279     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D8);
 280     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D8);
 281
 282     // config NANDF_D7 pad for pata instance PATA_DATA[7] port
 283     // config_pad_mode(NANDF_D7, 0x1);
 284     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D7);
 285     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D7);
 286
 287     // config NANDF_D6 pad for pata instance PATA_DATA[6] port
 288     // config_pad_mode(NANDF_D6, 0x1);
 289     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D6);
 290     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D6);
 291
 292     // config NANDF_D5 pad for pata instance PATA_DATA[5] port
 293     // config_pad_mode(NANDF_D5, 0x1);
 294     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D5);
 295     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D5);
 296
 297     // config NANDF_D4 pad for pata instance PATA_DATA[4] port
 298     // config_pad_mode(NANDF_D4, 0x1);
 299     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D4);
 300     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D4);
 301
 302     // config NANDF_D3 pad for pata instance PATA_DATA[3] port
 303     // config_pad_mode(NANDF_D3, 0x1);
 304     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D3);
 305     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D3);
 306
 307     // config NANDF_D2 pad for pata instance PATA_DATA[2] port
 308     // config_pad_mode(NANDF_D2, 0x1);
 309     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D2);
 310     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D2);
 311
 312     // config NANDF_D1 pad for pata instance PATA_DATA[1] port
 313     // config_pad_mode(NANDF_D1, 0x1);
 314     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D1);
 315     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D1);
 316
 317     // config NANDF_D0 pad for pata instance PATA_DATA[0] port
 318     // config_pad_mode(NANDF_D0, 0x1);
 319     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D0);
 320     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D0);
 321 }
 322
 323 static void mxc_fec_setup(void)
 324 {
 325     volatile unsigned int reg;
 326
 327     /* No FEC support for TO 2.0 and higher yet */
 328     if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) >= 0x2)
 329         return;
 330     /*FEC_TX_CLK*/
 331     writel(0x2, IOMUXC_BASE_ADDR + 0x0390);
 332     writel(0x180, IOMUXC_BASE_ADDR + 0x085C);
 333     writel(0x1, IOMUXC_BASE_ADDR + 0x09D0);
 334
 335     /*FEC_RX_CLK*/
 336     writel(0x2, IOMUXC_BASE_ADDR + 0x0388);
 337     writel(0x180, IOMUXC_BASE_ADDR + 0x0854);
 338     writel(0x1, IOMUXC_BASE_ADDR + 0x09C4);
 339
 340     /*FEC_RX_DV*/
 341     writel(0x2, IOMUXC_BASE_ADDR + 0x038c);
 342     writel(0x180, IOMUXC_BASE_ADDR + 0x0858);
 343     writel(0x1, IOMUXC_BASE_ADDR + 0x09C8);
 344
 345     /*FEC_COL*/
 346     writel(0x2, IOMUXC_BASE_ADDR + 0x0384);
 347     writel(0x180, IOMUXC_BASE_ADDR + 0x0850);
 348     writel(0x1, IOMUXC_BASE_ADDR + 0x9A8);
 349
 350     /*FEC_RDATA0*/
 351     writel(0x2, IOMUXC_BASE_ADDR + 0x0394);
 352     writel(0x180, IOMUXC_BASE_ADDR + 0x0860);
 353     writel(0x1, IOMUXC_BASE_ADDR + 0x09B4);
 354
 355     /*FEC_TDATA0*/
 356     writel(0x2, IOMUXC_BASE_ADDR + 0x0398);
 357     writel(0x5, IOMUXC_BASE_ADDR + 0x864);
 358
 359     /*FEC_TX_EN*/
 360     writel(0x2, IOMUXC_BASE_ADDR + 0x0380);
 361     writel(0x5, IOMUXC_BASE_ADDR + 0x084C);
 362
 363     /*FEC_MDC*/
 364     writel(0x2, IOMUXC_BASE_ADDR + 0x034C);
 365     writel(0x5, IOMUXC_BASE_ADDR + 0x0818);
 366
 367     /*FEC_MDIO*/
 368     writel(0x2, IOMUXC_BASE_ADDR + 0x0350);
 369     writel(0x1CD, IOMUXC_BASE_ADDR + 0x081C);
 370     writel(0x1, IOMUXC_BASE_ADDR + 0x09B0);
 371
 372     /*FEC_TX_ERR*/
 373     writel(0x2, IOMUXC_BASE_ADDR + 0x0344);
 374     writel(0x5, IOMUXC_BASE_ADDR + 0x0810);
 375
 376     /*FEC_RX_ERR*/
 377     writel(0x2, IOMUXC_BASE_ADDR + 0x0360);
 378     writel(0x180, IOMUXC_BASE_ADDR + 0x082C);
 379     writel(0x1, IOMUXC_BASE_ADDR + 0x09CC);
 380
 381     /*FEC_CRS*/
 382     writel(0x2, IOMUXC_BASE_ADDR + 0x0348);
 383     writel(0x180, IOMUXC_BASE_ADDR + 0x0814);
 384     writel(0x1, IOMUXC_BASE_ADDR + 0x09AC);
 385
 386     /*FEC_RDATA1*/
 387     writel(0x2, IOMUXC_BASE_ADDR + 0x0354);
 388     writel(0x180, IOMUXC_BASE_ADDR + 0x0820);
 389     writel(0x1, IOMUXC_BASE_ADDR + 0x09B8);
 390
 391     /*FEC_TDATA1*/
 392     writel(0x2, IOMUXC_BASE_ADDR + 0x0374);
 393     writel(0x5, IOMUXC_BASE_ADDR + 0x0840);
 394
 395     /*FEC_RDATA2*/
 396     writel(0x2, IOMUXC_BASE_ADDR + 0x0358);
 397     writel(0x180, IOMUXC_BASE_ADDR + 0x0824);
 398     writel(0x1, IOMUXC_BASE_ADDR + 0x09BC);
 399
 400     /*FEC_TDATA2*/
 401     writel(0x2, IOMUXC_BASE_ADDR + 0x0378);
 402     writel(0x5, IOMUXC_BASE_ADDR + 0x0844);
 403
 404     /*FEC_RDATA3*/
 405     writel(0x2, IOMUXC_BASE_ADDR + 0x035C);
 406     writel(0x180, IOMUXC_BASE_ADDR + 0x0828);
 407     writel(0x1, IOMUXC_BASE_ADDR + 0x09C0);
 408
 409     /*FEC_TDATA3*/
 410     writel(0x2, IOMUXC_BASE_ADDR + 0x037C);
 411     writel(0x5, IOMUXC_BASE_ADDR + 0x0848);
 412
 413     reg = readl(GPIO3_BASE_ADDR + 0x0);
 414     reg &= ~0x40;  // Lower reset line
 415     writel(reg, GPIO3_BASE_ADDR + 0x0);
 416
 417     reg = readl(GPIO3_BASE_ADDR + 0x4);
 418     reg |= 0x40;  // configure GPIO lines as output
 419     writel(reg, GPIO3_BASE_ADDR + 0x4);
 420
 421     /* Reset the ethernet controller over GPIO */
 422     writel(0x4, IOMUXC_BASE_ADDR + 0x02CC);
 423     writel(0xC5, IOMUXC_BASE_ADDR + 0x078C);
 424
 425     hal_delay_us(200);
 426
 427     reg = readl(GPIO3_BASE_ADDR + 0x0);
 428     reg |= 0x40;
 429     writel(reg, GPIO3_BASE_ADDR + 0x0);
 430 }
 431
 432 static void mxc_nfc_iomux_setup(void)
 433 {
 434     writel(0x0, IOMUXC_BASE_ADDR + 0x108);
 435     writel(0x0, IOMUXC_BASE_ADDR + 0x10C);
 436     writel(0x0, IOMUXC_BASE_ADDR + 0x110);
 437     writel(0x0, IOMUXC_BASE_ADDR + 0x114);
 438     writel(0x0, IOMUXC_BASE_ADDR + 0x118);
 439     writel(0x0, IOMUXC_BASE_ADDR + 0x11C);
 440     writel(0x0, IOMUXC_BASE_ADDR + 0x120);
 441     writel(0x0, IOMUXC_BASE_ADDR + 0x124);
 442     writel(0x0, IOMUXC_BASE_ADDR + 0x128);
 443     writel(0x0, IOMUXC_BASE_ADDR + 0x12C);
 444     writel(0x0, IOMUXC_BASE_ADDR + 0x130);
 445     writel(0x0, IOMUXC_BASE_ADDR + 0x134);
 446     writel(0x0, IOMUXC_BASE_ADDR + 0x138);
 447     writel(0x0, IOMUXC_BASE_ADDR + 0x13C);
 448     writel(0x0, IOMUXC_BASE_ADDR + 0x140);
 449     writel(0x0, IOMUXC_BASE_ADDR + 0x144);
 450     writel(0x0, IOMUXC_BASE_ADDR + 0x148);
 451     writel(0x0, IOMUXC_BASE_ADDR + 0x14C);
 452     writel(0x0, IOMUXC_BASE_ADDR + 0x150);
 453     writel(0x0, IOMUXC_BASE_ADDR + 0x154);
 454     writel(0x0, IOMUXC_BASE_ADDR + 0x158);
 455     writel(0x0, IOMUXC_BASE_ADDR + 0x15C);
 456     writel(0x0, IOMUXC_BASE_ADDR + 0x160);
 457     writel(0x0, IOMUXC_BASE_ADDR + 0x164);
 458     writel(0x0, IOMUXC_BASE_ADDR + 0x168);
 459     writel(0x0, IOMUXC_BASE_ADDR + 0x16C);
 460     writel(0x0, IOMUXC_BASE_ADDR + 0x170);
 461     writel(0x0, IOMUXC_BASE_ADDR + 0x174);
 462     writel(0x0, IOMUXC_BASE_ADDR + 0x178);
 463     writel(0x0, IOMUXC_BASE_ADDR + 0x17C);
 464     writel(0x0, IOMUXC_BASE_ADDR + 0x180);
 465     writel(0x0, IOMUXC_BASE_ADDR + 0x184);
 466     writel(0x0, IOMUXC_BASE_ADDR + 0x188);
 467     writel(0x0, IOMUXC_BASE_ADDR + 0x18C);
 468     writel(0x0, IOMUXC_BASE_ADDR + 0x190);
 469 }
 470
 471 #define REV_ATLAS_LITE_2_0 0x20
 472
 473 void setup_core_voltages(void)
 474 {
 475     struct mxc_i2c_request rq;
 476     unsigned char buf[4];
 477
 478     if (i2c_init(I2C2_BASE_ADDR, 170000) == 0) {
 479         rq.dev_addr = 0x8;
 480         rq.reg_addr_sz = 1;
 481         rq.buffer_sz = 3;
 482         rq.buffer = buf;
 483
 484         if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) <= 0x2) {
 485             /* Set core voltage to 1.1V */
 486             rq.reg_addr = 24;
 487             i2c_xfer(1, &rq, 1);
 488             buf[2] = (buf[2] & (~0x1F)) | 0x14;
 489             i2c_xfer(1, &rq, 0);
 490
 491             /* Setup VCC (SW2) to 1.25 */
 492             rq.reg_addr = 25;
 493             i2c_xfer(1, &rq, 1);
 494             buf[2] = (buf[2] & (~0x1F)) | 0x1A;
 495             i2c_xfer(1, &rq, 0);
 496
 497             /* Setup 1V2_DIG1 (SW3) to 1.25 */
 498             rq.reg_addr = 26;
 499             i2c_xfer(1, &rq, 1);
 500             buf[2] = (buf[2] & (~0x1F)) | 0x1A;
 501             i2c_xfer(1, &rq, 0);
 502             hal_delay_us(50);
 503             /* Raise the core frequency to 800MHz */
 504             writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR);
 505         } else {
 506             /* TO 3.0 */
 507             /* Setup VCC (SW2) to 1.225 */
 508             rq.reg_addr = 25;
 509             i2c_xfer(1, &rq, 1);
 510             buf[2] = (buf[2] & (~0x1F)) | 0x19;
 511             i2c_xfer(1, &rq, 0);
 512
 513             /* Setup 1V2_DIG1 (SW3) to 1.2 */
 514             rq.reg_addr = 26;
 515             i2c_xfer(1, &rq, 1);
 516             buf[2] = (buf[2] & (~0x1F)) | 0x18;
 517             i2c_xfer(1, &rq, 0);
 518         }
 519
 520         rq.reg_addr = 7;
 521         i2c_xfer(1, &rq, 1);
 522
 523         if (((buf[2] & 0x1F) < REV_ATLAS_LITE_2_0) || (((buf[1] >> 1) & 0x3) == 0)) {
 524             /* Set switchers in PWM mode for Atlas 2.0 and lower */
 525             /* Setup the switcher mode for SW1 & SW2*/
 526             rq.reg_addr = 28;
 527             i2c_xfer(1, &rq, 1);
 528             buf[2] = (buf[2] & (~0xF)) | 0x5;
 529             buf[1] = (buf[1] & (~0x3C)) | 0x14;
 530             i2c_xfer(1, &rq, 0);
 531
 532             /* Setup the switcher mode for SW3 & SW4*/
 533             rq.reg_addr = 29;
 534             i2c_xfer(1, &rq, 1);
 535             buf[2] = (buf[2] & (~0xF)) | 0x5;
 536             buf[1] = (buf[1] & (~0xF)) | 0x5;
 537             i2c_xfer(1, &rq, 0);
 538         } else {
 539             /* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */
 540             /* Setup the switcher mode for SW1 & SW2*/
 541             rq.reg_addr = 28;
 542             i2c_xfer(1, &rq, 1);
 543             buf[2] = (buf[2] & (~0xF)) | 0x8;
 544             buf[1] = (buf[1] & (~0x3C)) | 0x20;
 545             i2c_xfer(1, &rq, 0);
 546
 547             /* Setup the switcher mode for SW3 & SW4*/
 548             rq.reg_addr = 29;
 549             i2c_xfer(1, &rq, 1);
 550             buf[2] = (buf[2] & (~0xF)) | 0x8;
 551             buf[1] = (buf[1] & (~0xF)) | 0x8;
 552             i2c_xfer(1, &rq, 0);
 553         }
 554     }
 555 }
 556
 557 //
 558 // Platform specific initialization
 559 //
 560
 561 void plf_hardware_init(void)
 562 {
 563         unsigned long sw_rest_reg, weim_base;
 564
 565         setup_core_voltages();
 566         // CS5 setup
 567         writel(0, IOMUXC_BASE_ADDR + 0xF4);
 568         weim_base = WEIM_BASE_ADDR + 0x78;
 569         writel(0x00410089, weim_base + CSGCR1);
 570         writel(0x00000002, weim_base + CSGCR2);
 571         // RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0
 572         writel(0x32260000, weim_base + CSRCR1);
 573         // APR=0
 574         writel(0x00000000, weim_base + CSRCR2);
 575         // WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0, WCSA=0, WCSN=0
 576         writel(0x72080F00, weim_base + CSWCR1);
 577         cpld_base_addr = CS5_BASE_ADDR;
 578
 579         /* Reset interrupt status reg */
 580         writew(0x1F, cpld_base_addr + PBC_INT_REST);
 581         writew(0x00, cpld_base_addr + PBC_INT_REST);
 582         writew(0xFFFF, cpld_base_addr + PBC_INT_MASK);
 583
 584         /* Reset the XUART and Ethernet controllers */
 585         sw_rest_reg = readw(cpld_base_addr + PBC_SW_RESET);
 586         sw_rest_reg |= 0x9;
 587         writew(sw_rest_reg, cpld_base_addr + PBC_SW_RESET);
 588         sw_rest_reg &= ~0x9;
 589         writew(sw_rest_reg, cpld_base_addr + PBC_SW_RESET);
 590
 591         // UART1
 592         //RXD
 593         writel(0x0, IOMUXC_BASE_ADDR + 0x228);
 594         writel(0x1C5, IOMUXC_BASE_ADDR + 0x618);
 595         //TXD
 596         writel(0x0, IOMUXC_BASE_ADDR + 0x22c);
 597         writel(0x1C5, IOMUXC_BASE_ADDR + 0x61c);
 598         //RTS
 599         writel(0x0, IOMUXC_BASE_ADDR + 0x230);
 600         writel(0x1C4, IOMUXC_BASE_ADDR + 0x620);
 601         //CTS
 602         writel(0x0, IOMUXC_BASE_ADDR + 0x234);
 603         writel(0x1C4, IOMUXC_BASE_ADDR + 0x624);
 604         // enable GPIO1_9 for CLKO and GPIO1_8 for CLKO2
 605         writel(0x00000004, 0x73fa83E8);
 606         writel(0x00000004, 0x73fa83Ec);
 607
 608         // enable ARM clock div by 8
 609         writel(0x010900F0, CCM_BASE_ADDR + CLKCTL_CCOSR);
 610 #ifdef MXCFLASH_SELECT_NAND
 611         nfc_iomux_setup = (nfc_iomuxsetup_func_t*)mxc_nfc_iomux_setup;
 612 #endif
 613         mxc_fec_setup();
 614
 615         spi_nor_init = (imx_spi_init_func_t *)imx_spi_init_v2_3;
 616         spi_nor_xfer = (imx_spi_xfer_func_t *)imx_spi_xfer_v2_3;
 617 }
 618
 619
 620 void mxc_ipu_iomux_config(void)
 621 {
 622         // configure display data0~17 for Epson panel
 623         CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT0, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
 624         CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT0, 0x5);
 625         CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT1, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
 626         CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT1, 0x5);
 627         CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT2, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
 628         CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT2,0x5);
 629         CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT3, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
 630         CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT3, 0x5);
 631         CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT4, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
 632         CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT4, 0x5);
 633         CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT5, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
 634         CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT5, 0x5);
 635         CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT6, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
 636         CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT6, 0x5);
 637         CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT7, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
 638         CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT7, 0x5);
 639         CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT8, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
 640         CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT8, 0x5);
 641         CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT9, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
 642         CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT9, 0x5);
 643         CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT10, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
 644         CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT10, 0x5);
 645         CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT11, 0x5);
 646         CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT12, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
 647         CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT12, 0x5);
 648         CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT13, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
 649         CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT13, 0x5);
 650         CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT14, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
 651         CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT14, 0x5);
 652         CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT15, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
 653         CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT15, 0x5);
 654         CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT16, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
 655         CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT16, 0x5);
 656         CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT17, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
 657         CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT17, 0x5);
 658
 659         // DI1_PIN2 and DI1_PIN3, configured to be HSYNC and VSYNC of Epson LCD
 660         CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN2, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
 661         CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN3, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
 662
 663         // PCLK - DISP_CLK
 664         // No IOMUX configuration required, as there is no IOMUXing for this pin
 665
 666         // DRDY - PIN15
 667         // No IOMUX configuration required, as there is no IOMUXing for this pin
 668
 669         // configure this pin to be the SER_DISP_CS
 670
 671         CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_D1_CS, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT4);
 672         CONFIG_PIN(IOMUXC_SW_PAD_CTL_PAD_DI1_D1_CS,0x85);
 673
 674         // configure to be DISPB1_SER_RS
 675         CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP1, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
 676         CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI_GP1, 0x85);
 677         // configure to be SER_DISP1_CLK
 678         CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP2, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
 679         CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI_GP2, 0x85);
 680         // configure to be DISPB1_SER_DIO
 681         CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP3, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
 682         CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI_GP3, 0xC5);
 683         // configure to be DISPB1_SER_DIN
 684         CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP4, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
 685         CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI_GP4, 0xC4);
 686         //CS0
 687         CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_D0_CS, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT1);
 688         CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI1_D0_CS, 0x85);
 689         // WR
 690         CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN11, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT1);
 691         CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11, 0x85);
 692         // RD
 693         CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN12, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT1);
 694         CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI1_PIN12, 0x85);
 695         // RS
 696         CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN13, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT1);
 697         CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI1_PIN13, 0x85);
 698
 699 }
 700
 701 void mxc_mmc_init(unsigned int base_address)
 702 {
 703     switch(base_address) {
 704     case MMC_SDHC1_BASE_ADDR:
 705         /* SD1 CMD, SION bit */
 706         writel(0x10, IOMUXC_BASE_ADDR + 0x394);
 707        /* Configure SW PAD */
 708         /* SD1 CMD */
 709         writel(0xd5, IOMUXC_BASE_ADDR + 0x79C);
 710         /* SD1 CLK */
 711         writel(0xd5, IOMUXC_BASE_ADDR + 0x7A0);
 712         /* SD1 DAT0 */
 713         writel(0xd5, IOMUXC_BASE_ADDR + 0x7A4);
 714         /* SD1 DAT1 */
 715         writel(0xd5, IOMUXC_BASE_ADDR + 0x7A8);
 716         /* SD1 DAT2 */
 717         writel(0xd5, IOMUXC_BASE_ADDR + 0x7AC);
 718         /* SD1 DAT3 */
 719         writel(0xd5, IOMUXC_BASE_ADDR + 0x7B0);
 720         break;
 721     default:
 722         break;
 723     }
 724 }
 725
 726 void increase_core_voltage(bool i)
 727 {
 728     unsigned char buf[4];
 729     struct mxc_i2c_request rq;
 730
 731     if (i2c_init(I2C2_BASE_ADDR, 170000) == 0) {
 732         rq.dev_addr = 0x8;
 733         rq.reg_addr = 24;
 734         rq.reg_addr_sz = 1;
 735         rq.buffer_sz = 3;
 736         rq.buffer = buf;
 737
 738         i2c_xfer(1, &rq, 1);
 739
 740         if (i) {
 741             buf[2] = (buf[2] & (~0x1F)) | 0x17; //1.175
 742             //buf[2] = (buf[2] & (~0x1F)) | 0x18; //1.2
 743         } else {
 744             buf[2] = (buf[2] & (~0x1F)) | 0x12;
 745         }
 746         i2c_xfer(1, &rq, 0);
 747     } else {
 748         diag_printf("Cannot increase core voltage, failed to initialize I2C2\n");
 749     }
 750 }
 751
 752 void io_cfg_spi(struct imx_spi_dev *dev)
 753 {
 754     unsigned int reg;
 755
 756     switch (dev->base) {
 757     case CSPI1_BASE_ADDR:
 758         break;
 759     case CSPI2_BASE_ADDR:
 760         // Select mux mode: ALT2 mux port: MOSI of instance: ecspi2
 761         writel(0x2, IOMUXC_BASE_ADDR + 0x154);
 762         writel(0x105, IOMUXC_BASE_ADDR + 0x53C);
 763
 764         // Select mux mode: ALT2 mux port: MISO of instance: ecspi2.
 765         writel(0x2, IOMUXC_BASE_ADDR + 0x128);
 766         writel(0x105, IOMUXC_BASE_ADDR + 0x504);
 767
 768        // de-select SS0 of instance: ecspi1.
 769        writel(0x2, IOMUXC_BASE_ADDR + 0x298);
 770        writel(0x85, IOMUXC_BASE_ADDR + 0x698);
 771        // Select mux mode: ALT2 mux port: SS1 of instance: ecspi2.
 772        writel(0x2, IOMUXC_BASE_ADDR + 0x160);
 773        writel(0x105, IOMUXC_BASE_ADDR + 0x548);
 774
 775         // Select mux mode: ALT3 mux port: GPIO mode
 776         writel(0x3, IOMUXC_BASE_ADDR + 0x150);
 777         writel(0xE0, IOMUXC_BASE_ADDR + 0x538);
 778         reg = readl(GPIO3_BASE_ADDR + 0x0);
 779         reg |= 0x1000000;  // write a 1
 780         writel(reg, GPIO3_BASE_ADDR + 0x0);
 781         reg = readl(GPIO3_BASE_ADDR + 0x4);
 782         reg |= 0x1000000;  // configure GPIO lines as output
 783         writel(reg, GPIO3_BASE_ADDR + 0x4);
 784
 785         // Select mux mode: ALT2 mux port: SCLK of instance: ecspi2.
 786         writel(0x2, IOMUXC_BASE_ADDR + 0x124);
 787         writel(0x105, IOMUXC_BASE_ADDR + 0x500);
 788         break;
 789     default:
 790         break;
 791     }
 792 }
 793
 794
 795 #include CYGHWR_MEMORY_LAYOUT_H
 796
 797 typedef void code_fun(void);
 798
 799 void board_program_new_stack(void *func)
 800 {
 801     register CYG_ADDRESS stack_ptr asm("sp");
 802     register CYG_ADDRESS old_stack asm("r4");
 803     register code_fun *new_func asm("r0");
 804     old_stack = stack_ptr;
 805     stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
 806     new_func = (code_fun*)func;
 807     new_func();
 808     stack_ptr = old_stack;
 809 }
 810