1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 //=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
18 // Software Foundation; either version 2 or (at your option) any later version.
20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 // You should have received a copy of the GNU General Public License along
26 // with eCos; if not, write to the Free Software Foundation, Inc.,
27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
31 // with other works to produce a work based on this file, this file does not
32 // by itself cause the resulting work to be covered by the GNU General Public
33 // License. However the source code for this file must still be made available
34 // in accordance with section (3) of the GNU General Public License.
36 // This exception does not invalidate any other reasons why a work based on
37 // this file might be covered by the GNU General Public License.
39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //===========================================================================
45 #include <pkgconf/system.h> // System-wide configuration info
46 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
47 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
48 #include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
49 #include <cyg/hal/hal_mmu.h> // MMU definitions
50 #include <cyg/hal/karo_tx51.h> // Platform specific hardware definitions
51 #include CYGHWR_MEMORY_LAYOUT_H
53 #define CPU_CLK CYGNUM_HAL_ARM_TX51_CPU_CLK
54 #define SDRAM_CLK CYGNUM_HAL_ARM_TX51_SDRAM_CLK
56 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
57 #define PLATFORM_SETUP1 _platform_setup1
58 #define CYGHWR_HAL_ARM_HAS_MMU
60 #ifdef CYG_HAL_STARTUP_ROMRAM
61 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
64 #define TX51_NAND_PAGE_SIZE 2048
65 #define TX51_NAND_BLKS_PER_PAGE 64
67 #define DEBUG_LED_BIT 10
68 #define LED_GPIO_BASE GPIO4_BASE_ADDR
69 #define LED_MUX_OFFSET 0x1d0
70 #define LED_MUX_MODE 0x13
72 #define LED_ON LED_CTRL #1
73 #define LED_OFF LED_CTRL #0
75 #ifndef CYGOPT_HAL_ARM_TX51_DEBUG
83 #define CYGHWR_LED_MACRO LED_BLINK #\x
99 // switch user LED (GPIO4_10) on STK5
100 ldr r10, =LED_GPIO_BASE
104 ldr r9, [r10, #GPIO_DR]
105 orrne r9, #(1 << DEBUG_LED_BIT) @ LED ON
106 biceq r9, #(1 << DEBUG_LED_BIT) @ LED OFF
107 str r9, [r10, #GPIO_DR]
126 // initialize GPIO4_10 (PAD CSI2_D13) for LED on STK5
127 ldr r10, =LED_GPIO_BASE
129 ldr r9, [r10, #GPIO_DR]
130 bic r9, #(1 << DEBUG_LED_BIT)
131 str r9, [r10, #GPIO_DR]
133 ldr r9, [r10, #GPIO_GDIR]
134 orr r9, r9, #(1 << DEBUG_LED_BIT)
135 str r9, [r10, #GPIO_GDIR]
137 ldr r10, =IOMUXC_BASE_ADDR
138 mov r9, #LED_MUX_MODE
139 str r9, [r10, #LED_MUX_OFFSET]
142 #define DCDGEN(type, addr, data) .long type, addr, data
144 #define PLATFORM_PREAMBLE flash_header
146 // This macro represents the initial startup code for the platform
147 .macro _platform_setup1
148 KARO_TX51_SETUP_START:
155 ldr r1, =ROM_BASE_ADDR
156 ldr r11, [r1, #ROM_SI_REV_OFFSET]
160 ldr r0, =GPC_BASE_ADDR
161 cmp r11, #0x10 // r11 contains the silicon rev
162 ldrls r1, =0x1FC00000
163 ldrhi r1, =0x1A800000
166 // Explicitly disable L2 cache
167 mrc 15, 0, r0, c1, c0, 1
169 mcr 15, 0, r0, c1, c0, 1
171 // reconfigure L2 cache aux control reg
172 mov r0, #0xC0 // tag RAM
173 add r0, r0, #0x4 // data RAM
174 orr r0, r0, #(1 << 24) // disable write allocate delay
175 orr r0, r0, #(1 << 23) // disable write allocate combine
176 orr r0, r0, #(1 << 22) // disable write allocate
178 @ cc is still set from "cmp r11, #0x10" above
179 orrls r0, r0, #(1 << 25) @ disable write combine for TO 2 and lower revs
181 mcr 15, 1, r0, c9, c0, 2
189 #ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
191 #endif /* CYG_HAL_STARTUP_ROMRAM */
195 Normal_Boot_Continue:
198 * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity
202 @ Set up a stack [for calling C code]
203 ldr r1, =__startup_stack
204 ldr r2, =RAM_BANK0_BASE
211 /* Workaround for arm erratum #709718 */
212 @ Setup PRRR so device is always mapped to non-shared
213 mrc MMU_CP, 0, r1, c10, c2, 0 // Read Primary Region Remap Register
215 mcr MMU_CP, 0, r1, c10, c2, 0 // Write Primary Region Remap Register
219 mrc MMU_CP, 0, r1, MMU_Control, c0
220 orr r1, r1, #7 @ enable MMU bit
221 orr r1, r1, #0x800 @ enable z bit
222 orr r1, r1, #(1 << 28) @ Enable TEX remap, workaround for L1 cache issue
223 mcr MMU_CP, 0, r1, MMU_Control, c0
225 /* Workaround for arm errata #621766 */
226 mrc MMU_CP, 0, r1, MMU_Control, c0, 1
227 orr r1, r1, #(1 << 5) @ enable L1NEON bit
228 mcr MMU_CP, 0, r1, MMU_Control, c0, 1
230 mov pc, r2 @ Change address spaces
234 .endm @ _platform_setup1
236 /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
239 * Set all MPROTx to be non-bufferable, trusted for R/W,
240 * not forced to user-mode.
242 ldr r0, =AIPS1_CTRL_BASE_ADDR
246 ldr r0, =AIPS2_CTRL_BASE_ADDR
249 .endm /* init_aips */
252 ldr r0, =WDOG_BASE_ADDR
260 ldr r0, =CCM_BASE_ADDR
261 ldr r1, [r0, #CLKCTL_CCR]
265 orr r1, r1, #(1 << 12)
266 str r1, [r0, #CLKCTL_CCR]
268 ldr r1, [r0, #CLKCTL_CCSR]
269 bic r1, #(1 << 9) /* switch lp_apm to OSC */
270 str r1, [r0, #CLKCTL_CCSR]
272 /* Gate off clocks to the peripherals first */
274 str r1, [r0, #CLKCTL_CCGR0]
276 str r1, [r0, #CLKCTL_CCGR1]
277 str r1, [r0, #CLKCTL_CCGR2]
278 str r1, [r0, #CLKCTL_CCGR3]
281 str r1, [r0, #CLKCTL_CCGR4]
283 str r1, [r0, #CLKCTL_CCGR5]
285 str r1, [r0, #CLKCTL_CCGR6]
287 /* Disable IPU and HSC dividers */
289 str r1, [r0, #CLKCTL_CCDR]
291 /* Make sure to switch the DDR away from PLL 1 */
292 ldr r1, CCM_CBCDR_VAL1
293 str r1, [r0, #CLKCTL_CBCDR]
294 /* make sure divider effective */
296 ldr r1, [r0, #CLKCTL_CDHIPR]
300 /* Switch ARM to step clock */
301 ldr r1, [r0, #CLKCTL_CCSR]
303 str r1, [r0, #CLKCTL_CCSR]
314 /* Switch peripheral to PLL 3 */
315 ldr r1, CCM_CBCMR_VAL1
316 str r1, [r0, #CLKCTL_CBCMR]
318 ldr r1, CCM_CBCDR_VAL2
319 str r1, [r0, #CLKCTL_CBCDR]
323 /* Switch peripheral to PLL 2 */
324 ldr r1, CCM_CBCDR_VAL1
325 str r1, [r0, #CLKCTL_CBCDR]
326 /* Use lp_apm (24MHz) source for perclk */
327 ldr r1, CCM_CBCMR_VAL2
328 str r1, [r0, #CLKCTL_CBCMR]
332 /* Set the platform clock dividers */
333 ldr r2, =PLATFORM_BASE_ADDR
334 ldr r1, PLATFORM_CLOCK_DIV
335 str r1, [r2, #PLATFORM_ICGC]
337 /* Run TO 3.0 at Full speed, for other TO's wait till we increase VDDGP */
341 str r1, [r0, #CLKCTL_CACRR]
343 /* Switch ARM back to PLL 1. */
345 str r1, [r0, #CLKCTL_CCSR]
348 @ ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz
349 ldr r1, CCM_CBCDR_VAL3
350 str r1, [r0, #CLKCTL_CBCDR]
352 /* Restore the default values in the Gate registers */
354 str r1, [r0, #CLKCTL_CCGR0]
355 str r1, [r0, #CLKCTL_CCGR1]
356 str r1, [r0, #CLKCTL_CCGR2]
357 str r1, [r0, #CLKCTL_CCGR3]
358 str r1, [r0, #CLKCTL_CCGR4]
359 str r1, [r0, #CLKCTL_CCGR5]
360 str r1, [r0, #CLKCTL_CCGR6]
362 /* Use PLL 2 for UART's, get 66.5MHz from it */
363 ldr r1, CCM_CSCMR1_VAL
364 str r1, [r0, #CLKCTL_CSCMR1]
365 ldr r1, CCM_CSCDR1_VAL
366 str r1, [r0, #CLKCTL_CSCDR1]
368 /* make sure divider is in effect */
370 ldr r1, [r0, #CLKCTL_CDHIPR]
375 str r1, [r0, #CLKCTL_CCDR]
377 ldr r1, [r0, #CLKCTL_CCR]
378 bic r1, #(1 << 8) /* switch off FPM */
379 str r1, [r0, #CLKCTL_CCR]
382 .macro setup_pll pll_nr, mhz
383 ldr r2, BASE_ADDR_\pll_nr
385 /* implement workaround for ENGcm12051 */
386 mov r1, #0 @ Disable auto-restart (AREN)
387 str r1, [r2, #PLL_DP_CONFIG]
390 str r1, [r2, #PLL_DP_OP]
391 str r1, [r2, #PLL_DP_HFS_OP]
394 str r1, [r2, #PLL_DP_MFD]
395 str r1, [r2, #PLL_DP_HFS_MFD]
398 str r1, [r2, #PLL_DP_MFN]
399 str r1, [r2, #PLL_DP_HFS_MFN]
401 ldr r1, =((1 << 2) | 0x1232) @ Set DPLL ON; UPEN=1 BRMO=1 PLM=1
402 str r1, [r2, #PLL_DP_CTL]
404 ldr r1, [r2, #PLL_DP_CTL] @ Poll LRF
409 str r1, [r2, #PLL_DP_MFN]
410 str r1, [r2, #PLL_DP_HFS_MFN]
413 str r1, [r2, #PLL_DP_CONFIG] @ Assert LDREQ
415 ldr r1, [r2, #PLL_DP_CONFIG] @ Poll LDREQ
422 * since cache is disabled, this loop is more than enough
428 ldr r1, =0x1232 @ Set DPLL ON (set UPEN bit); BRMO=1
429 str r1, [r2, #PLL_DP_CTL]
431 mov r1, #(1 << 1) @ Enable auto-restart (AREN)
432 str r1, [r2, #PLL_DP_CONFIG]
435 str r1, [r2, #PLL_DP_OP]
436 str r1, [r2, #PLL_DP_HFS_OP]
438 ldr r1, W_DP_MFD_\mhz
439 str r1, [r2, #PLL_DP_MFD]
440 str r1, [r2, #PLL_DP_HFS_MFD]
442 ldr r1, W_DP_MFN_\mhz
443 str r1, [r2, #PLL_DP_MFN]
444 str r1, [r2, #PLL_DP_HFS_MFN]
446 mov r1, #((1 << 0) | (1 << 1))
447 str r1, [r2, #PLL_DP_CONFIG] @ Assert LDREQ + AREN
451 str r1, [r2, #PLL_DP_CTL]
453 ldr r1, [r2, #PLL_DP_CTL]
461 ldr r1, =M4IF_BASE_ADDR
462 ldr r0, M4IF_M4IF4_VAL
463 str r0, [r1, #M4IF_MIF4]
465 /* Configure M4IF registers, VPU and IPU given higher priority (=0x4) */
466 ldr r0, M4IF_FBPM0_VAL
467 str r0, [r1, #M4IF_FBPM0]
469 ldr r0, M4IF_FPWC_VAL
470 str r0, [r1, #M4IF_FPWC]
471 .endm /* init_m4if */
475 cmp r11, #0x10 // r11 contains the silicon rev
477 /* Decrease the DRAM SDCLK pads to HIGH Drive strength */
478 ldr r0, =IOMUXC_BASE_ADDR
481 /* Change the delay line configuration */
482 ldr r0, =ESDCTL_BASE_ADDR
484 str r1, [r0, #ESDCTL_ESDCDLY1]
486 str r1, [r0, #ESDCTL_ESDCDLY2]
488 str r1, [r0, #ESDCTL_ESDCDLY3]
490 str r1, [r0, #ESDCTL_ESDCDLY4]
492 str r1, [r0, #ESDCTL_ESDCDLY5]
496 #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
497 #define PLATFORM_SETUP1
500 #define PLATFORM_VECTORS _platform_vectors
501 .macro _platform_vectors
505 .globl _KARO_STRUCT_SIZE
507 .word 0 // reserve space structure length
509 .globl _KARO_CECFG_START
512 .word 0 // reserve space for CE configuration
515 .globl _KARO_CECFG_END
520 .ascii "KARO TX51 " __DATE__ " " __TIME__
523 /* SDRAM timing setup */
527 #if SDRAM_SIZE <= SZ_128M
528 #define RA_BITS (13 - 11) /* row addr bits - 11 */
530 #define RA_BITS (14 - 11) /* row addr bits - 11 */
533 #define CA_BITS (10 - 8) /* 0-2: col addr bits - 8 3: rsrvd */
534 #define DSIZ 2 /* 0: D[31..16] 1: D[15..D0] 2: D[31..0] 3: rsrvd */
535 #define SREFR 3 /* 0: disabled 1-5: 2^n rows/clock *: rsrvd */
536 #define SRT 0 /* 0: disabled *: 1: self refr. ... */
537 #define PWDT 0 /* 0: disabled 1: precharge pwdn
538 2: pwdn after 64 clocks 3: pwdn after 128 clocks */
539 #define ESDCTL_VAL (0x80000000 | (SREFR << 28) | (RA_BITS << 24) | (CA_BITS << 20) | \
540 (DSIZ << 16) | (SRT << 14) | (PWDT << 12))
542 #define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
544 .macro CK_VAL, name, clks, offs
548 .set \name, \clks - \offs
552 .macro NS_VAL, name, ns, offs
556 CK_VAL \name, NS_TO_CK(\ns), \offs
562 NS_VAL tRFC, 125, 10 /* clks - 10 (0..15) */
563 NS_VAL tXSR, 138, 25 /* clks - 25 (0..15) */
564 NS_VAL tXP, 25, 1 /* clks - 1 (0..7) */
565 CK_VAL tWTR, 1, 1 /* clks - 1 (0..1) */
566 NS_VAL tRP, 18, 2 /* clks - 2 (0..3) */
567 CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */
568 NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */
569 NS_VAL tRAS, 42, 1 /* clks - 1 (0..15) */
570 NS_VAL tRRD, 12, 1 /* clks - 1 (0..3) */
571 NS_VAL tRCD, 18, 1 /* clks - 1 (0..7) */
572 NS_VAL tRC, 60, 1 /* 0: 20 *: clks - 1 (0..15) */
574 /* MT46H64M32LF-5 or -6 */
575 NS_VAL tRFC, 72, 10 /* clks - 10 (0..15) */
576 NS_VAL tXSR, 113, 25 /* clks - 25 (0..15) */
577 CK_VAL tXP, 2, 1 /* clks - 1 (0..7) */
578 CK_VAL tWTR, 2, 1 /* clks - 1 (0..1) */
579 NS_VAL tRP, 18, 2 /* clks - 2 (0..3) */
580 CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */
581 NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */
582 NS_VAL tRAS, 42, 1 /* clks - 1 (0..15) */
583 NS_VAL tRRD, 12, 1 /* clks - 1 (0..3) */
584 NS_VAL tRCD, 18, 1 /* clks - 1 (0..7) */
585 NS_VAL tRC, 60, 1 /* 0: 20 *: clks - 1 (0..15) */
588 #define ESDCFG_VAL ((tRFC << 28) | (tXSR << 24) | (tXP << 21) | \
589 (tWTR << 20) | (tRP << 18) | (tMRD << 16) | \
590 (tRAS << 12) | (tRRD << 10) | (tWR << 7) | \
591 (tRCD << 4) | (tRC << 0))
595 #define ESDMISC_RALAT(n) (((n) & 0x3) << 7)
596 #define ESDMISC_DDR2_EN(n) (((n) & 0x1) << 4)
597 #define ESDMISC_DDR_EN(n) (((n) & 0x1) << 3)
598 #define ESDMISC_AP(n) (((n) & 0xf) << 16)
599 #define ESDMISC_VAL (ESDMISC_AP(10) | ESDMISC_RALAT(RALAT) | \
600 (LHD << 5) | ESDMISC_DDR2_EN(0) | ESDMISC_DDR_EN(0))
610 .long 0 // 0x97f40000 - 0x1000
614 .long 0 // hab_super_root_key
618 #ifndef RAM_BANK1_SIZE
619 .long RAM_BANK0_BASE + SDRAM_SIZE - REDBOOT_OFFSET
621 .long RAM_BANK1_BASE + RAM_BANK1_SIZE - REDBOOT_OFFSET
624 .long 0xB17219E9 // Fixed. can't change.
626 .long dcd_end - dcd_start
628 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x80000000)
629 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
630 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
631 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
632 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00338018)
633 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, ESDCTL_VAL)
634 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, ESDCFG_VAL)
635 #ifdef RAM_BANK1_SIZE
636 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, ESDCTL_VAL)
637 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, ESDCFG_VAL)
639 DCDGEN(4, ESDCTL_BASE_ADDR + 0x34, 0x00020000 | ((RALAT & 0x3) << 29))
640 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, ESDMISC_VAL)
641 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
644 .long REDBOOT_IMAGE_SIZE
647 SRC_BASE_ADDR_W: .long SRC_BASE_ADDR
648 WDOG_BASE_ADDR_W: .long WDOG_BASE_ADDR
649 AIPS1_PARAM: .word 0x77777777
650 M4IF_FBPM0_VAL: .word 0x00000103
651 M4IF_M4IF4_VAL: .word 0x00230185
652 M4IF_FPWC_VAL: .word 0x00240126
653 MXC_REDBOOT_ROM_START: .long SDRAM_BASE_ADDR + SDRAM_SIZE - REDBOOT_OFFSET
654 CCM_CBCDR_VAL1: .word 0x19239145
655 CCM_CBCDR_VAL2: .word 0x13239145
656 #if (CPU_CLK % SDRAM_CLK == 0)
657 CCM_CBCDR_VAL3: .word (((CPU_CLK + SDRAM_CLK - 1) / SDRAM_CLK - 1) << 27) | (1 << 30) | 0x01e35100
659 CCM_CBCDR_VAL3: .word 0x01e35100
665 CCM_CBCDR_VAL3: .word 0x59E35100
667 CCM_CBCDR_VAL3: .word 0x51E35100
671 #elif SDRAM_CLK == 166
673 CCM_CBCDR_VAL3: .word 0x01E35100
675 CCM_CBCDR_VAL3: .word 0x01E35100
684 CCM_CBCMR_VAL1: .word 0x000010C0
685 CCM_CBCMR_VAL2: .word 0x000020C0
686 CCM_CSCMR1_VAL: .word 0xA5A2A020
687 CCM_CSCDR1_VAL: .word 0x00C30321
688 BASE_ADDR_PLL1: .long PLL1_BASE_ADDR
689 BASE_ADDR_PLL2: .long PLL2_BASE_ADDR
690 BASE_ADDR_PLL3: .long PLL3_BASE_ADDR
691 W_DP_OP_800: .word DP_OP_800
692 W_DP_MFD_800: .word DP_MFD_800
693 W_DP_MFN_800: .word DP_MFN_800
694 W_DP_OP_700: .word DP_OP_700
695 W_DP_MFD_700: .word DP_MFD_700
696 W_DP_MFN_700: .word DP_MFN_700
697 W_DP_OP_600: .word DP_OP_600
698 W_DP_MFD_600: .word DP_MFD_600
699 W_DP_MFN_600: .word DP_MFN_600
700 W_DP_OP_400: .word DP_OP_400
701 W_DP_MFD_400: .word DP_MFD_400
702 W_DP_MFN_400: .word DP_MFN_400
703 W_DP_OP_532: .word DP_OP_532
704 W_DP_MFD_532: .word DP_MFD_532
705 W_DP_MFN_532: .word DP_MFN_532
706 W_DP_OP_665: .word DP_OP_665
707 W_DP_MFD_665: .word DP_MFD_665
708 W_DP_MFN_665: .word DP_MFN_665
709 W_DP_OP_216: .word DP_OP_216
710 W_DP_MFD_216: .word DP_MFD_216
711 W_DP_MFN_216: .word DP_MFN_216
712 PLATFORM_CLOCK_DIV: .word 0x00000124
714 /*----------------------------------------------------------------------*/
715 /* end of hal_platform_setup.h */
716 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */