1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 //=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
18 // Software Foundation; either version 2 or (at your option) any later version.
20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 // You should have received a copy of the GNU General Public License along
26 // with eCos; if not, write to the Free Software Foundation, Inc.,
27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
31 // with other works to produce a work based on this file, this file does not
32 // by itself cause the resulting work to be covered by the GNU General Public
33 // License. However the source code for this file must still be made available
34 // in accordance with section (3) of the GNU General Public License.
36 // This exception does not invalidate any other reasons why a work based on
37 // this file might be covered by the GNU General Public License.
39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //===========================================================================
45 #include <pkgconf/system.h> // System-wide configuration info
46 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
47 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
48 #include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
49 #include <cyg/hal/hal_mmu.h> // MMU definitions
50 #include CYGBLD_HAL_PLF_DEFS_H // Platform specific hardware definitions
51 #include CYGHWR_MEMORY_LAYOUT_H
53 #define CPU_CLK CYGNUM_HAL_ARM_TX53_CPU_CLK
57 #define DEBUG_LED_BIT 20
58 #define LED_GPIO_BASE GPIO2_BASE_ADDR
59 #define LED_MUX_OFFSET 0x174
60 #define LED_MUX_MODE 0x11
62 #ifdef CYGOPT_HAL_ARM_TX53_DEBUG
63 #define LED_ON bl led_on
64 #define LED_OFF bl led_off
70 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
71 #define PLATFORM_SETUP1 _platform_setup1
72 #define CYGHWR_HAL_ARM_HAS_MMU
74 #ifdef CYG_HAL_STARTUP_ROMRAM
75 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
78 #define TX53_NAND_PAGE_SIZE 2048
79 #define TX53_NAND_BLKS_PER_PAGE 64
81 #define PLATFORM_PREAMBLE flash_header
83 // This macro represents the initial startup code for the platform
84 .macro _platform_setup1
85 KARO_TX53_SETUP_START:
94 mov r0, #0 @ set up for MCR
95 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
96 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
99 * disable MMU stuff and caches
101 mrc p15, 0, r0, c1, c0, 0
102 bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
103 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
104 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
105 orr r0, r0, #0x00000800 @ set bit 12 (Z---) BTB
106 mcr p15, 0, r0, c1, c0, 0
108 /* ARM errata ID #468414 */
109 mrc 15, 0, r1, c1, c0, 1
110 orr r1, r1, #(1 << 5) /* enable L1NEON bit */
111 mcr 15, 0, r1, c1, c0, 1
113 // Explicitly disable L2 cache
114 mrc 15, 0, r0, c1, c0, 1
116 mcr 15, 0, r0, c1, c0, 1
118 // reconfigure L2 cache aux control reg
119 mov r0, #0xC0 // tag RAM
120 add r0, r0, #0x4 // data RAM
121 orr r0, r0, #(1 << 24) // disable write allocate delay
122 orr r0, r0, #(1 << 23) // disable write allocate combine
123 orr r0, r0, #(1 << 22) // disable write allocate
125 mcr 15, 1, r0, c9, c0, 2
129 /* switch off LCD backlight */
130 ldr r10, =GPIO1_BASE_ADDR
132 ldr r9, [r10, #GPIO_DR]
133 orr r9, r9, #(1 << 1)
134 str r9, [r10, #GPIO_DR]
136 ldr r9, [r10, #GPIO_GDIR]
137 orr r9, r9, #(1 << 1)
138 str r9, [r10, #GPIO_GDIR]
147 Normal_Boot_Continue:
150 * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity
153 @ Set up a stack [for calling C code]
154 ldr r1, =__startup_stack
155 ldr r2, =RAM_BANK0_BASE
162 /* Workaround for arm erratum #709718 */
163 @ Setup PRRR so device is always mapped to non-shared
164 mrc MMU_CP, 0, r1, c10, c2, 0 // Read Primary Region Remap Register
166 mcr MMU_CP, 0, r1, c10, c2, 0 // Write Primary Region Remap Register
170 mrc MMU_CP, 0, r1, MMU_Control, c0
171 orr r1, r1, #7 @ enable MMU bit
172 orr r1, r1, #0x800 @ enable z bit
173 orr r1, r1, #(1 << 28) @ Enable TEX remap, workaround for L1 cache issue
174 mcr MMU_CP, 0, r1, MMU_Control, c0
176 /* Workaround for arm errata #621766 */
177 mrc MMU_CP, 0, r1, MMU_Control, c0, 1
178 orr r1, r1, #(1 << 5) @ enable L1NEON bit
179 mcr MMU_CP, 0, r1, MMU_Control, c0, 1
181 mov pc, r2 @ Change address spaces
185 .endm @ _platform_setup1
187 /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
190 * Set all MPROTx to be non-bufferable, trusted for R/W,
191 * not forced to user-mode.
193 ldr r0, =AIPS1_CTRL_BASE_ADDR
197 ldr r0, =AIPS2_CTRL_BASE_ADDR
200 .endm /* init_aips */
203 ldr r0, =CCM_BASE_ADDR
204 ldr r1, [r0, #CLKCTL_CCR]
208 orr r1, r1, #(1 << 12)
209 str r1, [r0, #CLKCTL_CCR]
211 /* Switch ARM to step clock */
213 str r1, [r0, #CLKCTL_CCSR]
216 setup_pll PLL1_BASE_ADDR, 1000
218 setup_pll PLL1_BASE_ADDR, 800
222 setup_pll PLL3_BASE_ADDR, 400
224 /* Switch peripherals to PLL3 */
225 ldr r1, [r0, #CLKCTL_CBCMR]
228 str r1, [r0, #CLKCTL_CBCMR]
230 ldr r1, [r0, #CLKCTL_CBCDR]
231 orr r1, r1, #(1 << 25)
232 str r1, [r0, #CLKCTL_CBCDR]
234 /* make sure change is effective */
235 ldr r1, [r0, #CLKCTL_CDHIPR]
241 setup_pll PLL2_BASE_ADDR, 400
242 #elif SDRAM_CLK == 333
243 setup_pll PLL2_BASE_ADDR, 333
244 #elif SDRAM_CLK == 266
245 setup_pll PLL2_BASE_ADDR, 266
246 #elif SDRAM_CLK == 216
247 setup_pll PLL2_BASE_ADDR, 216
248 #elif SDRAM_CLK == 666
249 setup_pll PLL2_BASE_ADDR, 666
253 /* Switch peripheral to PLL2 */
254 ldr r1, [r0, #CLKCTL_CBCDR]
256 str r1, [r0, #CLKCTL_CBCDR]
258 ldr r1, [r0, #CLKCTL_CBCMR]
261 str r1, [r0, #CLKCTL_CBCMR]
263 /* make sure change is effective */
265 ldr r1, [r0, #CLKCTL_CDHIPR]
270 setup_pll PLL3_BASE_ADDR, 216
272 /* Set the platform clock dividers */
273 ldr r2, =PLATFORM_BASE_ADDR
274 ldr r1, PLATFORM_CLOCK_DIV
275 str r1, [r2, #PLATFORM_ICGC]
278 str r1, [r0, #CLKCTL_CACRR] /* ARM podf */
280 /* Switch ARM back to PLL 1. */
282 str r1, [r0, #CLKCTL_CCSR]
286 str r1, [r0, #CLKCTL_CSCDR1]
288 str r1, [r0, #CLKCTL_CSCMR1]
291 str r1, [r0, #CLKCTL_CCDR]
293 /* for cko - for ARM div by 8 */
295 orr r1, r1, #0x00000F0
296 str r1, [r0, #CLKCTL_CCOSR]
300 .macro setup_pll pll, mhz
303 str r1, [r2, #PLL_DP_CTL] @ Set DPLL ON (set UPEN bit); BRMO=1
305 str r1, [r2, #PLL_DP_CONFIG] @ Enable auto-restart AREN bit
308 str r1, [r2, #PLL_DP_OP]
309 str r1, [r2, #PLL_DP_HFS_OP]
311 ldr r1, W_DP_MFD_\mhz
312 str r1, [r2, #PLL_DP_MFD]
313 str r1, [r2, #PLL_DP_HFS_MFD]
315 ldr r1, W_DP_MFN_\mhz
316 str r1, [r2, #PLL_DP_MFN]
317 str r1, [r2, #PLL_DP_HFS_MFN]
319 /* Now restart PLL */
321 str r1, [r2, #PLL_DP_CTL]
323 ldr r1, [r2, #PLL_DP_CTL]
327 #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
328 #define PLATFORM_SETUP1
330 #ifndef CYGOPT_HAL_ARM_TX53_DEBUG
336 #define CYGHWR_LED_MACRO LED_BLINK #\x
350 // initialize GPIO4_10 (PAD CSI2_D13) for LED on STK5
351 ldr r10, =LED_GPIO_BASE
353 ldr r9, [r10, #GPIO_DR]
354 bic r9, #(1 << DEBUG_LED_BIT) @ LED OFF
355 str r9, [r10, #GPIO_DR]
357 ldr r9, [r10, #GPIO_GDIR]
358 orr r9, r9, #(1 << DEBUG_LED_BIT)
359 str r9, [r10, #GPIO_GDIR]
362 #ifdef CYGOPT_HAL_ARM_TX53_DEBUG
364 ldr r10, =LED_GPIO_BASE
366 ldr r9, [r10, #GPIO_DR]
367 orr r9, #(1 << DEBUG_LED_BIT) @ LED ON
368 str r9, [r10, #GPIO_DR]
372 ldr r10, =LED_GPIO_BASE
374 ldr r9, [r10, #GPIO_DR]
375 bic r9, #(1 << DEBUG_LED_BIT) @ LED OFF
376 str r9, [r10, #GPIO_DR]
383 ldr r9, =(36000 / 10 / 10)
405 #define PLATFORM_VECTORS _platform_vectors
406 .macro _platform_vectors
410 .globl _KARO_STRUCT_SIZE
412 .word 0 // reserve space structure length
414 .globl _KARO_CECFG_START
417 .word 0 // reserve space for CE configuration
420 .globl _KARO_CECFG_END
426 .ascii "KARO TX53 " __DATE__ " " __TIME__
429 #define CPU_2_BE_32(l) \
430 ((((l) << 24) & 0xFF000000) | \
431 (((l) << 8) & 0x00FF0000) | \
432 (((l) >> 8) & 0x0000FF00) | \
433 (((l) >> 24) & 0x000000FF))
435 #define MXC_DCD_ITEM(addr, val) \
436 .word CPU_2_BE_32(addr), CPU_2_BE_32(val)
438 #define MXC_DCD_CMD_SZ_BYTE 1
439 #define MXC_DCD_CMD_SZ_SHORT 2
440 #define MXC_DCD_CMD_SZ_WORD 4
441 #define MXC_DCD_CMD_FLAG_WRITE 0x0
442 #define MXC_DCD_CMD_FLAG_CLR 0x1
443 #define MXC_DCD_CMD_FLAG_SET 0x3
444 #define MXC_DCD_CMD_FLAG_CHK_ANY (1 << 0)
445 #define MXC_DCD_CMD_FLAG_CHK_SET (1 << 1)
446 #define MXC_DCD_CMD_FLAG_CHK_CLR (0 << 1)
448 #define MXC_DCD_CMD_WRT(type, flags, next) \
449 .word CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type))
451 #define MXC_DCD_CMD_CHK(type, flags, addr, mask) \
452 .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\
453 CPU_2_BE_32(addr), CPU_2_BE_32(mask)
455 #define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \
456 .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\
457 CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
459 #define MXC_DCD_CMD_NOP() \
460 .word CPU_2_BE_32((0xc0 << 24) | (4 << 8))
462 #define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
463 #define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
465 .macro CK_VAL, name, clks, offs, max
469 .ifle \clks - \offs - \max
470 .set \name, \clks - \offs
475 .macro NS_VAL, name, ns, offs, max
479 CK_VAL \name, NS_TO_CK(\ns), \offs, \max
483 .macro CK_MAX, name, ck1, ck2, offs, max
485 CK_VAL \name, \ck1, \offs, \max
487 CK_VAL \name, \ck2, \offs, \max
491 #define ESDMISC_DDR_TYPE_DDR3 0
492 #define ESDMISC_DDR_TYPE_LPDDR2 1
493 #define ESDMISC_DDR_TYPE_DDR2 2
495 #define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d))
497 #define CKIL_FREQ_Hz 32768
498 #define ESDOR_CLK_PERIOD_ns (1000000000 / CKIL_FREQ_Hz / 2) /* base clock for ESDOR values */
501 #if SDRAM_SIZE > SZ_512M
502 #define BANK_ADDR_BITS 2
504 #define BANK_ADDR_BITS 1
506 #define SDRAM_BURST_LENGTH 8
509 #define ADDR_MIRROR 0
510 #define DDR_TYPE ESDMISC_DDR_TYPE_DDR3
512 /* 512/1024MiB SDRAM: NT5CB128M16P-CG */
514 NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */
515 CK_MAX tXS, tRFC + 1 + NS_TO_CK(10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
516 CK_MAX tXP, 3, NS_TO_CK(6), 1, 7 /* clks - 1 (0..7) */ /* max(6ns, 3*CK) */
517 CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */
518 NS_VAL tFAW, 45, 1, 31 /* clks - 1 (0..31) */
519 CK_VAL tCL, 9, 3, 8 /* clks - 3 (0..8) CAS Latency */
522 NS_VAL tRCD, 14, 1, 7 /* clks - 1 (0..7) */
523 NS_VAL tRP, 14, 1, 7 /* clks - 1 (0..7) */
524 NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */
525 NS_VAL tRAS, 36, 1, 31 /* clks - 1 (0..31) */
526 CK_VAL tRPA, 0, 0, 1 /* clks (0..1) */
527 NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
528 CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */
529 CK_VAL tCWL, 5, 2, 6 /* clks - 2 (0..6) */
532 CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */
533 CK_MAX tRTP, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
534 CK_MAX tWTR, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
535 CK_MAX tRRD, 4, NS_TO_CK(8), 1, 7 /* clks - 1 (0..7) */
538 CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
541 NS_VAL tAOFPD, 9, 1, 7 /* clks - 1 (0..7) */
542 NS_VAL tAONPD, 9, 1, 7 /* clks - 1 (0..7) */
543 CK_VAL tANPD, tCWL, 1, 15 /* clks - 1 (0..15) */
544 CK_VAL tAXPD, tCWL, 1, 15 /* clks - 1 (0..15) */
545 CK_VAL tODTLon tCWL - 1, 1, 7 /* clks - 1 (0..7) */
546 CK_VAL tODTLoff tCWL - 1, 1, 31 /* clks - 1 (0..31) */
548 #define tSDE_RST (DIV_ROUND_UP(200000, ESDOR_CLK_PERIOD_ns) + 1)
550 /* Add an extra (or two?) ESDOR_CLK_PERIOD_ns according to
551 * erroneous Erratum Engcm12377
553 #define tRST_CKE (DIV_ROUND_UP(500000 + 2 * ESDOR_CLK_PERIOD_ns, ESDOR_CLK_PERIOD_ns) + 1)
555 #define ROW_ADDR_BITS 14
556 #define COL_ADDR_BITS 10
559 .set mrs_val, (0x8080 | \
560 (3 << 4) /* MRS command */ | \
561 ((1 << 8) /* DLL Reset */ | \
562 ((tWR + 1 - 4) << 9) | \
563 (((tCL + 3) - 4) << 4)) << 16)
565 .set mrs_val, (0x8080 | \
566 (3 << 4) /* MRS command */ | \
567 ((1 << 8) /* DLL Reset */ | \
568 (((tWR + 1) / 2) << 9) | \
569 (((tCL + 3) - 4) << 4)) << 16)
571 #define ESDSCR_MRS_VAL(cs) (mrs_val | ((1 << (cs)) << 8))
573 #define ESDCFG0_VAL ( \
581 #define ESDCFG1_VAL ( \
591 #define ESDCFG2_VAL ( \
597 #define BL (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
598 #define ESDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
599 ((COL_ADDR_BITS - 9) << 20) | \
601 (1 << 16) | /* SDRAM bus width */ \
602 ((-1) << (32 - BANK_ADDR_BITS)))
604 #define ESDMISC_VAL ((1 << 12) | \
608 (ADDR_MIRROR << 19) | \
611 #define ESDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
613 #define ESDOTC_VAL ((tAOFPD << 27) | \
624 .word 0x20424346 /* "FCB " marker */
625 .word 0x01 /* FCB version number */
627 .word 0x0 /* primary image starting page number */
628 .word 0x0 /* secondary image starting page number */
631 .word 0x0 /* DBBT start page (0 == NO DBBT) */
632 .word 0 /* Bad block marker offset in main area (unused) */
634 .word 0 /* BI Swap disabled */
635 .word 0 /* Bad Block marker offset in spare area */
640 .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
656 .long REDBOOT_IMAGE_SIZE
660 #define DCD_VERSION 0x40
663 .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION)
665 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib)
666 /* disable all irrelevant clocks */
667 MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR0, 0xffcc0fff)
668 MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR1, 0x000fffc3)
669 MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR2, 0x033c0000)
670 MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR3, 0x00000000)
671 MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR4, 0x00000000)
672 MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR5, 0x00fff033)
673 MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR6, 0x0f00030f)
674 MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR7, 0xfff00000)
675 MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CMEOR, 0x00000000)
677 MXC_DCD_ITEM(IOMUXC_BASE_ADDR + LED_MUX_OFFSET, LED_MUX_MODE) /* EIM_D18 => GPIO2[20] STK5-LED */
678 MXC_DCD_ITEM(IOMUXC_BASE_ADDR + 0x318, 0x11) /* GPIO_1 => LCD Backlight */
680 MXC_DCD_ITEM(0x63fd800c, 0x00000000) /* M4IF: MUX NFC signals on WEIM */
682 MXC_DCD_ITEM(0x53fd4014, 0x00888944) /* CBCDR */
684 MXC_DCD_ITEM(0x53fd4014, 0x00888644) /* CBCDR */
686 MXC_DCD_ITEM(0x53fd4018, 0x00016154) /* CBCMR */
688 #define DDR_SEL_VAL 2
692 #define DDR_SEL_SHIFT 25
695 #define DDR_INPUT_SHIFT 9
701 #define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT)
702 #define DSE_MASK (DSE_VAL << DSE_SHIFT)
703 #define ODT_MASK (ODT_VAL << ODT_SHIFT)
705 #define DQM_VAL DSE_MASK
706 #define SDQS_VAL (ODT_MASK | DSE_MASK | (1 << PUE_SHIFT))
707 #define SDODT_VAL (DSE_MASK | (0 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
708 #define SDCLK_VAL DSE_MASK
709 #define SDCKE_VAL ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
711 MXC_DCD_ITEM(0x53fa8724, DDR_SEL_MASK) /* DDR_TYPE: DDR3 */
712 MXC_DCD_ITEM(0x53fa86f4, 0 << DDR_INPUT_SHIFT) /* DDRMODE_CTL */
713 MXC_DCD_ITEM(0x53fa8714, 0 << DDR_INPUT_SHIFT) /* GRP_DDRMODE */
714 MXC_DCD_ITEM(0x53fa86fc, 1 << PKE_SHIFT) /* GRP_DDRPKE */
715 MXC_DCD_ITEM(0x53fa8710, 0 << HYS_SHIFT) /* GRP_DDRHYS */
716 MXC_DCD_ITEM(0x53fa8708, 1 << PUE_SHIFT) /* GRP_DDRPK */
718 MXC_DCD_ITEM(0x53fa8584, DQM_VAL) /* DQM0 */
719 MXC_DCD_ITEM(0x53fa8594, DQM_VAL) /* DQM1 */
720 MXC_DCD_ITEM(0x53fa8560, DQM_VAL) /* DQM2 */
721 MXC_DCD_ITEM(0x53fa8554, DQM_VAL) /* DQM3 */
723 MXC_DCD_ITEM(0x53fa857c, SDQS_VAL) /* SDQS0 */
724 MXC_DCD_ITEM(0x53fa8590, SDQS_VAL) /* SDQS1 */
725 MXC_DCD_ITEM(0x53fa8568, SDQS_VAL) /* SDQS2 */
726 MXC_DCD_ITEM(0x53fa8558, SDQS_VAL) /* SDQS3 */
728 MXC_DCD_ITEM(0x53fa8580, SDODT_VAL) /* SDODT0 */
729 MXC_DCD_ITEM(0x53fa8578, SDCLK_VAL) /* SDCLK0 */
731 MXC_DCD_ITEM(0x53fa8564, SDODT_VAL) /* SDODT1 */
732 MXC_DCD_ITEM(0x53fa8570, SDCLK_VAL) /* SDCLK1 */
734 MXC_DCD_ITEM(0x53fa858c, SDCKE_VAL) /* SDCKE0 */
735 MXC_DCD_ITEM(0x53fa855c, SDCKE_VAL) /* SDCKE1 */
737 MXC_DCD_ITEM(0x53fa8574, DSE_MASK) /* DRAM_CAS */
738 MXC_DCD_ITEM(0x53fa8588, DSE_MASK) /* DRAM_RAS */
740 MXC_DCD_ITEM(0x53fa86f0, DSE_MASK) /* GRP_ADDDS */
741 MXC_DCD_ITEM(0x53fa8720, DSE_MASK) /* GRP_CTLDS */
742 MXC_DCD_ITEM(0x53fa8718, DSE_MASK) /* GRP_B0DS */
743 MXC_DCD_ITEM(0x53fa871c, DSE_MASK) /* GRP_B1DS */
744 MXC_DCD_ITEM(0x53fa8728, DSE_MASK) /* GRP_B2DS */
745 MXC_DCD_ITEM(0x53fa872c, DSE_MASK) /* GRP_B3DS */
747 /* calibration defaults */
748 MXC_DCD_ITEM(0x63fd904c, 0x001f001f)
749 MXC_DCD_ITEM(0x63fd9050, 0x001f001f)
750 MXC_DCD_ITEM(0x63fd907c, 0x011e011e)
751 MXC_DCD_ITEM(0x63fd9080, 0x011f0120)
752 MXC_DCD_ITEM(0x63fd9088, 0x3a393d3b)
753 MXC_DCD_ITEM(0x63fd9090, 0x3f3f3f3f)
755 MXC_DCD_ITEM(0x63fd9018, ESDMISC_VAL)
756 MXC_DCD_ITEM(0x63fd9000, ESDCTL_VAL)
757 MXC_DCD_ITEM(0x63fd900c, ESDCFG0_VAL)
758 MXC_DCD_ITEM(0x63fd9010, ESDCFG1_VAL)
759 MXC_DCD_ITEM(0x63fd9014, ESDCFG2_VAL)
761 MXC_DCD_ITEM(0x63fd902c, 0x000026d2)
762 MXC_DCD_ITEM(0x63fd9030, ESDOR_VAL)
763 MXC_DCD_ITEM(0x63fd9008, ESDOTC_VAL)
764 MXC_DCD_ITEM(0x63fd9004, 0x00030012)
767 MXC_DCD_ITEM(0x63fd901c, 0x00008032) /* MRS: MR2 */
768 MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: MR3 */
769 MXC_DCD_ITEM(0x63fd901c, 0x00408031) /* MRS: MR1 */
770 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0)) /* MRS: MR0 */
772 #if BANK_ADDR_BITS > 1
773 MXC_DCD_ITEM(0x63fd901c, 0x0000803a) /* MRS: MR2 */
774 MXC_DCD_ITEM(0x63fd901c, 0x0000803b) /* MRS: MR3 */
775 MXC_DCD_ITEM(0x63fd901c, 0x00408039) /* MRS: MR1 */
776 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1)) /* MRS: MR0 */
778 MXC_DCD_ITEM(0x63fd9020, 0x00005800) /* refresh interval */
779 MXC_DCD_ITEM(0x63fd9058, 0x00011112)
781 MXC_DCD_ITEM(0x63fd90d0, 0x00000003) /* select default compare pattern for calibration */
784 MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
785 MXC_DCD_ITEM(0x63fd901c, 0x00008040) /* MRS: ZQ calibration */
786 MXC_DCD_ITEM(0x63fd9040, 0x0539002b) /* Force ZQ calibration */
788 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd9040, 0x00010000)
789 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib)
792 MXC_DCD_ITEM(0x63fd901c, 0x00048033) /* MRS: select MPR */
793 MXC_DCD_ITEM(0x63fd901c, 0x00848231) /* MRS: start write leveling */
794 MXC_DCD_ITEM(0x63fd901c, 0x00000000)
795 MXC_DCD_ITEM(0x63fd9048, 0x00000001)
797 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd9048, 0x00000001)
798 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib)
799 MXC_DCD_ITEM(0x63fd901c, 0x00048031) /* MRS: end write leveling */
800 MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: select normal data path */
802 /* DQS calibration */
803 MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
804 MXC_DCD_ITEM(0x63fd901c, 0x00048033) /* MRS: select MPR */
805 MXC_DCD_ITEM(0x63fd907c, 0x90000000) /* reset RD fifo and start DQS calib. */
807 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd907c, 0x90000000)
808 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib)
809 MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: select normal data path */
811 /* WR DL calibration */
812 MXC_DCD_ITEM(0x63fd901c, 0x00000000)
813 MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
814 MXC_DCD_ITEM(0x63fd901c, 0x00048033) /* MRS: select MPR */
815 MXC_DCD_ITEM(0x63fd90a4, 0x00000010)
816 wr_dl_calib: /* 6c4 */
817 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd90a4, 0x00000010)
818 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib)
819 MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: select normal data path */
821 /* RD DL calibration */
822 MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
823 MXC_DCD_ITEM(0x63fd901c, 0x00048033) /* MRS: select MPR */
824 MXC_DCD_ITEM(0x63fd90a0, 0x00000010)
825 rd_dl_calib: /* 70c */
826 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd90a0, 0x00000010)
827 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dcd_end)
828 MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: select normal data path */
830 MXC_DCD_ITEM(0x63fd901c, 0x00000000)
832 MXC_DCD_ITEM(0x53fa8004, 0x00194005) @ set LDO to 1.3V
836 MXC_DCD_ITEM(0x53fa819c, 0x00000000) @ EIM_DA0
837 MXC_DCD_ITEM(0x53fa81a0, 0x00000000) @ EIM_DA1
838 MXC_DCD_ITEM(0x53fa81a4, 0x00000000) @ EIM_DA2
839 MXC_DCD_ITEM(0x53fa81a8, 0x00000000) @ EIM_DA3
840 MXC_DCD_ITEM(0x53fa81ac, 0x00000000) @ EIM_DA4
841 MXC_DCD_ITEM(0x53fa81b0, 0x00000000) @ EIM_DA5
842 MXC_DCD_ITEM(0x53fa81b4, 0x00000000) @ EIM_DA6
843 MXC_DCD_ITEM(0x53fa81b8, 0x00000000) @ EIM_DA7
844 MXC_DCD_ITEM(0x53fa81dc, 0x00000000) @ WE_B
845 MXC_DCD_ITEM(0x53fa81e0, 0x00000000) @ RE_B
846 MXC_DCD_ITEM(0x53fa8228, 0x00000000) @ CLE
847 MXC_DCD_ITEM(0x53fa822c, 0x00000000) @ ALE
848 MXC_DCD_ITEM(0x53fa8230, 0x00000000) @ WP_B
849 MXC_DCD_ITEM(0x53fa8234, 0x00000000) @ RB0
850 MXC_DCD_ITEM(0x53fa8238, 0x00000000) @ CS0
852 MXC_DCD_ITEM(0x53fa84ec, 0x000000e4) @ EIM_DA0
853 MXC_DCD_ITEM(0x53fa84f0, 0x000000e4) @ EIM_DA1
854 MXC_DCD_ITEM(0x53fa84f4, 0x000000e4) @ EIM_DA2
855 MXC_DCD_ITEM(0x53fa84f8, 0x000000e4) @ EIM_DA3
856 MXC_DCD_ITEM(0x53fa84fc, 0x000000e4) @ EIM_DA4
857 MXC_DCD_ITEM(0x53fa8500, 0x000000e4) @ EIM_DA5
858 MXC_DCD_ITEM(0x53fa8504, 0x000000e4) @ EIM_DA6
859 MXC_DCD_ITEM(0x53fa8508, 0x000000e4) @ EIM_DA7
860 MXC_DCD_ITEM(0x53fa852c, 0x00000004) @ NANDF_WE_B
861 MXC_DCD_ITEM(0x53fa8530, 0x00000004) @ NANDF_RE_B
862 MXC_DCD_ITEM(0x53fa85a0, 0x00000004) @ NANDF_CLE_B
863 MXC_DCD_ITEM(0x53fa85a4, 0x00000004) @ NANDF_ALE_B
864 MXC_DCD_ITEM(0x53fa85a8, 0x000000e4) @ NANDF_WE_B
865 MXC_DCD_ITEM(0x53fa85ac, 0x000000e4) @ NANDF_RB0
866 MXC_DCD_ITEM(0x53fa85b0, 0x00000004) @ NANDF_CS0
868 .ifgt dcd_end - dcd_start - 1768
873 MXC_REDBOOT_ROM_START: .long SDRAM_BASE_ADDR + SDRAM_SIZE - REDBOOT_OFFSET
876 CCM_CBCDR_VAL1: .word 0x02888944
877 CCM_CBCDR_VAL2: .word 0x00888944
879 CCM_CBCDR_VAL1: .word 0x02888644
880 CCM_CBCDR_VAL2: .word 0x00888644
883 W_CSCMR1_VAL: .word 0xa6a2a020
884 W_CSCDR1_VAL: .word 0x00080b18
885 W_DP_OP_1000: .word DP_OP_1000
886 W_DP_MFD_1000: .word DP_MFD_1000
887 W_DP_MFN_1000: .word DP_MFN_1000
888 W_DP_OP_800: .word DP_OP_800
889 W_DP_MFD_800: .word DP_MFD_800
890 W_DP_MFN_800: .word DP_MFN_800
891 W_DP_OP_700: .word DP_OP_700
892 W_DP_MFD_700: .word DP_MFD_700
893 W_DP_MFN_700: .word DP_MFN_700
894 W_DP_OP_400: .word DP_OP_400
895 W_DP_MFD_400: .word DP_MFD_400
896 W_DP_MFN_400: .word DP_MFN_400
897 W_DP_OP_532: .word DP_OP_532
898 W_DP_MFD_532: .word DP_MFD_532
899 W_DP_MFN_532: .word DP_MFN_532
900 W_DP_OP_666: .word DP_OP_666
901 W_DP_MFD_666: .word DP_MFD_666
902 W_DP_MFN_666: .word DP_MFN_666
903 W_DP_OP_665: .word DP_OP_665
904 W_DP_MFD_665: .word DP_MFD_665
905 W_DP_MFN_665: .word DP_MFN_665
906 W_DP_OP_216: .word DP_OP_216
907 W_DP_MFD_216: .word DP_MFD_216
908 W_DP_MFN_216: .word DP_MFN_216
909 W_DP_OP_333: .word DP_OP_333
910 W_DP_MFD_333: .word DP_MFD_333
911 W_DP_MFN_333: .word DP_MFN_333
912 W_DP_OP_266: .word DP_OP_266
913 W_DP_MFD_266: .word DP_MFD_266
914 W_DP_MFN_266: .word DP_MFN_266
915 PLATFORM_CLOCK_DIV: .word 0x00000124
917 /*----------------------------------------------------------------------*/
918 /* end of hal_platform_setup.h */
919 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */