1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 //=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
31 // with other works to produce a work based on this file, this file does not
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33 // License. However the source code for this file must still be made available
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40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //===========================================================================
45 #include <pkgconf/system.h> // System-wide configuration info
46 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
47 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
48 #include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
49 #include <cyg/hal/hal_mmu.h> // MMU definitions
50 #include CYGBLD_HAL_PLF_DEFS_H // Platform specific hardware definitions
51 #include CYGHWR_MEMORY_LAYOUT_H
53 #define CPU_CLK CYGNUM_HAL_ARM_TX53_CPU_CLK
57 #define DEBUG_LED_BIT 20
58 #define LED_GPIO_BASE GPIO2_BASE_ADDR
59 #define LED_MUX_OFFSET 0x174
60 #define LED_MUX_MODE 0x11
62 #ifdef CYGOPT_HAL_ARM_TX53_DEBUG
63 #define LED_ON bl led_on
64 #define LED_OFF bl led_off
70 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
71 #define PLATFORM_SETUP1 _platform_setup1
72 #define CYGHWR_HAL_ARM_HAS_MMU
74 #ifdef CYG_HAL_STARTUP_ROMRAM
75 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
78 #define TX53_NAND_PAGE_SIZE 2048
79 #define TX53_NAND_BLKS_PER_PAGE 64
81 #define PLATFORM_PREAMBLE flash_header
84 #define REDBOOT_RAM_START (RAM_BANK1_BASE + RAM_BANK1_SIZE - REDBOOT_OFFSET)
86 #define REDBOOT_RAM_START (RAM_BANK0_BASE + RAM_BANK0_SIZE - REDBOOT_OFFSET)
89 #define redboot_v2p(v) ((v) - __text_start + REDBOOT_RAM_START)
91 // This macro represents the initial startup code for the platform
92 .macro _platform_setup1
93 KARO_TX53_SETUP_START:
102 mov r0, #0 @ set up for MCR
103 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
104 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
107 * disable MMU stuff and caches
109 mrc p15, 0, r0, c1, c0, 0
110 bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
111 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
112 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
113 orr r0, r0, #0x00000800 @ set bit 12 (Z---) BTB
114 mcr p15, 0, r0, c1, c0, 0
116 /* ARM errata ID #468414 */
117 mrc 15, 0, r1, c1, c0, 1
118 orr r1, r1, #(1 << 5) /* enable L1NEON bit */
119 mcr 15, 0, r1, c1, c0, 1
121 // Explicitly disable L2 cache
122 mrc 15, 0, r0, c1, c0, 1
124 mcr 15, 0, r0, c1, c0, 1
126 // reconfigure L2 cache aux control reg
127 mov r0, #0xC0 // tag RAM
128 add r0, r0, #0x4 // data RAM
129 orr r0, r0, #(1 << 24) // disable write allocate delay
130 orr r0, r0, #(1 << 23) // disable write allocate combine
131 orr r0, r0, #(1 << 22) // disable write allocate
133 mcr 15, 1, r0, c9, c0, 2
137 /* switch off LCD backlight */
138 ldr r10, =GPIO1_BASE_ADDR
140 ldr r9, [r10, #GPIO_DR]
141 orr r9, r9, #(1 << 1)
142 str r9, [r10, #GPIO_DR]
144 ldr r9, [r10, #GPIO_GDIR]
145 orr r9, r9, #(1 << 1)
146 str r9, [r10, #GPIO_GDIR]
156 * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity
159 @ Set up a stack [for calling C code]
160 /* stack is always in the first memory bank, so there is no
161 * need to fixup the address
163 ldr sp, .__startup_stack
171 /* Workaround for arm erratum #709718 */
172 @ Setup PRRR so device is always mapped to non-shared
173 mrc MMU_CP, 0, r1, c10, c2, 0 // Read Primary Region Remap Register
175 mcr MMU_CP, 0, r1, c10, c2, 0 // Write Primary Region Remap Register
179 #ifdef RAM_BANK1_SIZE
180 ldr r1, =(__text_start - REDBOOT_RAM_START)
183 mrc MMU_CP, 0, r1, MMU_Control, c0
184 orr r1, r1, #7 @ enable MMU bit
185 orr r1, r1, #0x800 @ enable z bit
186 orr r1, r1, #(1 << 28) @ Enable TEX remap, workaround for L1 cache issue
187 mcr MMU_CP, 0, r1, MMU_Control, c0
189 /* Workaround for arm errata #621766 */
190 mrc MMU_CP, 0, r1, MMU_Control, c0, 1
191 orr r1, r1, #(1 << 5) @ enable L1NEON bit
192 mcr MMU_CP, 0, r1, MMU_Control, c0, 1
194 mov pc, r2 @ Change address spaces
199 .endm @ _platform_setup1
201 /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
204 * Set all MPROTx to be non-bufferable, trusted for R/W,
205 * not forced to user-mode.
207 ldr r0, =AIPS1_CTRL_BASE_ADDR
211 ldr r0, =AIPS2_CTRL_BASE_ADDR
214 .endm /* init_aips */
217 ldr r0, =CCM_BASE_ADDR
218 ldr r1, [r0, #CLKCTL_CCR]
222 orr r1, r1, #(1 << 12)
223 str r1, [r0, #CLKCTL_CCR]
225 /* Switch ARM to step clock */
227 str r1, [r0, #CLKCTL_CCSR]
230 setup_pll PLL1_BASE_ADDR, 1000
232 setup_pll PLL1_BASE_ADDR, 800
236 setup_pll PLL3_BASE_ADDR, 400
238 /* Switch peripherals to PLL3 */
239 ldr r1, [r0, #CLKCTL_CBCMR]
242 str r1, [r0, #CLKCTL_CBCMR]
244 ldr r1, [r0, #CLKCTL_CBCDR]
245 orr r1, r1, #(1 << 25)
246 str r1, [r0, #CLKCTL_CBCDR]
248 /* make sure change is effective */
249 ldr r1, [r0, #CLKCTL_CDHIPR]
254 setup_pll PLL2_BASE_ADDR, 400
255 #elif SDRAM_CLK == 333
256 setup_pll PLL2_BASE_ADDR, 333
257 #elif SDRAM_CLK == 266
258 setup_pll PLL2_BASE_ADDR, 266
259 #elif SDRAM_CLK == 216
260 setup_pll PLL2_BASE_ADDR, 216
261 #elif SDRAM_CLK == 666
262 setup_pll PLL2_BASE_ADDR, 666
266 /* Switch peripheral to PLL2 */
267 ldr r1, [r0, #CLKCTL_CBCDR]
269 str r1, [r0, #CLKCTL_CBCDR]
271 ldr r1, [r0, #CLKCTL_CBCMR]
274 str r1, [r0, #CLKCTL_CBCMR]
276 /* make sure change is effective */
278 ldr r1, [r0, #CLKCTL_CDHIPR]
282 setup_pll PLL3_BASE_ADDR, 216
284 /* Set the platform clock dividers */
285 ldr r2, =PLATFORM_BASE_ADDR
286 ldr r1, PLATFORM_CLOCK_DIV
287 str r1, [r2, #PLATFORM_ICGC]
290 str r1, [r0, #CLKCTL_CACRR] /* ARM podf */
292 /* Switch ARM back to PLL 1. */
294 str r1, [r0, #CLKCTL_CCSR]
298 str r1, [r0, #CLKCTL_CSCDR1]
300 str r1, [r0, #CLKCTL_CSCMR1]
303 str r1, [r0, #CLKCTL_CCDR]
305 /* for cko - for ARM div by 8 */
307 orr r1, r1, #0x00000F0
308 str r1, [r0, #CLKCTL_CCOSR]
312 .macro setup_pll pll, mhz
315 str r1, [r2, #PLL_DP_CTL] @ Set DPLL ON (set UPEN bit); BRMO=1
317 str r1, [r2, #PLL_DP_CONFIG] @ Enable auto-restart AREN bit
320 str r1, [r2, #PLL_DP_OP]
321 str r1, [r2, #PLL_DP_HFS_OP]
323 ldr r1, W_DP_MFD_\mhz
324 str r1, [r2, #PLL_DP_MFD]
325 str r1, [r2, #PLL_DP_HFS_MFD]
327 ldr r1, W_DP_MFN_\mhz
328 str r1, [r2, #PLL_DP_MFN]
329 str r1, [r2, #PLL_DP_HFS_MFN]
331 /* Now restart PLL */
333 str r1, [r2, #PLL_DP_CTL]
335 ldr r1, [r2, #PLL_DP_CTL]
339 #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
340 #define PLATFORM_SETUP1
342 #ifndef CYGOPT_HAL_ARM_TX53_DEBUG
348 #define CYGHWR_LED_MACRO LED_BLINK #\x
362 // initialize GPIO4_10 (PAD CSI2_D13) for LED on STK5
363 ldr r10, =LED_GPIO_BASE
365 ldr r9, [r10, #GPIO_DR]
366 bic r9, #(1 << DEBUG_LED_BIT) @ LED OFF
367 str r9, [r10, #GPIO_DR]
369 ldr r9, [r10, #GPIO_GDIR]
370 orr r9, r9, #(1 << DEBUG_LED_BIT)
371 str r9, [r10, #GPIO_GDIR]
374 #ifdef CYGOPT_HAL_ARM_TX53_DEBUG
376 ldr r10, =LED_GPIO_BASE
378 ldr r9, [r10, #GPIO_DR]
379 orr r9, #(1 << DEBUG_LED_BIT) @ LED ON
380 str r9, [r10, #GPIO_DR]
384 ldr r10, =LED_GPIO_BASE
386 ldr r9, [r10, #GPIO_DR]
387 bic r9, #(1 << DEBUG_LED_BIT) @ LED OFF
388 str r9, [r10, #GPIO_DR]
395 ldr r9, =(36000 / 10)
417 #define PLATFORM_VECTORS _platform_vectors
418 .macro _platform_vectors
422 .globl _KARO_STRUCT_SIZE
424 .word 0 // reserve space structure length
426 .globl _KARO_CECFG_START
429 .word 0 // reserve space for CE configuration
432 .globl _KARO_CECFG_END
438 .ascii "KARO TX53 " __DATE__ " " __TIME__
441 #define CPU_2_BE_32(l) \
442 ((((l) << 24) & 0xFF000000) | \
443 (((l) << 8) & 0x00FF0000) | \
444 (((l) >> 8) & 0x0000FF00) | \
445 (((l) >> 24) & 0x000000FF))
448 CCM register set 0x53FD4000 0x53FD7FFF
449 EIM register set 0x63FDA000 0x63FDAFFF
450 NANDFC register set 0xF7FF0000 0xF7FFFFFF
451 IOMUX Control (IOMUXC) registers 0x53FA8000 0x53FABFFF
452 DPLLC1 register 0x63F80000 0x63F83FFF
453 DPLLC2 register 0x63F84000 0x63F87FFF
454 DPLLC3 register 0x63F88000 0x63F8BFFF
455 DPLLC4 register 0x63F8C000 0x63F8FFFF
456 ESD RAM controller register 0x63FD9000 0x63FD9FFF
457 M4IF register 0x63FD8000 0x63FD8FFF
458 DDR 0x70000000 0xEFFFFFFF
459 EIM 0xF0000000 0xF7FEFFFF
460 NANDFC Buffers 0xF7FF0000 0xF7FFFFFF
461 IRAM Free Space 0xF8006000 0xF8017FF0
462 GPU Memory 0xF8020000 0xF805FFFF
464 #define CHECK_DCD_ADDR(a) ( \
465 ((a) >= 0x53fd4000 && (a) <= 0x53fd7fff) /* CCM */ || \
466 ((a) >= 0x63fda000 && (a) <= 0x63fdafff) /* EIM (CS0) */ || \
467 ((a) >= 0x53fa8000 && (a) <= 0x53fabfff) /* IOMUXC */ || \
468 ((a) >= 0x63f80000 && (a) <= 0x63f8ffff) /* DPLLC1..4 */ || \
469 ((a) >= 0x63fd8000 && (a) <= 0x63fd9fff) /* M4IF & SDRAM Contr. */ || \
470 ((a) >= 0x70000000 && (a) <= 0xefffffff) /* SDRAM */ || \
471 ((a) >= 0xf0000000 && (a) <= 0xf7ffffff) /* EIM & NANDFC buffers */ || \
472 ((a) >= 0xf8006000 && (a) <= 0xf8017ff0) /* IRAM free space */ || \
473 ((a) >= 0xf8020000 && (a) <= 0xf805ffff) /* GPU RAM */)
475 .macro mxc_dcd_item addr, val
476 .ifne CHECK_DCD_ADDR(\addr)
477 .word CPU_2_BE_32(\addr), CPU_2_BE_32(\val)
479 .error "Address \addr not accessible from DCD"
483 #define MXC_DCD_ITEM(addr, val) mxc_dcd_item (addr), (val)
485 #define MXC_DCD_CMD_SZ_BYTE 1
486 #define MXC_DCD_CMD_SZ_SHORT 2
487 #define MXC_DCD_CMD_SZ_WORD 4
488 #define MXC_DCD_CMD_FLAG_WRITE 0x0
489 #define MXC_DCD_CMD_FLAG_CLR 0x1
490 #define MXC_DCD_CMD_FLAG_SET 0x3
491 #define MXC_DCD_CMD_FLAG_CHK_CLR ((0 << 0) | (0 << 1))
492 #define MXC_DCD_CMD_FLAG_CHK_SET ((0 << 0) | (1 << 1))
493 #define MXC_DCD_CMD_FLAG_CHK_ANY_CLR ((1 << 0) | (0 << 1))
494 #define MXC_DCD_CMD_FLAG_CHK_ANY_SET ((1 << 0) | (1 << 1))
496 #define MXC_DCD_START \
497 .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION) ; \
502 .ifgt . - dcd_start - 1768
503 .error "DCD too large!"
508 #define MXC_DCD_CMD_WRT(type, flags) \
509 1: .word CPU_2_BE_32((0xcc << 24) | ((1f - .) << 8) | ((flags) << 3) | (type))
511 #define MXC_DCD_CMD_CHK(type, flags, addr, mask) \
512 1: .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)), \
513 CPU_2_BE_32(addr), CPU_2_BE_32(mask)
515 #define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \
516 1: .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)), \
517 CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
519 #define MXC_DCD_CMD_NOP() \
520 1: .word CPU_2_BE_32((0xc0 << 24) | (4 << 8))
523 #define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
524 #define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
525 #define NS_TO_CK10(ns) DIV_ROUND_UP(NS_TO_CK(ns), 10)
527 .macro CK_VAL, name, clks, offs, max
531 .ifle \clks - \offs - \max
532 .set \name, \clks - \offs
534 .error "Value \clks out of range for parameter \name"
539 .macro NS_VAL, name, ns, offs, max
543 CK_VAL \name, NS_TO_CK(\ns), \offs, \max
547 .macro CK_MAX, name, ck1, ck2, offs, max
549 CK_VAL \name, \ck1, \offs, \max
551 CK_VAL \name, \ck2, \offs, \max
555 #define ESDMISC_DDR_TYPE_DDR3 0
556 #define ESDMISC_DDR_TYPE_LPDDR2 1
557 #define ESDMISC_DDR_TYPE_DDR2 2
559 #define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d))
561 #define CKIL_FREQ_Hz 32768
562 #define ESDOR_CLK_PERIOD_ns (1000000000 / CKIL_FREQ_Hz / 2) /* base clock for ESDOR values */
565 #if SDRAM_SIZE > RAM_BANK0_SIZE
566 #define BANK_ADDR_BITS 2
568 #define BANK_ADDR_BITS 1
570 #define SDRAM_BURST_LENGTH 8
574 #define ADDR_MIRROR 0
575 #define DDR_TYPE ESDMISC_DDR_TYPE_DDR3
577 /* 512/1024MiB SDRAM: NT5CB128M16FP-DII */
578 #if SDRAM_CLK > 666 && SDRAM_CLK <= 800
581 #elif SDRAM_CLK > 533 && SDRAM_CLK <= 666
582 #define CL_VAL 9 // or 10
584 #elif SDRAM_CLK > 400 && SDRAM_CLK <= 533
585 #define CL_VAL 7 // or 8
587 #elif SDRAM_CLK > 333 && SDRAM_CLK <= 400
590 #elif SDRAM_CLK >= 303 && SDRAM_CLK <= 333
594 #error SDRAM clock out of range: 303 .. 800
598 NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */
599 CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
600 CK_MAX tXP, NS_TO_CK10(75), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) */
601 CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */
602 NS_VAL tFAW, 50, 1, 31 /* clks - 1 (0..31) */
603 CK_VAL tCL, CL_VAL, 3, 8 /* clks - 3 (0..8) CAS Latency */
606 CK_VAL tRCD, NS_TO_CK10(125), 1, 7 /* clks - 1 (0..7) */ /* 12.5 */
607 CK_VAL tRP, NS_TO_CK10(125), 1, 7 /* clks - 1 (0..7) */ /* 12.5 */
608 NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */
609 CK_VAL tRAS, NS_TO_CK10(375), 1, 31 /* clks - 1 (0..31) */ /* 37.5 */
610 CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */
611 NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */
612 CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */
613 CK_VAL tCWL, CWL_VAL, 2, 6 /* clks - 2 (0..6) */
616 CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */
617 CK_MAX tRTP, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
618 CK_MAX tWTR, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
619 CK_MAX tRRD, NS_TO_CK(10), 4, 1, 7 /* clks - 1 (0..7) */
622 CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
623 #define tSDE_RST (DIV_ROUND_UP(200000, ESDOR_CLK_PERIOD_ns) + 1)
624 /* Add an extra (or two?) ESDOR_CLK_PERIOD_ns according to
625 * erroneous Erratum Engcm12377
627 #define tRST_CKE (DIV_ROUND_UP(500000 + 2 * ESDOR_CLK_PERIOD_ns, ESDOR_CLK_PERIOD_ns) + 1)
631 CK_VAL tAOFPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 8.5ns */
632 CK_VAL tAONPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 8.5ns */
633 CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
634 CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */
635 CK_VAL tODTLon tCWL, 0, 7 /* clks - 1 (0..7) */ /* CWL+AL-2 */
636 CK_VAL tODTLoff tCWL, 0, 31 /* clks - 1 (0..31) */ /* CWL+AL-2 */
639 CK_MAX tCKE, NS_TO_CK(5), 3, 1, 7
640 CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7
641 CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7
648 #define ESDPDC_VAL_0 ( \
653 (BOTH_CS_PD << 6) | \
658 #define ESDPDC_VAL_1 (ESDPDC_VAL_0 | \
663 #define ROW_ADDR_BITS 14
664 #define COL_ADDR_BITS 10
666 #define Rtt_Nom 1 /* ODT: 0: off 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */
667 #define Rtt_WR 0 /* Dynamic ODT: 0: off 1: RZQ/4 2: RZQ/2 */
668 #define DLL_DISABLE 0
671 .set mr0_val, (((1 - DLL_DISABLE) << 8) /* DLL Reset */ | \
672 (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
673 ((tWR + 1 - 4) << 9) | \
674 ((((tCL + 3) - 4) & 0x7) << 4) | \
675 ((((tCL + 3) - 4) & 0x8) >> 1))
677 .set mr0_val, ((1 << 8) /* DLL Reset */ | \
678 (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
679 (((tWR + 1) / 2) << 9) | \
680 ((((tCL + 3) - 4) & 0x7) << 4) | \
681 ((((tCL + 3) - 4) & 0x8) >> 1))
685 ((Rtt_Nom & 1) << 2) | \
686 (((Rtt_Nom >> 1) & 1) << 6) | \
687 (((Rtt_Nom >> 2) & 1) << 9) | \
688 (DLL_DISABLE << 0) | \
691 (Rtt_WR << 9) /* dynamic ODT */ | \
692 (0 << 7) /* SRT: Ext. temp. (mutually exclusive with ASR!) */ | \
693 (1 << 6) | /* ASR: Automatic Self Refresh */\
694 (((tCWL + 2) - 5) << 3) | \
698 #define ESDSCR_MRS_VAL(cs, mr, val) (((val) << 16) | \
699 (1 << 15) /* CON_REQ */ | \
701 (3 << 4) /* MRS command */ | \
706 #define ESDCFG0_VAL ( \
714 #define ESDCFG1_VAL ( \
724 #define ESDCFG2_VAL ( \
730 #define BL (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */
731 #define ESDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \
732 ((COL_ADDR_BITS - 9) << 20) | \
734 (1 << 16) | /* SDRAM bus width */ \
735 ((-1) << (32 - BANK_ADDR_BITS)))
737 #define ESDMISC_VAL ((1 << 12) | \
741 (ADDR_MIRROR << 19) | \
744 #define ESDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0))
746 #define ESDOTC_VAL ((tAOFPD << 27) | \
757 .word 0x20424346 /* "FCB " marker */
758 .word 0x01 /* FCB version number */
760 .word 0x0 /* primary image starting page number */
761 .word 0x0 /* secondary image starting page number */
764 .word 0x0 /* DBBT start page (0 == NO DBBT) */
765 .word 0 /* Bad block marker offset in main area (unused) */
767 .word 0 /* BI Swap disabled */
768 .word 0 /* Bad Block marker offset in spare area */
773 .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40)
775 .long redboot_v2p(reset_vector)
778 .long redboot_v2p(dcd_hdr)
780 .word redboot_v2p(boot_data)
782 .word redboot_v2p(ivt_header)
787 .long redboot_v2p(__text_start)
789 .long REDBOOT_IMAGE_SIZE
793 #define DCD_VERSION 0x40
797 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
799 MXC_DCD_ITEM(0x53fa8004, 0x00194005) @ set LDO to 1.3V
801 /* disable all irrelevant clocks */
802 MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR0, 0xffcc0fff)
803 MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR1, 0x000fffc3)
804 MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR2, 0x033c0000)
805 MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR3, 0x00000000)
806 MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR4, 0x00000000)
807 MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR5, 0x00fff033)
808 MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR6, 0x0f00030f)
809 MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR7, 0xfff00000)
810 MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CMEOR, 0x00000000)
812 MXC_DCD_ITEM(IOMUXC_BASE_ADDR + LED_MUX_OFFSET, LED_MUX_MODE) /* EIM_D18 => GPIO2[20] STK5-LED */
813 MXC_DCD_ITEM(IOMUXC_BASE_ADDR + 0x318, 0x11) /* GPIO_1 => LCD Backlight */
815 MXC_DCD_ITEM(0x63fd800c, 0x00000000) /* M4IF: MUX NFC signals on WEIM */
817 MXC_DCD_ITEM(0x53fd4014, 0x00888944) /* CBCDR */
819 MXC_DCD_ITEM(0x53fd4014, 0x00888644) /* CBCDR */
821 MXC_DCD_ITEM(0x53fd4018, 0x00016154) /* CBCMR */
823 #define DDR_SEL_VAL 2
827 #define DDR_SEL_SHIFT 25
830 #define DDR_INPUT_SHIFT 9
836 #define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT)
837 #define DSE_MASK (DSE_VAL << DSE_SHIFT)
838 #define ODT_MASK (ODT_VAL << ODT_SHIFT)
840 #define DQM_VAL DSE_MASK
841 #define SDQS_VAL (ODT_MASK | DSE_MASK | (1 << PUE_SHIFT))
842 #define SDODT_VAL (DSE_MASK | (0 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
843 #define SDCLK_VAL DSE_MASK
844 #define SDCKE_VAL ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT))
846 MXC_DCD_ITEM(0x53fa8724, DDR_SEL_MASK) /* DDR_TYPE: DDR3 */
847 MXC_DCD_ITEM(0x53fa86f4, 0 << DDR_INPUT_SHIFT) /* DDRMODE_CTL */
848 MXC_DCD_ITEM(0x53fa8714, 0 << DDR_INPUT_SHIFT) /* GRP_DDRMODE */
849 MXC_DCD_ITEM(0x53fa86fc, 1 << PKE_SHIFT) /* GRP_DDRPKE */
850 MXC_DCD_ITEM(0x53fa8710, 0 << HYS_SHIFT) /* GRP_DDRHYS */
851 MXC_DCD_ITEM(0x53fa8708, 1 << PUE_SHIFT) /* GRP_DDRPK */
853 MXC_DCD_ITEM(0x53fa8584, DQM_VAL) /* DQM0 */
854 MXC_DCD_ITEM(0x53fa8594, DQM_VAL) /* DQM1 */
855 MXC_DCD_ITEM(0x53fa8560, DQM_VAL) /* DQM2 */
856 MXC_DCD_ITEM(0x53fa8554, DQM_VAL) /* DQM3 */
858 MXC_DCD_ITEM(0x53fa857c, SDQS_VAL) /* SDQS0 */
859 MXC_DCD_ITEM(0x53fa8590, SDQS_VAL) /* SDQS1 */
860 MXC_DCD_ITEM(0x53fa8568, SDQS_VAL) /* SDQS2 */
861 MXC_DCD_ITEM(0x53fa8558, SDQS_VAL) /* SDQS3 */
863 MXC_DCD_ITEM(0x53fa8580, SDODT_VAL) /* SDODT0 */
864 MXC_DCD_ITEM(0x53fa8578, SDCLK_VAL) /* SDCLK0 */
866 MXC_DCD_ITEM(0x53fa8564, SDODT_VAL) /* SDODT1 */
867 MXC_DCD_ITEM(0x53fa8570, SDCLK_VAL) /* SDCLK1 */
869 MXC_DCD_ITEM(0x53fa858c, SDCKE_VAL) /* SDCKE0 */
870 MXC_DCD_ITEM(0x53fa855c, SDCKE_VAL) /* SDCKE1 */
872 MXC_DCD_ITEM(0x53fa8574, DSE_MASK) /* DRAM_CAS */
873 MXC_DCD_ITEM(0x53fa8588, DSE_MASK) /* DRAM_RAS */
875 MXC_DCD_ITEM(0x53fa86f0, DSE_MASK) /* GRP_ADDDS */
876 MXC_DCD_ITEM(0x53fa8720, DSE_MASK) /* GRP_CTLDS */
877 MXC_DCD_ITEM(0x53fa8718, DSE_MASK) /* GRP_B0DS */
878 MXC_DCD_ITEM(0x53fa871c, DSE_MASK) /* GRP_B1DS */
879 MXC_DCD_ITEM(0x53fa8728, DSE_MASK) /* GRP_B2DS */
880 MXC_DCD_ITEM(0x53fa872c, DSE_MASK) /* GRP_B3DS */
882 /* calibration defaults */
883 MXC_DCD_ITEM(0x63fd904c, 0x001f001f)
884 MXC_DCD_ITEM(0x63fd9050, 0x001f001f)
885 MXC_DCD_ITEM(0x63fd907c, 0x011e011e)
886 MXC_DCD_ITEM(0x63fd9080, 0x011f0120)
887 MXC_DCD_ITEM(0x63fd9088, 0x3a393d3b)
888 MXC_DCD_ITEM(0x63fd9090, 0x3f3f3f3f)
890 MXC_DCD_ITEM(0x63fd9018, ESDMISC_VAL)
891 MXC_DCD_ITEM(0x63fd9000, ESDCTL_VAL)
892 MXC_DCD_ITEM(0x63fd900c, ESDCFG0_VAL)
893 MXC_DCD_ITEM(0x63fd9010, ESDCFG1_VAL)
894 MXC_DCD_ITEM(0x63fd9014, ESDCFG2_VAL)
896 MXC_DCD_ITEM(0x63fd902c, 0x000026d2)
897 MXC_DCD_ITEM(0x63fd9030, ESDOR_VAL)
898 MXC_DCD_ITEM(0x63fd9008, ESDOTC_VAL)
899 MXC_DCD_ITEM(0x63fd9004, ESDPDC_VAL_0)
902 MXC_DCD_ITEM(0x63fd901c, 0x00008000) /* CON_REQ */
903 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, 0x63fd901c, 0x00004000)
904 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
906 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 2, mr2_val)) /* MRS: MR2 */
907 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, mr3_val)) /* MRS: MR3 */
908 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: MR1 */
909 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 0, mr0_val)) /* MRS: MR0 */
910 #if BANK_ADDR_BITS > 1
912 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1, 2, 0x0000)) /* MRS: MR2 */
913 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1, 3, 0x0000)) /* MRS: MR3 */
914 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1, 1, 0x0040)) /* MRS: MR1 */
915 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1, 0, mr0_val)) /* MRS: MR0 */
917 MXC_DCD_ITEM(0x63fd9020, 3 << 14) /* disable refresh during calibration */
918 MXC_DCD_ITEM(0x63fd9058, 0x00022222)
920 MXC_DCD_ITEM(0x63fd90d0, 0x00000003) /* select default compare pattern for calibration */
923 MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
924 MXC_DCD_ITEM(0x63fd901c, 0x00008040) /* MRS: ZQ calibration */
925 MXC_DCD_ITEM(0x63fd9040, 0x0539002b) /* Force ZQ calibration */
926 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x63fd9040, 0x00010000)
927 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
929 /* DQS calibration */
930 MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
931 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */
932 MXC_DCD_ITEM(0x63fd907c, 0x90000000) /* reset RD fifo and start DQS calib. */
934 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x63fd907c, 0x90000000)
935 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
936 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
938 /* WR DL calibration */
939 MXC_DCD_ITEM(0x63fd901c, 0x00008000)
940 MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
941 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */
942 MXC_DCD_ITEM(0x63fd90a4, 0x00000010)
944 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x63fd90a4, 0x00000010)
945 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
946 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
948 /* RD DL calibration */
949 MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
950 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */
951 MXC_DCD_ITEM(0x63fd90a0, 0x00000010)
953 MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x63fd90a0, 0x00000010)
954 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
955 MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
956 MXC_DCD_ITEM(0x63fd9020, (3 << 11) | (0 << 14)) /* refresh interval: 4 cycles every 64kHz period */
957 MXC_DCD_ITEM(0x63fd9004, ESDPDC_VAL_1)
959 /* DDR calibration done */
960 MXC_DCD_ITEM(0x63fd901c, 0x00000000)
964 MXC_DCD_ITEM(0x53fa819c, 0x00000000) @ EIM_DA0
965 MXC_DCD_ITEM(0x53fa81a0, 0x00000000) @ EIM_DA1
966 MXC_DCD_ITEM(0x53fa81a4, 0x00000000) @ EIM_DA2
967 MXC_DCD_ITEM(0x53fa81a8, 0x00000000) @ EIM_DA3
968 MXC_DCD_ITEM(0x53fa81ac, 0x00000000) @ EIM_DA4
969 MXC_DCD_ITEM(0x53fa81b0, 0x00000000) @ EIM_DA5
970 MXC_DCD_ITEM(0x53fa81b4, 0x00000000) @ EIM_DA6
971 MXC_DCD_ITEM(0x53fa81b8, 0x00000000) @ EIM_DA7
972 MXC_DCD_ITEM(0x53fa81dc, 0x00000000) @ WE_B
973 MXC_DCD_ITEM(0x53fa81e0, 0x00000000) @ RE_B
974 MXC_DCD_ITEM(0x53fa8228, 0x00000000) @ CLE
975 MXC_DCD_ITEM(0x53fa822c, 0x00000000) @ ALE
976 MXC_DCD_ITEM(0x53fa8230, 0x00000000) @ WP_B
977 MXC_DCD_ITEM(0x53fa8234, 0x00000000) @ RB0
978 MXC_DCD_ITEM(0x53fa8238, 0x00000000) @ CS0
980 MXC_DCD_ITEM(0x53fa84ec, 0x000000e4) @ EIM_DA0
981 MXC_DCD_ITEM(0x53fa84f0, 0x000000e4) @ EIM_DA1
982 MXC_DCD_ITEM(0x53fa84f4, 0x000000e4) @ EIM_DA2
983 MXC_DCD_ITEM(0x53fa84f8, 0x000000e4) @ EIM_DA3
984 MXC_DCD_ITEM(0x53fa84fc, 0x000000e4) @ EIM_DA4
985 MXC_DCD_ITEM(0x53fa8500, 0x000000e4) @ EIM_DA5
986 MXC_DCD_ITEM(0x53fa8504, 0x000000e4) @ EIM_DA6
987 MXC_DCD_ITEM(0x53fa8508, 0x000000e4) @ EIM_DA7
988 MXC_DCD_ITEM(0x53fa852c, 0x00000004) @ NANDF_WE_B
989 MXC_DCD_ITEM(0x53fa8530, 0x00000004) @ NANDF_RE_B
990 MXC_DCD_ITEM(0x53fa85a0, 0x00000004) @ NANDF_CLE_B
991 MXC_DCD_ITEM(0x53fa85a4, 0x00000004) @ NANDF_ALE_B
992 MXC_DCD_ITEM(0x53fa85a8, 0x000000e4) @ NANDF_WE_B
993 MXC_DCD_ITEM(0x53fa85ac, 0x000000e4) @ NANDF_RB0
994 MXC_DCD_ITEM(0x53fa85b0, 0x00000004) @ NANDF_CS0
998 W_CSCMR1_VAL: .word 0xa6a2a020
999 W_CSCDR1_VAL: .word 0x00080b18
1000 W_DP_OP_1000: .word DP_OP_1000
1001 W_DP_MFD_1000: .word DP_MFD_1000
1002 W_DP_MFN_1000: .word DP_MFN_1000
1003 W_DP_OP_800: .word DP_OP_800
1004 W_DP_MFD_800: .word DP_MFD_800
1005 W_DP_MFN_800: .word DP_MFN_800
1006 W_DP_OP_700: .word DP_OP_700
1007 W_DP_MFD_700: .word DP_MFD_700
1008 W_DP_MFN_700: .word DP_MFN_700
1009 W_DP_OP_400: .word DP_OP_400
1010 W_DP_MFD_400: .word DP_MFD_400
1011 W_DP_MFN_400: .word DP_MFN_400
1012 W_DP_OP_532: .word DP_OP_532
1013 W_DP_MFD_532: .word DP_MFD_532
1014 W_DP_MFN_532: .word DP_MFN_532
1015 W_DP_OP_666: .word DP_OP_666
1016 W_DP_MFD_666: .word DP_MFD_666
1017 W_DP_MFN_666: .word DP_MFN_666
1018 W_DP_OP_665: .word DP_OP_665
1019 W_DP_MFD_665: .word DP_MFD_665
1020 W_DP_MFN_665: .word DP_MFN_665
1021 W_DP_OP_216: .word DP_OP_216
1022 W_DP_MFD_216: .word DP_MFD_216
1023 W_DP_MFN_216: .word DP_MFN_216
1024 W_DP_OP_333: .word DP_OP_333
1025 W_DP_MFD_333: .word DP_MFD_333
1026 W_DP_MFN_333: .word DP_MFN_333
1027 W_DP_OP_266: .word DP_OP_266
1028 W_DP_MFD_266: .word DP_MFD_266
1029 W_DP_MFN_266: .word DP_MFN_266
1030 PLATFORM_CLOCK_DIV: .word 0x00000124
1032 /*----------------------------------------------------------------------*/
1033 /* end of hal_platform_setup.h */
1034 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */