1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 //=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 // You should have received a copy of the GNU General Public License along
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
31 // with other works to produce a work based on this file, this file does not
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33 // License. However the source code for this file must still be made available
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40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //===========================================================================
45 #include <pkgconf/system.h> // System-wide configuration info
46 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
47 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
48 #include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
49 #include <cyg/hal/hal_mmu.h> // MMU definitions
50 #include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
52 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
53 #define PLATFORM_SETUP1 _platform_setup1
54 #define CYGHWR_HAL_ARM_HAS_MMU
56 #ifdef CYG_HAL_STARTUP_ROMRAM
57 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
60 #define CYGHWR_HAL_ROM_VADDR 0x0
61 #undef CLOCK_SETUP_ALIGNED
63 // This macro represents the initial startup code for the platform
64 .macro _platform_setup1
65 FSL_BOARD_SETUP_START:
68 * - invalidate I/D cache/TLB and drain write buffer;
69 * - invalidate L2 cache
71 * - branch predictions
73 #ifdef TURN_OFF_IMPRECISE_ABORT
79 mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
80 mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
81 mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
83 /* Also setup the Peripheral Port Remap register inside the core */
84 ldr r0, ARM_PPMRR /* start from AIPS 2GB region */
85 mcr p15, 0, r0, c15, c2, 4
87 /*** L2 Cache setup/invalidation/disable ***/
88 /* Disable L2 cache first */
89 mov r0, #L2CC_BASE_ADDR
90 ldr r2, [r0, #L2_CACHE_CTL_REG]
92 str r2, [r0, #L2_CACHE_CTL_REG]
95 * - 128k size(16k way)
96 * - 8-way associativity
97 * - 0 ws TAG/VALID/DIRTY
100 ldr r1, [r0, #L2_CACHE_AUX_CTL_REG]
101 and r1, r1, #0xFE000000
102 ldr r2, L2CACHE_PARAM
104 str r1, [r0, #L2_CACHE_AUX_CTL_REG]
108 str r1, [r0, #L2_CACHE_INV_WAY_REG]
110 /* Poll Invalidate By Way register */
111 ldr r2, [r0, #L2_CACHE_INV_WAY_REG]
114 /*** End of L2 operations ***/
116 mov r0, #SDRAM_NON_FLASH_BOOT
117 ldr r1, AVIC_VECTOR0_ADDR_W
118 str r0, [r1] // for checking boot source from nand, nor or sdram
120 * End of ARM1136 init
134 // Note: enabling above setup causes the following "mov r0, #NOR_FLASH_BOOT"
135 // loading r0=0xb8002000 instead of NOR_FLASH_BOOT(0x0). This can be fixed
136 // by force aligning this "mov r0, #NOR_FLASH_BOOT" to 32-byte boundry.
137 // Remove it now as it is really not needed anyway.
139 // If SDRAM has been setup, bypass clock/WEIM setup
140 cmp pc, #SDRAM_BASE_ADDR
142 cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
143 blo HWInitialise_skip_SDRAM_setup
145 mov r0, #NOR_FLASH_BOOT
146 ldr r1, AVIC_VECTOR0_ADDR_W
149 // Disable the SDCLK by clearing SDE (bit 31) in ESDCTL0 and ESDCTL1
150 // (as the DDR chip needs a stable clock after CKE is high)
151 ldr r0, ESDCTL_BASE_W
152 ldr r1, SDRAM_0x02216080
153 str r1, [r0, #ESDCTL_ESDCTL0]
154 str r1, [r0, #ESDCTL_ESDCTL1]
162 HWInitialise_skip_SDRAM_setup:
165 add r2, r0, #0x800 // 2K window
167 blo Normal_Boot_Continue
169 bhi Normal_Boot_Continue
171 /* Copy image from flash to SDRAM first */
172 ldr r1, MXC_REDBOOT_ROM_START
174 1: ldmia r0!, {r3-r10}
180 and r0, pc, r1 /* offset of pc */
181 ldr r1, MXC_REDBOOT_ROM_START
189 mov r0, #NAND_FLASH_BOOT
190 ldr r1, AVIC_VECTOR0_ADDR_W
193 ldr r1, AVIC_VECTOR1_ADDR_W
196 mov r0, #NFC_BASE; //r0: nfc base. Reloaded after each page copying
197 mov r1, #0x800 //r1: starting flash addr to be copied. Updated constantly
198 add r2, r0, #0x200 //r2: end of 1st RAM buf. Doesn't change
199 add r12, r0, #0xE00 //r12: NFC register base. Doesn't change
200 ldr r14, MXC_REDBOOT_ROM_START
201 add r13, r14, #REDBOOT_IMAGE_SIZE //r13: end of SDRAM address for copying. Doesn't change
202 add r14, r14, r1 //r14: starting SDRAM address for copying. Updated constantly
204 //unlock internal buffer
209 // writew(FLASH_Read_Mode1, NAND_FLASH_CMD_REG);
211 strh r3, [r12, #NAND_FLASH_CMD_REG_OFF]
212 mov r3, #NAND_FLASH_CONFIG2_FCMD_EN;
213 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
216 // start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, nflash_dev_info->base_mask);
218 do_addr_input //1st addr cycle
220 do_addr_input //2nd addr cycle
222 do_addr_input //3rd addr cycle
224 do_addr_input //4th addr cycle
226 // NFC_DATA_OUTPUT(buf, FDO_PAGE_SPARE_VAL);
227 // writew(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN,
228 // NAND_FLASH_CONFIG1_REG);
229 mov r3, #(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN)
230 strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
232 // writew(buf_no, RAM_BUFFER_ADDRESS_REG);
234 strh r3, [r12, #RAM_BUFFER_ADDRESS_REG_OFF]
235 // writew(FDO_PAGE_SPARE_VAL & 0xFF, NAND_FLASH_CONFIG2_REG);
236 mov r3, #FDO_PAGE_SPARE_VAL
237 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
241 // check for bad block
242 mov r3, r1, lsl #(32-5-9)
243 cmp r3, #(512 << (32-5-9))
245 add r4, r0, #0x800 //r3 -> spare area buf 0
250 // really sucks. Bad block!!!!
253 // even suckier since we already read the first page!
254 sub r14, r14, #512 //rewind 1 page for the sdram pointer
255 sub r1, r1, #512 //rewind 1 page for the flash pointer
257 add r1, r1, #(32*512)
261 1: ldmia r0!, {r3-r10}
266 bge NAND_Copy_Main_done
273 Normal_Boot_Continue:
275 #ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
276 /* Copy image from flash to SDRAM first */
279 ldr r1, MXC_REDBOOT_ROM_START
281 beq HWInitialise_skip_SDRAM_copy
283 add r2, r0, #REDBOOT_IMAGE_SIZE
285 1: ldmia r0!, {r3-r10}
291 and r0, pc, r1 /* offset of pc */
292 ldr r1, =(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000 + 0x8)
298 #endif /* CYG_HAL_STARTUP_ROMRAM */
300 HWInitialise_skip_SDRAM_copy:
311 * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity
315 // Set up a stack [for calling C code]
316 ldr r1, =__startup_stack
317 ldr r2, =RAM_BANK0_BASE
325 mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
326 orr r1, r1, #7 // enable MMU bit
327 mcr MMU_CP, 0, r1, MMU_Control, c0
328 mov pc,r2 /* Change address spaces */
334 // Save shadow copy of BCR, also hardware configuration
338 str r9, [r1] // Saved far above...
340 .endm // _platform_setup1
342 #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
343 #define PLATFORM_SETUP1
346 /* Allow all 3 masters to have access to these shared peripherals */
348 ldr r0, SPBA_CTRL_BASE_ADDR_W
350 ldr r1, =0x7 /* allow all 3 masters access */
351 ldr r2, SPBA_LOCK_VAL
361 .endm /* init_spba */
363 /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
366 * Set all MPROTx to be non-bufferable, trusted for R/W,
367 * not forced to user-mode.
369 ldr r0, AIPS1_CTRL_BASE_ADDR_W
370 ldr r1, AIPS1_PARAM_W
373 ldr r0, AIPS2_CTRL_BASE_ADDR_W
378 * Clear the on and off peripheral modules Supervisor Protect bit
379 * for SDMA to access them. Did not change the AIPS control registers
380 * (offset 0x20) access type
382 ldr r0, AIPS1_CTRL_BASE_ADDR_W
389 and r1, r1, #0x00FFFFFF
392 ldr r0, AIPS2_CTRL_BASE_ADDR_W
399 and r1, r1, #0x00FFFFFF
401 .endm /* init_aips */
403 /* MAX (Multi-Layer AHB Crossbar Switch) setup */
405 ldr r0, MAX_BASE_ADDR_W
406 /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
408 str r1, [r0, #0x000] /* for S0 */
409 str r1, [r0, #0x100] /* for S1 */
410 str r1, [r0, #0x200] /* for S2 */
411 str r1, [r0, #0x300] /* for S3 */
412 str r1, [r0, #0x400] /* for S4 */
413 /* SGPCR - always park on last master */
415 str r1, [r0, #0x010] /* for S0 */
416 str r1, [r0, #0x110] /* for S1 */
417 str r1, [r0, #0x210] /* for S2 */
418 str r1, [r0, #0x310] /* for S3 */
419 str r1, [r0, #0x410] /* for S4 */
420 /* MGPCR - restore default values */
422 str r1, [r0, #0x800] /* for M0 */
423 str r1, [r0, #0x900] /* for M1 */
424 str r1, [r0, #0xA00] /* for M2 */
425 str r1, [r0, #0xB00] /* for M3 */
426 str r1, [r0, #0xC00] /* for M4 */
427 str r1, [r0, #0xD00] /* for M5 */
432 #ifdef CLOCK_SETUP_ALIGNED
437 ldr r0, CRM_MCU_BASE_ADDR_W
438 // enable MPLL, UPLL, TurboPLL
439 ldr r1, CRM_MCR_0x18FF2952
440 str r1, [r0, #CLKCTL_MCR]
443 ldr r1, [r0, #CLKCTL_MCR]
447 #if 1 // for 133MHz HCLK
448 ldr r1, TPCTL_PARAM_532_W
449 str r1, [r0, #CLKCTL_TPCTL]
450 ldr r1, PDR0_399_133_66_W
452 ldr r1, TPCTL_PARAM_500_W
453 str r1, [r0, #CLKCTL_TPCTL]
454 ldr r1, PDR0_399_100_50_W
457 // add some delay here
462 #ifdef CLOCK_SETUP_ALIGNED
467 str r1, [r0, #CLKCTL_PDR0]
468 ldr r1, MPCTL_PARAM_399_W
469 str r1, [r0, #CLKCTL_MPCTL]
471 /* Set to default values */
472 ldr r1, PDR1_0x2910AC56_W
473 str r1, [r0, #CLKCTL_PDR1]
474 /* Set UPLL=288MHz */
475 ldr r1, UPCTL_PARAM_288_W
476 str r1, [r0, #CLKCTL_UPCTL]
479 * J10 (CPU card) - CKO1=MCU_PLL div by 8
480 * J9 (CPU card) - CKO2=IPG_CLK_ARM div by 8
482 ldr r1, CRM_COSR_0x00036C58
483 str r1, [r0, #CLKCTL_COSR]
484 .endm /* init_clock */
488 /* Configure M3IF registers */
491 * M3IF Control Register (M3IFCTL)
492 * MRRP[0] = TMAX not on priority list (0 << 0) = 0x00000000
493 * MRRP[1] = SMIF not on priority list (0 << 0) = 0x00000000
494 * MRRP[2] = MAX0 not on priority list (0 << 0) = 0x00000000
495 * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
496 * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
497 * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
498 * MRRP[6] = IPU on priority list (1 << 6) = 0x00000040
499 * MRRP[7] = SMIF-L2CC not on priority list (0 << 0) = 0x00000000
504 str r0, [r1] /* M3IF control reg */
505 .endm /* init_m3if */
507 /* CS0 sync mode setup */
509 // setup the sync mode in the flash itself first
510 mov r0, #CS0_BASE_ADDR
511 add r0, r0, #0x00004300
516 // setup the sync mode in the WEIM
517 ldr r0, WEIM_BASE_ADDR_W
518 ldr r1, CS0_CSCRU_0x23D29000
520 ldr r1, CS0_CSCRL_0x60000D01
524 .endm /* init_cs0_sync */
526 /* CS0 async mode setup */
527 .macro init_cs0_async
528 // setup the async mode in the flash itself first
529 mov r0, #CS0_BASE_ADDR
530 add r0, r0, #0x00017000
531 add r0, r0, #0x00000700
536 /* CS0 setup: Configuring the CS0 in Asynchronous mode */
537 ldr r0, WEIM_BASE_ADDR_W /* 0xB8002000 */
538 ldr r1, CS0_CSCRU_0x23C29000 /* no sync/burst */
539 str r1, [r0, #CSCRU] /* +0x00 */
540 ldr r1, CS0_CSCRL_0x60000D01 /* 16-bit port, CS enabled */
541 str r1, [r0, #CSCRL] /* +0x04 */
542 mov r1, #0x00000080 /* decrease Write Wait State enabled */
543 str r1, [r0, #CSCRA] /* +0x08 */
544 .endm /* init_cs0_async */
551 ldr r0, =WEIM_CTRL_CS2
561 .macro init_ddr_sdram
562 ldr r0, ESDCTL_BASE_W
563 ldr r2, IOMUXC_BASE_ADDR_W
564 mov r12, #SDRAM_BASE_ADDR
566 // 3. Enable the SDCLK by setting SDE (bit 31) in ESDCTL1
567 // reg32_write(ESDCTL1, 0x82216080);
568 ldr r1, SDRAM_0x02216080
569 add r1, r1, #0x80000000
570 str r1, [r0, #ESDCTL_ESDCTL1]
571 // 4. Put the CSD0 controller in Manual Self Refresh, with SREFR=0
572 // and PWDT=2 or 3. This step is needed to be able to enter properly
573 // the Low Power modes
574 // reg32_write(ESDCTL0, (0xc2216080 & 0xffff13ff) + (3<<10));
575 ldr r1, SDRAM_0x02210C80
576 str r1, [r0, #ESDCTL_ESDCTL0]
577 // 5. Wait for the SDRAMRDY bit (bit 31 in ESDMISC) to be set. This bit
578 // indicates that the SDRAM is ready for use.
580 ldr r1, [r0, #ESDCTL_ESDMISC]
581 ands r1, r1, #0x80000000
583 // 6. Reset the ESDCTL and the ESDCTL delay lines:
584 // reg32_write(ESDMISC, 0x000000f)
586 str r1, [r0, #ESDCTL_ESDMISC]
587 // 7. Set the proper delay lines correction:
588 // reg32_write(ESDCDLY1, 0x00280000);
589 // reg32_write(ESDCDLY2, 0x00280000);
590 // reg32_write(ESDCDLY5, 0x003e0000);
591 // For Read, only ESDCDLY1 and ESDCDLY2 have to be initialized, as 16
592 // bit memory is used.
594 str r1, [r0, #ESDCTL_ESDCDLY1]
595 str r1, [r0, #ESDCTL_ESDCDLY2]
597 str r1, [r0, #ESDCTL_ESDCDLY5]
598 // 8. Configure the ESDCTL timing parameters (see Table 4 for details):
599 // reg32_write(ESDCFG1, 0x00795729);
600 ldr r1, SDRAM_0x00795729
601 str r1, [r0, #ESDCTL_ESDCFG1]
602 // 9. Remove ESDRAMC reset (this step is not mandatory, as the RST bit in
603 // ESDMISC is auto-clearing)
604 // reg32_write(ESDMISC, 0x0000000d);
606 str r1, [r0, #ESDCTL_ESDMISC]
607 // 10. Set the pads drive strengths / DDR mode (MCU accesses):
608 // reg32_write(0x500003d0, 0x00000007);//sw_pad_ctl_sdqs0="111"
609 // reg32_write(0x500003c4, 0x00001800);//sw_pad_ctl_oe_b="110"
610 // reg32_write(0x500003C8, 0x00700000);//sw_pad_ctl_dqm0="111"
611 // reg32_write(0x500003F8, 0x00700000);//sw_pad_ctl_sd0="111"
612 // reg32_write(0x5000041C, 0x00700000);//sw_pad_ctl_a0_ma0='111'
625 // 11. Wait for 200us (as the DDR clock must be stable for at least
626 // 200us and the delay line measurement needs at least 16us after
627 // a reset before being operational).
633 // 12. Send a Precharge command to all banks, using a Byte access with A10 high.
634 // reg32_write(ESDCTL1, 0x92216080);
635 // reg8_write(0x90000400, 0x00);
636 ldr r1, SDRAM_0x92216080
637 str r1, [r0, #ESDCTL_ESDCTL1]
639 strb r1, [r12, #0x400]
641 // 13. Send (at least) 2 AutoRefresh commands. They must be separated by at
642 // least tRFC = 75ns (10 tck at 133 MHz)
643 // reg32_write(ESDCTL1, 0xA2216080);
644 // reg16_write(0x90000000, 0x0000);
646 // reg16_write(0x90000000, 0x0000);
647 ldr r1, SDRAM_0xA2216080
648 str r1, [r0, #ESDCTL_ESDCTL1]
659 // 14. Place the SDCTL in Load Mode Register Command mode
660 // reg32_write(ESDCTL1, 0xB2216080);
661 ldr r1, SDRAM_0xB2216080
662 str r1, [r0, #ESDCTL_ESDCTL1]
663 // 15. Set the DDR Mode Register. Set the Burst Size to 8, the Burst Mode
664 // to Sequential, the CAS latency to 3. Byte Access is required.
665 // reg8_write(0x90000033, 0x00);
667 strb r1, [r12, #0x33]
668 // 16. Set the DDR Extended Mode Register. The DDR drive strength should
669 // be set to Full Drive. The access is done in Bank 2. A Byte Access
671 // (There should be at least tMRD = 15ns between the access to MR
672 // and EMR, but this is taken care by SDCTL).
673 // reg8_write(0x92000000, 0x00);
674 add r11, r12, #0x02000000
676 // 17. Put the DDR controller in Normal operating mode
677 // reg32_write(ESDCTL1, 0x82216080);
678 ldr r3, SDRAM_0x82216080 /* 16 bit memory */
679 str r3, [r0, #ESDCTL_ESDCTL1]
680 // 18. Perform a 16-bit Read
681 // reg32_read(0x90000000);
685 .macro do_wait_op_done
687 ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
688 ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
691 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
692 .endm // do_wait_op_done
696 strh r3, [r12, #NAND_FLASH_ADD_REG_OFF]
697 mov r3, #NAND_FLASH_CONFIG2_FADD_EN
698 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
700 .endm // do_addr_input
702 /* To support 133MHz SDR */
703 .macro init_drive_strength
704 // No need to change the default drive strength for DDR
705 .endm /* init_drive_strength */
709 * Deal with DSP reset
715 beq skip_dsp_switch_le
716 bic r1, r1, #(1 << 5)
720 /* Put DSP in reset */
724 /* Hold for some time */
730 /* Put DSP out of reset */
734 #define PLATFORM_VECTORS _platform_vectors
735 .macro _platform_vectors
736 .globl _board_BCR, _board_CFG
737 _board_BCR: .long 0 // Board Control register shadow
738 _board_CFG: .long 0 // Board Configuration (read at RESET)
741 #define PLATFORM_PREAMBLE _switch_to_le
744 .word 0xEE110F10 // mrc 15, 0, r0, c1, c0, 0
745 .word 0xE3C00080 // bic r0, r0, #0x80
746 .word 0xEE010F10 // mcr 15, 0, r0, c1, c0, 0
748 .word 0x0F10EE11 // mrc 15, 0, r0, c1, c0, 0
749 .word 0x0080E3C0 // bic r0, r0, #0x80
750 .word 0x0F10EE01 // mcr 15, 0, r0, c1, c0, 0
761 #if 0 /// good for SDRAM since 32bit
762 .word 0xEE110F10 // mrc 15, 0, r0, c1, c0, 0
763 .word 0xE3C00080 // bic r0, r0, #0x80
764 .word 0xEE010F10 // mcr 15, 0, r0, c1, c0, 0
767 ARM_PPMRR: .word 0x40000015
768 L2CACHE_PARAM: .word 0x00030024
769 IIM_SREV_REG_VAL: .word IIM_BASE_ADDR + IIM_SREV_OFF
770 AIPS1_CTRL_BASE_ADDR_W: .word AIPS1_CTRL_BASE_ADDR
771 AIPS2_CTRL_BASE_ADDR_W: .word AIPS2_CTRL_BASE_ADDR
772 AIPS1_PARAM_W: .word 0x77777777
773 MAX_BASE_ADDR_W: .word MAX_BASE_ADDR
774 MAX_PARAM1: .word 0x00302154
775 RVAL_WVAL_W: .word 0x515
776 CLKCTL_BASE_ADDR_W: .word CLKCTL_BASE_ADDR
777 CRM_MCR_0x18FF2902: .word 0x18FF2902
778 CRM_MCR_0x18FF2952: .word 0x18FF2952
779 CRM_COSR_0x00036C58: .word 0x00036C58
780 PDR0_399_100_50_W: .word PDR0_399_100_50
781 PDR0_399_133_66_W: .word PDR0_399_133_66
782 PDR0_399_66_66_W: .word PDR0_399_66_66
783 PDR1_0x2910AC56_W: .word 0x2910AC56
784 MPCTL_PARAM_399_W: .word MPCTL_PARAM_399
785 UPCTL_PARAM_288_W: .word UPCTL_PARAM_288
786 TPCTL_PARAM_500_W: .word TPCTL_PARAM_500
787 TPCTL_PARAM_532_W: .word TPCTL_PARAM_532
788 SPBA_CTRL_BASE_ADDR_W: .word SPBA_CTRL_BASE_ADDR
789 SPBA_LOCK_VAL: .word 0xC0010007
790 ESDCTL_BASE_W: .word ESDCTL_BASE
791 M3IF_BASE_W: .word M3IF_BASE
792 SDRAM_0x02216080: .word 0x02216080
793 SDRAM_0x82216080: .word 0x82216080
794 SDRAM_0x92216080: .word 0x92216080
795 SDRAM_0xA2216080: .word 0xA2216080
796 SDRAM_0xB2216080: .word 0xB2216080
797 SDRAM_0x00795729: .word 0x00795729
798 SDRAM_0x02210C80: .word 0x02210C80
799 WEIM_BASE_ADDR_W: .word WEIM_BASE_ADDR
800 CS0_CSCRU_0x23C29000: .word 0x23C29000
801 CS0_CSCRL_0x60000D01: .word 0x60000D01
802 CS0_CSCRU_0x23D29000: .word 0x23D29000
803 DS_0x12449D24: .word 0x12449D24
804 IOMUXC_BASE_ADDR_W: .word IOMUXC_BASE_ADDR
805 CRM_MCU_BASE_ADDR_W: .word CRM_MCU_BASE_ADDR
806 MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
807 CONST_0x0FFF: .word 0x0FFF
808 AVIC_VECTOR0_ADDR_W: .word MXCBOOT_FLAG_REG
809 AVIC_VECTOR1_ADDR_W: .word MXCFIS_FLAG_REG
811 /*---------------------------------------------------------------------------*/
812 /* end of hal_platform_setup.h */
813 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */