1 //==========================================================================
5 // SoC chip definitions
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12 // Copyright (C) 2002 Gary Thomas
14 // eCos is free software; you can redistribute it and/or modify it under
15 // the terms of the GNU General Public License as published by the Free
16 // Software Foundation; either version 2 or (at your option) any later version.
18 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
23 // You should have received a copy of the GNU General Public License along
24 // with eCos; if not, write to the Free Software Foundation, Inc.,
25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 // As a special exception, if other files instantiate templates or use macros
28 // or inline functions from this file, or you compile this file and link it
29 // with other works to produce a work based on this file, this file does not
30 // by itself cause the resulting work to be covered by the GNU General Public
31 // License. However the source code for this file must still be made available
32 // in accordance with section (3) of the GNU General Public License.
34 // This exception does not invalidate any other reasons why a work based on
35 // this file might be covered by the GNU General Public License.
37 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
38 // at http://sources.redhat.com/ecos/ecos-license/
39 // -------------------------------------------
40 //####ECOSGPLCOPYRIGHTEND####
41 //========================================================================*/
48 #define REG8_VAL(a) (a)
49 #define REG16_VAL(a) (a)
50 #define REG32_VAL(a) (a)
52 #define REG8_PTR(a) (a)
53 #define REG16_PTR(a) (a)
54 #define REG32_PTR(a) (a)
56 #else /* __ASSEMBLER__ */
58 extern char HAL_PLATFORM_EXTRA[];
59 #define REG8_VAL(a) ((unsigned char)(a))
60 #define REG16_VAL(a) ((unsigned short)(a))
61 #define REG32_VAL(a) ((unsigned int)(a))
63 #define REG8_PTR(a) ((volatile unsigned char *)(a))
64 #define REG16_PTR(a) ((volatile unsigned short *)(a))
65 #define REG32_PTR(a) ((volatile unsigned int *)(a))
66 #define readb(a) (*(volatile unsigned char *)(a))
67 #define readw(a) (*(volatile unsigned short *)(a))
68 #define readl(a) (*(volatile unsigned int *)(a))
69 #define writeb(v,a) (*(volatile unsigned char *)(a) = (v))
70 #define writew(v,a) (*(volatile unsigned short *)(a) = (v))
71 #define writel(v,a) (*(volatile unsigned int *)(a) = (v))
73 #endif /* __ASSEMBLER__ */
76 * Default Memory Layout Definitions
79 #define L2CC_BASE_ADDR 0x30000000
84 #define AIPS1_BASE_ADDR 0x43F00000
85 #define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
86 #define MAX_BASE_ADDR 0x43F04000
87 #define EVTMON_BASE_ADDR 0x43F08000
88 #define CLKCTL_BASE_ADDR 0x43F0C000
89 #define ETB_SLOT4_BASE_ADDR 0x43F10000
90 #define ETB_SLOT5_BASE_ADDR 0x43F14000
91 #define ECT_CTIO_BASE_ADDR 0x43F18000
92 #define I2C_BASE_ADDR 0x43F80000
93 #define MU_BASE_ADDR 0x43F84000
94 #define GPC_BASE_ADDR 0x43F88000
95 #define VPU_BASE_ADDR 0x43F8C000
96 #define CTI_AP_BASE_ADDR 0x43F90000
97 #define DSM_BASE_ADDR 0x43F98000
98 #define OWIRE_BASE_ADDR 0x43F9C000
99 #define KPP_BASE_ADDR 0x43FA8000
104 #define SPBA_BASE_ADDR 0x50000000
105 #define UART4_BASE_ADDR 0x50000000
106 #define MMC_SDHC1_BASE_ADDR 0x50004000
107 #define MMC_SDHC2_BASE_ADDR 0x50008000
108 #define UART1_BASE_ADDR 0x5000C000
109 #define UART2_BASE_ADDR 0x50010000
110 #define SSI1_BASE_ADDR 0x50014000
111 #define SIM1_BASE_ADDR 0x50018000
112 #define IIM_BASE_ADDR 0x5001C000
113 #define SDMA_CTI_BASE_ADDR 0x50020000
114 #define USBOTG_BASE_ADDR 0x50024000
115 #define UART3_BASE_ADDR 0x5002C000
116 #define CSPI1_BASE_ADDR 0x50030000
117 #define SPBA_CTRL_BASE_ADDR 0x5003C000
118 #define IOMUXC_BASE_ADDR 0x50040000
119 #define SRC_BASE_ADDR 0x50044000
120 #define CRM_AP_BASE_ADDR 0x50048000
121 #define PLL_AP_BASE_ADDR 0x5004C000
122 #define PLL_BP_BASE_ADDR 0x50050000
123 #define PLL_USB_BASE_ADDR 0x50054000
124 #define GPIO2_BASE_ADDR 0x50058000
125 #define RTIC_BASE_ADDR 0x5005C000
126 #define SCC_BASE 0x50060000
127 #define SAHARA_BASE 0x50064000
128 #define MAX_SP_BASE_ADDR 0x50068000
129 #define IOMUX_AP_BASE_ADDR 0x5006C000
130 #define GPIO1_BASE_ADDR 0x50070000
131 #define EMIV2_BASE_ADDR 0x50074000
136 #define AIPS2_BASE_ADDR 0x53F00000
137 #define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
138 #define GPT_BASE_ADDR 0x53F90000
139 #define EPIT1_BASE_ADDR 0x53F94000
140 #define RTR_BASE_ADDR 0x53F98000
141 #define IPU_CTRL_BASE_ADDR 0x53FC0000
142 #define AUDMUX_BASE 0x53FC4000
143 #define EDIO_BASE_ADDR 0x53FC8000
144 #define HSCS_BASE_ADDR 0x53FCC000
145 #define LPMC_BASE_ADDR 0x53FD0000
146 #define SDMA_BASE_ADDR 0x53FD4000
147 #define RTC_BASE_ADDR 0x53FD8000
148 #define WDOG1_BASE_ADDR 0x53FDC000
149 #define WDOG_BASE_ADDR WDOG1_BASE_ADDR
152 * DSP Peripheral registers
154 #define DSP_CRM_BP 0xFFFC8000
159 #define ROMPATCH_BASE_ADDR 0x60000000
160 #define AVIC_BASE_ADDR 0x68000000
163 * NAND, SDRAM, WEIM, M3IF, EMI controllers
165 #define ESDCTL_BASE (EMIV2_BASE_ADDR + 0x1000)
166 #define WEIM_BASE_ADDR (EMIV2_BASE_ADDR + 0x2000)
167 #define NFC_IP_BASE (EMIV2_BASE_ADDR + 0x3000)
168 #define WEIM_CTRL_CS0 WEIM_BASE_ADDR
169 #define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x18)
170 #define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x30)
171 #define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x48)
172 #define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x60)
173 #define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x78)
174 #define M4IF_BASE EMIV2_BASE_ADDR
175 #define EMIV2_CTRL_BASE_ADDR (EMIV2_BASE_ADDR + 0x3F00)
178 * Memory regions and CS
180 #define IPU_MEM_BASE_ADDR 0x70000000
181 #define CSD0_BASE_ADDR 0x80000000
182 #define CSD1_BASE_ADDR 0x90000000
183 #define CS0_BASE_ADDR 0xA0000000
184 #define CS1_BASE_ADDR 0xA8000000
185 #define CS2_BASE_ADDR 0xB0000000
186 #define CS3_BASE_ADDR 0xB2000000
187 #define CS4_BASE_ADDR 0xB4000000
188 #define CS5_BASE_ADDR 0xB6000000
190 #define INTERNAL_ROM_VA 0xF0000000
193 * IRQ Controller Register Definitions.
195 #define AVIC_NIMASK REG32_PTR(AVIC_BASE_ADDR + (0x04))
196 #define AVIC_INTTYPEH REG32_PTR(AVIC_BASE_ADDR + (0x18))
197 #define AVIC_INTTYPEL REG32_PTR(AVIC_BASE_ADDR + (0x1C))
200 #define L2CC_BASE_ADDR 0x30000000
201 #define L2_CACHE_LINE_SIZE 32
202 #define L2_CACHE_CTL_REG 0x100
203 #define L2_CACHE_AUX_CTL_REG 0x104
204 #define L2_CACHE_SYNC_REG 0x730
205 #define L2_CACHE_INV_LINE_REG 0x770
206 #define L2_CACHE_INV_WAY_REG 0x77C
207 #define L2_CACHE_CLEAN_LINE_REG 0x7B0
208 #define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0
211 #define CRM_AP_ASCSR 0x00
212 #define CRM_AP_ACSR 0x04
213 #define CRM_AP_ACDR 0x08
214 #define CRM_AP_ACDER 0x0C
215 #define CRM_AP_APR 0x10
216 #define CRM_AP_ACGCR 0x14
217 #define CRM_AP_ARCGR 0x18
218 #define CRM_AP_L1CGR0 0x1C
219 #define CRM_AP_L1CGR1 0x20
220 #define CRM_AP_L1CGR2 0x24
221 #define CRM_AP_L1CGR3 0x28
222 #define CRM_AP_L2CGR0 0x2C
223 #define CRM_AP_L2CGR1 0x30
224 #define CRM_AP_L2CGR2 0x34
225 #define CRM_AP_L2CGR3 0x38
226 #define CRM_AP_L2CGR4 0x3C
227 #define CRM_AP_L2CGR5 0x40
228 #define CRM_AP_L2CGR6 0x44
229 #define CRM_AP_L2CGR7 0x48
230 #define CRM_AP_L2CGR8 0x4C
231 #define CRM_AP_AMORA 0x50
232 #define CRM_AP_AMORB 0x54
233 #define CRM_AP_AMORC 0x58
234 #define CRM_AP_APOR 0x5C
235 #define CRM_AP_AMCR 0x60
236 #define CRM_AP_ADFMR 0x64
237 #define CRM_AP_ACR 0x68
238 #define CRM_AP_AGPR 0x6C
241 #define SRC_SBMR 0x00
242 #define SRC_SRSR 0x04
243 #define SRC_SSCR 0x08
244 #define SRC_SCRCR 0x18
246 #define SPBA_IIM 0x1C
248 /* DSP CRM_BP - only available from the DSP, or through MU */
249 #define CRM_BP_BSCSR 0x00
250 #define CRM_BP_BCSR 0x04
251 #define CRM_BP_BCDR 0x08
252 #define CRM_BP_BDCR 0x24
253 #define CRM_BP_BCGCR 0x08
254 #define CRM_BP_BMLPMRA 0x0C
255 #define CRM_BP_BMLPMRB 0x10
256 #define CRM_BP_BMLPMRC 0x14
257 #define CRM_BP_BMLPMRD 0x18
258 #define CRM_BP_BMLPMRE 0x1C
261 #define CRM_BP_BCR 0x28
262 #define CRM_BP_BMCR 0x2C
263 #define CRM_BP_BPCR 0x30
265 #define FREQ_26MHZ 26000000
266 #define FREQ_32768HZ (32768 * 512)
267 #define FREQ_32000HZ (32000 * 512)
268 #define PLL_REF_CLK FREQ_26MHZ
278 #define ESDCTL_ESDCTL0 0x00
279 #define ESDCTL_ESDCFG0 0x04
280 #define ESDCTL_ESDCTL1 0x08
281 #define ESDCTL_ESDCFG1 0x0C
282 #define ESDCTL_ESDMISC 0x10
283 #define ESDCTL_ESDSCR 0x14
284 #define ESDCTL_ESDCDLY1 0x20
285 #define ESDCTL_ESDCDLY2 0x24
286 #define ESDCTL_ESDCDLY3 0x28
287 #define ESDCTL_ESDCDLY4 0x2C
288 #define ESDCTL_ESDCDLY5 0x30
289 #define ESDCTL_ESDCDLYGD 0x34
292 #define PLL_DP_CTL 0x00
293 #define PLL_DP_CONFIG 0x04
294 #define PLL_DP_OP 0x08
295 #define PLL_DP_MFD 0x0C
296 #define PLL_DP_MFN 0x10
297 #define PLL_DP_MFNMINUS 0x14
298 #define PLL_DP_MFNPLUS 0x18
299 #define PLL_DP_HFS_OP 0x1C
300 #define PLL_DP_HFS_MFD 0x20
301 #define PLL_DP_HFS_MFN 0x24
302 #define PLL_DP_TOGC 0x28
303 #define PLL_DP_DESTAT 0x2C
318 #define CHIP_REV_1_0 0x10 /* PASS 1.0 */
319 #define CHIP_REV_1_1 0x11 /* PASS 1.0 */
320 #define CHIP_REV_1_2 0x12 /* PASS 1.2 */
321 #define CHIP_REV_2_0 0x20 /* PASS 2.0 */
322 #define CHIP_REV_2_1 0x21 /* PASS 2.1 */
323 #define CHIP_LATEST CHIP_REV_1_0
325 #define IIM_STAT_OFF 0x00
326 #define IIM_STAT_BUSY (1 << 7)
327 #define IIM_STAT_PRGD (1 << 1)
328 #define IIM_STAT_SNSD (1 << 0)
329 #define IIM_STATM_OFF 0x04
330 #define IIM_ERR_OFF 0x08
331 #define IIM_ERR_PRGE (1 << 7)
332 #define IIM_ERR_WPE (1 << 6)
333 #define IIM_ERR_OPE (1 << 5)
334 #define IIM_ERR_RPE (1 << 4)
335 #define IIM_ERR_WLRE (1 << 3)
336 #define IIM_ERR_SNSE (1 << 2)
337 #define IIM_ERR_PARITYE (1 << 1)
338 #define IIM_EMASK_OFF 0x0C
339 #define IIM_FCTL_OFF 0x10
340 #define IIM_UA_OFF 0x14
341 #define IIM_LA_OFF 0x18
342 #define IIM_SDAT_OFF 0x1C
343 #define IIM_PREV_OFF 0x20
344 #define IIM_SREV_OFF 0x24
345 #define IIM_PREG_P_OFF 0x28
346 #define IIM_SCS0_OFF 0x2C
347 #define IIM_SCS1_P_OFF 0x30
348 #define IIM_SCS2_OFF 0x34
349 #define IIM_SCS3_P_OFF 0x38
350 #define IIM_HAB0 0x810
352 #define FREQ_CKIH_26M 26000000
354 #define EPIT_BASE_ADDR EPIT1_BASE_ADDR
358 #define EPITCMPR 0x0C
361 #define NFC_BASE 0xBFFF0000
362 #define NAND_REG_BASE (NFC_BASE + 0xE00)
363 #define NAND_ADD_CMD_REG (NAND_REG_BASE + 0x00)
364 #define NAND_CONFIGURATION1_REG (NAND_REG_BASE + 0x04)
365 #define NAND_ECC_STATUS_RESULT_REG (NAND_REG_BASE + 0x08)
366 #define NAND_LAUNCH_REG (NAND_REG_BASE + 0x0C)
368 #define NAND_LAUNCH_FCMD (1 << 0)
369 #define NAND_LAUNCH_FADD (1 << 1)
370 #define NAND_LAUNCH_FDI (1 << 2)
372 #define NAND_CONFIGURATION1_NFC_RST (1 << 2)
373 #define NAND_CONFIGURATION1_NF_CE (1 << 1)
374 #define NAND_CONFIGURATION1_SP_EN (1 << 0)
376 #define NFC_WR_PROT_REG (NFC_IP_BASE + 0x00)
377 #define UNLOCK_BLK_ADD0_REG (NFC_IP_BASE + 0x04)
378 #define UNLOCK_BLK_ADD1_REG (NFC_IP_BASE + 0x08)
379 #define UNLOCK_BLK_ADD2_REG (NFC_IP_BASE + 0x0C)
380 #define UNLOCK_BLK_ADD3_REG (NFC_IP_BASE + 0x10)
381 #define NFC_FLASH_CONFIG2_REG (NFC_IP_BASE + 0x14)
382 #define NFC_IPC_REG (NFC_IP_BASE + 0x18)
383 #define NFC_AXI_ERR_ADD_REG (NFC_IP_BASE + 0x1C)
384 #define NFC_IPC_INT (1 << 31)
385 #define NFC_IPC_LPS (1 << 30)
386 #define NFC_IPC_RB_B (1 << 29)
387 #define NFC_IPC_CACK (1 << 1)
388 #define NFC_IPC_CREQ (1 << 0)
389 #define NFC_WR_PROTECT_CS0 (0 << 20)
390 #define NFC_WR_PROTECT_BLS_UNLOCK (2 << 16)
391 #define NFC_WR_PROTECT_WPC (4 << 0)
393 #define NFC_FLASH_CONFIG2_EDC0 (0 << 9)
394 #define NFC_FLASH_CONFIG2_EDC1 (1 << 9)
395 #define NFC_FLASH_CONFIG2_EDC2 (2 << 9)
396 #define NFC_FLASH_CONFIG2_EDC3 (3 << 9)
397 #define NFC_FLASH_CONFIG2_EDC4 (4 << 9)
398 #define NFC_FLASH_CONFIG2_EDC5 (5 << 9)
399 #define NFC_FLASH_CONFIG2_EDC6 (6 << 9)
400 #define NFC_FLASH_CONFIG2_EDC7 (7 << 9)
401 #define NFC_FLASH_CONFIG2_PPB_32 (0 << 7)
402 #define NFC_FLASH_CONFIG2_PPB_64 (1 << 7)
403 #define NFC_FLASH_CONFIG2_PPB_128 (2 << 7)
404 #define NFC_FLASH_CONFIG2_PPB_256 (3 << 7)
405 #define NFC_FLASH_CONFIG2_INT_MSK (1 << 4)
406 #define NFC_FLASH_CONFIG2_ECC_EN (1 << 3)
407 #define NFC_FLASH_CONFIG2_SYM (1 << 2)
408 #define NFC_FLASH_CONFIG2_DLP_DISABLE (0 << 0)
410 #define RAM_BUFFER_ADDRESS_RBA_3 0x3
411 #define NFC_BUFSIZE_1KB 0x0
412 #define NFC_BUFSIZE_2KB 0x1
413 #define NFC_CONFIGURATION_UNLOCKED 0x2
414 #define ECC_STATUS_RESULT_NO_ERR 0x0
415 #define ECC_STATUS_RESULT_1BIT_ERR 0x1
416 #define ECC_STATUS_RESULT_2BIT_ERR 0x2
417 #define NF_WR_PROT_UNLOCK 0x4
418 #define NAND_FLASH_CONFIG1_FORCE_CE (1 << 7)
419 #define NAND_FLASH_CONFIG1_RST (1 << 6)
420 #define NAND_FLASH_CONFIG1_BIG (1 << 5)
421 #define NAND_FLASH_CONFIG1_INT_MSK (1 << 4)
422 #define NAND_FLASH_CONFIG1_ECC_EN (1 << 3)
423 #define NAND_FLASH_CONFIG1_SP_EN (1 << 2)
425 #define MXC_NAND_BASE_DUMMY 0x00000000
426 #define NOR_FLASH_BOOT 0
427 #define NAND_FLASH_BOOT 0x10000000
428 #define SDRAM_NON_FLASH_BOOT 0x20000000
429 #define MXCBOOT_FLAG_REG (AVIC_BASE_ADDR + 0x100)
430 #define MXCFIS_NOTHING 0x00000000
431 #define MXCFIS_NAND 0x10000000
432 #define MXCFIS_NOR 0x20000000
433 #define MXCFIS_FLAG_REG (AVIC_BASE_ADDR + 0x104)
435 #define IS_BOOTING_FROM_NAND() (readl(MXCBOOT_FLAG_REG) == NAND_FLASH_BOOT)
436 #define IS_BOOTING_FROM_NOR() (readl(MXCBOOT_FLAG_REG) == NOR_FLASH_BOOT)
437 #define IS_BOOTING_FROM_SDRAM() (readl(MXCBOOT_FLAG_REG) == SDRAM_NON_FLASH_BOOT)
439 #ifndef MXCFLASH_SELECT_NAND
440 #define IS_FIS_FROM_NAND() 0
442 #define IS_FIS_FROM_NAND() (readl(MXCFIS_FLAG_REG) == MXCFIS_NAND)
445 #ifndef MXCFLASH_SELECT_NOR
446 #define IS_FIS_FROM_NOR() 0
448 #define IS_FIS_FROM_NOR() (!IS_FIS_FROM_NAND())
451 #define MXC_ASSERT_NOR_BOOT() writel(MXCFIS_NOR, MXCFIS_FLAG_REG)
452 #define MXC_ASSERT_NAND_BOOT() writel(MXCFIS_NAND, MXCFIS_FLAG_REG)
454 // MXC30031ADS board NAND boot is different from "normal" case. Instead of
455 // jumping directly to starting NAND base, it loads the value at 0x400 of
456 // the beginning of NAND and jumps to there.
457 #define MXC_NAND_BOOT_LOAD_AT_0x400
459 * This macro is used to get certain bit field from a number
461 #define MXC_GET_FIELD(val, len, sh) ((val >> sh) & ((1 << len) - 1))
464 * This macro is used to set certain bit field inside a number
466 #define MXC_SET_FIELD(val, len, sh, nval) ((val & ~(((1 << len) - 1) << sh)) | (nval << sh))
468 #define UART_WIDTH_32 /* internal UART is 32bit access only */
472 #if !defined(__ASSEMBLER__)
473 void cyg_hal_plf_serial_init(void);
474 void cyg_hal_plf_serial_stop(void);
475 void hal_delay_us(unsigned int usecs);
476 #define HAL_DELAY_US(n) hal_delay_us(n)
500 SPI1_CLK = CSPI1_BASE_ADDR,
503 unsigned int pll_clock(enum plls pll);
505 unsigned int get_main_clock(enum main_clocks clk);
507 unsigned int get_peri_clock(enum peri_clocks clk);
514 typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int);
516 #endif //#if !defined(__ASSEMBLER__)
518 #define HAL_MMU_OFF() \
521 "mcr p15, 0, r0, c7, c14, 0;" \
522 "mcr p15, 0, r0, c7, c10, 4;" /* drain the write buffer */ \
523 "mcr p15, 0, r0, c7, c5, 0;" /* invalidate I cache */ \
524 "mrc p15, 0, r0, c1, c0, 0;" /* read c1 */ \
525 "bic r0, r0, #0x7;" /* disable DCache and MMU */ \
526 "bic r0, r0, #0x1000;" /* disable ICache */ \
527 "mcr p15, 0, r0, c1, c0, 0;" /* */ \
528 "nop;" /* flush i+d-TLBs */ \
529 "nop;" /* flush i+d-TLBs */ \
530 "nop;" /* flush i+d-TLBs */ \
531 "nop;" /* flush i+d-TLBs */ \
532 "nop;" /* flush i+d-TLBs */ \
533 "nop;" /* flush i+d-TLBs */ \
534 "nop;" /* flush i+d-TLBs */ \
535 "nop;" /* flush i+d-TLBs */ \
536 "nop;" /* flush i+d-TLBs */ \
539 : "r0","memory" /* clobber list */); \
542 #endif // __HAL_SOC_H__