1 //==========================================================================
5 // HAL misc board support code for StrongARM SA1110/Brutus
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
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13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
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19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
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30 // License. However the source code for this file must still be made available
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37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
45 // Travis C. Furrer <furrer@mit.edu>
47 // Purpose: HAL board support
48 // Description: Implementations of HAL board interfaces
50 //####DESCRIPTIONEND####
52 //========================================================================*/
54 #include <pkgconf/hal.h>
55 #include <pkgconf/system.h>
56 #include CYGBLD_HAL_PLATFORM_H
58 #include <cyg/infra/cyg_type.h> // base types
59 #include <cyg/infra/cyg_trac.h> // tracing macros
60 #include <cyg/infra/cyg_ass.h> // assertion macros
62 #include <cyg/hal/hal_io.h> // IO macros
63 #include <cyg/hal/hal_arch.h> // Register state info
64 #include <cyg/hal/hal_diag.h>
65 #include <cyg/hal/hal_intr.h> // Interrupt names
66 #include <cyg/hal/hal_cache.h>
67 #include <cyg/hal/hal_sa11x0.h> // Hardware definitions
68 #include <cyg/hal/brutus.h> // Platform specifics
70 #include <cyg/infra/diag.h> // diag_printf
72 // All the MM table layout is here:
73 #include <cyg/hal/hal_mm.h>
75 #include <string.h> // memset
80 unsigned long ttb_base = SA11X0_RAM_BANK0_BASE + 0x4000;
84 * Set the TTB register
86 asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
89 * Set the Domain Access Control Register
91 i = ARM_ACCESS_DACR_DEFAULT;
92 asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
95 * First clear all TT entries - ie Set them to Faulting
97 memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
99 /* Actual Virtual Size Attributes Function */
100 /* Base Base MB cached? buffered? access permissions */
101 /* xxx00000 xxx00000 */
102 X_ARM_MMU_SECTION(0x000, 0x400, 1, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Boot flash ROMspace */
103 X_ARM_MMU_SECTION(0x080, 0x080, 4, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Application flash ROM */
104 X_ARM_MMU_SECTION(0x100, 0x100, 1, ARM_CACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Static RAM - 512K */
105 X_ARM_MMU_SECTION(0x180, 0x180, 1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Static select 3 */
106 X_ARM_MMU_SECTION(0x200, 0x200, 256, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* PCMCIA Socket 0 */
107 X_ARM_MMU_SECTION(0x300, 0x300, 256, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* PCMCIA Sockets 1 */
108 X_ARM_MMU_SECTION(0x800, 0x800, 0x400, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* StrongARM(R) Registers */
109 X_ARM_MMU_SECTION(0xC00, 0x000, 4, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* DRAM Bank 0 */
110 X_ARM_MMU_SECTION(0xC80, 0x004, 4, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* DRAM Bank 1 */
111 X_ARM_MMU_SECTION(0xD00, 0x008, 4, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* DRAM Bank 2 */
112 X_ARM_MMU_SECTION(0xD80, 0x00C, 4, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* DRAM Bank 3 */
113 X_ARM_MMU_SECTION(0xC00, 0xC00, 256, ARM_UNCACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* DRAM Banks - raw access */
114 X_ARM_MMU_SECTION(0xE00, 0xE00, 128, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Zeros (Cache Clean) Bank */
119 // Platform specific initialization
123 plf_hardware_init(void)
127 #include CYGHWR_MEMORY_LAYOUT_H
128 typedef void code_fun(void);
129 void brutus_program_new_stack(void *func)
131 register CYG_ADDRESS stack_ptr asm("sp");
132 register CYG_ADDRESS old_stack asm("r4");
133 register code_fun *new_func asm("r0");
134 old_stack = stack_ptr;
135 stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
136 new_func = (code_fun*)func;
138 stack_ptr = old_stack;
142 // ------------------------------------------------------------------------