1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 /*=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Red Hat, Inc.
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41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //=============================================================================
44 //#####DESCRIPTIONBEGIN####
47 // Contributors: msalter
49 // Purpose: Intel XScale GRG specific support routines
51 // Usage: #include <cyg/hal/hal_platform_setup.h>
52 // Only used by "vectors.S"
54 //####DESCRIPTIONEND####
56 //===========================================================================*/
58 #include <pkgconf/system.h> // System-wide configuration info
59 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
60 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
61 #include <cyg/hal/hal_ixp425.h> // Variant specific hardware definitions
62 #include <cyg/hal/hal_mmu.h> // MMU definitions
63 #include <cyg/hal/hal_mm.h> // more MMU definitions
64 #include <cyg/hal/grg.h> // Platform specific hardware definitions
66 // ------------------------------------------------------------------------
67 // Convenience macros for setting up page table
69 .macro IXP_MAP_SDRAM va, c, b, x, p
70 XSCALE_MMU_SECTION SDRAM_PHYS_BASE>>20, \va>>20, SDRAM_SIZE>>20, \c, \b, 3, \x, \p
73 .macro IXP_MAP_EXP_V n, va, sz, c, b, x, p
74 XSCALE_MMU_SECTION (0x500 + ((IXP425_EXP_CS_SIZE * \n) >> 20)), \va>>20, \sz>>20, \c, \b, 3, \x, \p
77 .macro IXP_MAP_EXP n, sz, c, b, x, p
78 IXP_MAP_EXP_V \n, (0x50000000 + (IXP425_EXP_CS_SIZE * \n)), \sz, \c, \b, \x, \p
81 .macro IXP_MAP_IO addr, sz
82 XSCALE_MMU_SECTION \addr>>20, \addr>>20, \sz>>20, 0, 0, 3, 0, 0
85 #if defined(CYG_HAL_STARTUP_ROM)
86 #define PLATFORM_SETUP1 _platform_setup1
87 #define CYGHWR_HAL_ARM_HAS_MMU
89 // ------------------------------------------------------------------------
90 // Define macro used to diddle the LEDs during early initialization.
91 // Can use r0+r1. Argument in \x.
92 #define CYGHWR_LED_MACRO
95 .macro DELAY cycles, reg0
103 // ------------------------------------------------------------------------
104 // This macro represents the initial startup code for the platform
105 .macro _platform_setup1
107 #ifdef CYGHWR_HAL_ARM_BIGENDIAN
109 mrc p15, 0, r0, c1, c0, 0
111 mcr p15, 0, r0, c1, c0, 0
115 ldr r0,=(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE)
118 // invalidate I & D caches & BTB
119 mcr p15, 0, r0, c7, c7, 0
122 // invalidate I & Data TLB
123 mcr p15, 0, r0, c8, c7, 0
126 // drain write and fill buffers
127 mcr p15, 0, r0, c7, c10, 4
130 // disable write buffer coalescing
131 mrc p15, 0, r0, c1, c0, 1
133 mcr p15, 0, r0, c1, c0, 1
136 // Setup chip selects
137 ldr r1, =IXP425_EXP_CFG_BASE
138 #ifdef IXP425_EXP_CS0_INIT
139 ldr r0, =IXP425_EXP_CS0_INIT
140 str r0, [r1, #IXP425_EXP_CS0]
142 #ifdef IXP425_EXP_CS1_INIT
143 ldr r0, =IXP425_EXP_CS1_INIT
144 str r0, [r1, #IXP425_EXP_CS1]
146 #ifdef IXP425_EXP_CS2_INIT
147 ldr r0, =IXP425_EXP_CS2_INIT
148 str r0, [r1, #IXP425_EXP_CS2]
150 #ifdef IXP425_EXP_CS3_INIT
151 ldr r0, =IXP425_EXP_CS3_INIT
152 str r0, [r1, #IXP425_EXP_CS3]
154 #ifdef IXP425_EXP_CS4_INIT
155 ldr r0, =IXP425_EXP_CS4_INIT
156 str r0, [r1, #IXP425_EXP_CS4]
158 #ifdef IXP425_EXP_CS5_INIT
159 ldr r0, =IXP425_EXP_CS5_INIT
160 str r0, [r1, #IXP425_EXP_CS5]
162 #ifdef IXP425_EXP_CS6_INIT
163 ldr r0, =IXP425_EXP_CS6_INIT
164 str r0, [r1, #IXP425_EXP_CS6]
166 #ifdef IXP425_EXP_CS7_INIT
167 ldr r0, =IXP425_EXP_CS7_INIT
168 str r0, [r1, #IXP425_EXP_CS7]
172 mrc p15, 0, r0, c1, c0, 0
173 orr r0, r0, #MMU_Control_I
174 mcr p15, 0, r0, c1, c0, 0
177 // Setup SDRAM controller
179 ldr r0, =IXP425_SDRAM_CFG_BASE
181 ldr r1, =IXP425_SDRAM_CONFIG_INIT
182 str r1, [r0, #IXP425_SDRAM_CONFIG]
184 // disable refresh cycles
186 str r1, [r0, #IXP425_SDRAM_REFRESH]
189 mov r1, #SDRAM_IR_NOP
190 str r1, [r0, #IXP425_SDRAM_IR]
193 // set SDRAM internal refresh val
194 ldr r1, =IXP425_SDRAM_REFRESH_CNT
195 str r1, [r0, #IXP425_SDRAM_REFRESH]
198 // send precharge-all command to close all open banks
199 mov r1, #SDRAM_IR_PRECHARGE
200 str r1, [r0, #IXP425_SDRAM_IR]
203 // provide 8 auto-refresh cycles
204 mov r1, #SDRAM_IR_AUTO_REFRESH
207 str r1, [r0, #IXP425_SDRAM_IR]
212 // set mode register in sdram
213 mov r1, #IXP425_SDRAM_SET_MODE_CMD
214 str r1, [r0, #IXP425_SDRAM_IR]
217 // start normal operation
218 mov r1, #SDRAM_IR_NORMAL
219 str r1, [r0, #IXP425_SDRAM_IR]
222 // Enable byte swapping control via page table P bit.
223 ldr r2, =IXP425_EXP_CFG_BASE
224 ldr r1, [r2, #IXP425_EXP_CNFG1]
225 orr r1, r1, #EXP_CNFG1_BYTE_SWAP_EN
226 str r1, [r2, #IXP425_EXP_CNFG1]
228 // value to load into pc to jump to real runtime address
231 // Setup EXP_CNFG0 value to switch EXP bus out of low memory
232 ldr r2, =IXP425_EXP_CFG_BASE
233 ldr r1, [r2, #IXP425_EXP_CNFG0]
234 bic r1, r1, #EXP_CNFG0_MEM_MAP
239 // Here is where we switch from boot address (0x000000000) to the
240 // actual flash runtime address. We align to cache boundary so we
241 // execute from cache during the switchover. Cachelines are 8 words.
242 str r1, [r2, #IXP425_EXP_CNFG0] // make the EXP bus switch
249 // display FFFF and loop forever.
253 // Build mmu tables into RAM so page table walks by the cpu
254 // don't interfere with FLASH programming.
255 mov r1, #SDRAM_PHYS_BASE
256 orr r1, r1, #0x4000 // RAM tables
257 add r2, r1, #0x4000 // End of tables
266 // Build section mappings
267 IXP_MAP_SDRAM SDRAM_BASE, 1, 0, 0, 0 // Cached SDRAM
268 IXP_MAP_SDRAM SDRAM_ALIAS_BASE, 1, 0, 0, 0 // Cached SDRAM alias
269 IXP_MAP_SDRAM SDRAM_UNCACHED_BASE, 0, 0, 0, 0 // Uncached SDRAM
270 IXP_MAP_SDRAM SDRAM_DC_BASE, 1, 0, 0, 1 // Cached data coherent SDRAM
272 IXP_MAP_EXP 0, IXDP_FLASH_SIZE, 1, 0, 0, 0 // Flash
273 IXP_MAP_EXP 4, (1 << 20), 0, 0, 0, 0 // NPE use
274 IXP_MAP_EXP 5, (1 << 20), 0, 0, 0, 0 // NPE use
276 IXP_MAP_EXP_V 0, IXDP_FLASH_DC_BASE, IXDP_FLASH_SIZE, 1, 0, 0, 1 // data coherent flash
278 IXP_MAP_IO IXP425_PCI_WINDOW_BASE, IXP425_PCI_WINDOW_SIZE
279 IXP_MAP_IO IXP425_QMGR_BASE, IXP425_QMGR_SIZE
280 IXP_MAP_IO IXP425_PCI_CFG_BASE, IXP425_PCI_CFG_SIZE
281 IXP_MAP_IO IXP425_EXP_CFG_BASE, IXP425_EXP_CFG_SIZE
282 IXP_MAP_IO IXP425_MISC_CFG_BASE, IXP425_MISC_CFG_SIZE
283 IXP_MAP_IO IXP425_SDRAM_CFG_BASE, IXP425_SDRAM_CFG_SIZE
285 mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers
288 // Set the TTB register to DRAM mmu_table
289 ldr r0, =(SDRAM_PHYS_BASE | 0x4000) // RAM tables
290 mcr p15, 0, r0, c2, c0, 0 // load page table pointer
293 // enable permission checks in all domains
295 mcr p15, 0, r0, c3, c0, 0
299 mrc p15, 0, r0, c1, c0, 0
300 orr r0, r0, #MMU_Control_M
301 orr r0, r0, #MMU_Control_R
302 mcr p15, 0, r0, c1, c0, 0
306 mrc p15, 0, r0, c1, c0, 0
307 orr r0, r0, #MMU_Control_C
308 mcr p15, 0, r0, c1, c0, 0
311 // Enable branch target buffer
312 mrc p15, 0, r0, c1, c0, 0
313 orr r0, r0, #MMU_Control_BTB
314 mcr p15, 0, r0, c1, c0, 0
317 mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers
320 mcr p15, 0, r0, c7, c7, 0 // flush Icache, Dcache and BTB
323 mcr p15, 0, r0, c8, c7, 0 // flush instuction and data TLBs
326 mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers
330 ldr r1, =hal_dram_size /* [see hal_intr.h] */
334 .endm // _platform_setup1
336 #else // defined(CYG_HAL_STARTUP_ROM)
337 #define PLATFORM_SETUP1
340 #define PLATFORM_VECTORS _platform_vectors
341 .macro _platform_vectors
344 /*---------------------------------------------------------------------------*/
345 /* end of hal_platform_setup.h */
346 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */