1 //=============================================================================
3 // interrupts.c - Cyclone Diagnostics
5 //=============================================================================
6 //####ECOSGPLCOPYRIGHTBEGIN####
7 // -------------------------------------------
8 // This file is part of eCos, the Embedded Configurable Operating System.
9 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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22 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
24 // As a special exception, if other files instantiate templates or use macros
25 // or inline functions from this file, or you compile this file and link it
26 // with other works to produce a work based on this file, this file does not
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35 // at http://sources.redhat.com/ecos/ecos-license/
36 // -------------------------------------------
37 //####ECOSGPLCOPYRIGHTEND####
38 //=============================================================================
39 //#####DESCRIPTIONBEGIN####
41 // Author(s): Scott Coulter, Jeff Frazier, Eric Breeden
47 //####DESCRIPTIONEND####
49 //===========================================================================*/
51 /******************************************************************************/
52 /* interrupts.c - Interrupt dispatcher routines for IQ80310 Board */
54 /* modification history */
55 /* -------------------- */
56 /* 07sep00, ejb, Written for IQ80310 Cygmon diagnostics */
57 /* 11oct00, ejb, Switched FIQ and IRQ interrupt handlers */
58 /* 18dec00 snc and jwf */
59 /* 02feb01 jwf for snc */
60 /******************************************************************************/
64 #include "7_segment_displays.h"
66 extern int(*board_fiq_handler)(void);
67 extern int(*board_irq_handler)(void);
68 extern long _cspr_enable_fiq_int(void);
69 extern long _cspr_enable_irq_int(void);
70 extern long _read_cpsr(void);
71 extern long _scrub_ecc(unsigned);
72 extern void _flushICache(void);
75 #define AND_WORD(addr,val) *addr = *addr & val
78 void error_print(char *fmt, int arg0, int arg1, int arg2, int arg3);
81 extern int nmi_verbose; /* for NMI, only print NMI info if this is TRUE */
82 extern int pci_config_cycle; /* don't handle NMI if in a config cycle */
83 extern int pci_config_error;
93 extern UINT secondary_busno;
94 extern UINT primary_busno;
96 extern STATUS pci_to_xint(int device, int intpin, int *xint);
97 extern int isHost(void);
98 extern int off_ppci_bus (int busno);
100 #define MAX_SPURIOUS_CNT 5
101 #define NUM_PCI_XINTS 4 /* SINTA - SINTD */
102 #define MAX_PCI_HANDLERS 8 /* maximum handlers per PCI Xint */
105 int ecc_error_reported = FALSE;
107 static int isr_xint0_spurious = 0;
108 static int isr_xint1_spurious = 0;
109 static int isr_xint2_spurious = 0;
110 static int isr_xint3_spurious = 0;
112 /* Table where the interrupt handler addresses are stored. */
113 INT_HANDLER pci_int_handlers[4][MAX_PCI_HANDLERS];
115 /* Other User Interrupt Service Routines */
117 void (*usr_timer_isr)(int) = NULL;
118 int usr_timer_arg = 0;
119 void (*usr_enet_isr)(int) = NULL;
120 int usr_enet_arg = 0;
121 void (*usr_uart1_isr)(int) = NULL;
122 int usr_uart1_arg = 0;
123 void (*usr_uart2_isr)(int) = NULL;
124 int usr_uart2_arg = 0;
125 void (*usr_dma0_isr)(int) = NULL;
126 int usr_dma0_arg = 0;
127 void (*usr_dma1_isr)(int) = NULL;
128 int usr_dma1_arg = 0;
129 void (*usr_dma2_isr)(int) = NULL;
130 int usr_dma2_arg = 0;
131 void (*usr_pm_isr)(int) = NULL;
133 void (*usr_aa_isr)(int) = NULL;
135 void (*usr_i2c_isr)(int) = NULL;
137 void (*usr_mu_isr)(int) = NULL;
139 void (*usr_patu_isr)(int) = NULL;
140 int usr_patu_arg = 0;
142 int ecc_int_handler(void);
146 /*********************************
147 * PCI interrupt wrappers
149 int sinta_handler(void)
152 /* cycle through connected interrupt handlers to determine which caused int */
153 for (x = 0; x < MAX_PCI_HANDLERS; x++)
155 if (pci_int_handlers[0][x].handler != NULL) /* Is a routine installed */
156 if ((*pci_int_handlers[0][x].handler)(pci_int_handlers[0][x].arg) == 1)
164 isr_xint0_spurious++;
166 if (isr_xint0_spurious > MAX_SPURIOUS_CNT)
170 isr_xint0_spurious = 0;
176 int sintb_handler(void)
180 /* cycle through connected interrupt handlers to determine which caused int */
181 for (x = 0; x < MAX_PCI_HANDLERS; x++)
183 if (pci_int_handlers[1][x].handler != NULL) /* Is a routine installed */
184 if ((*pci_int_handlers[1][x].handler)(pci_int_handlers[1][x].arg) == 1)
192 isr_xint1_spurious++;
194 if (isr_xint1_spurious > MAX_SPURIOUS_CNT)
198 isr_xint1_spurious = 0;
204 int sintc_handler(void)
209 /* cycle through connected interrupt handlers to determine which caused int */
210 for (x = 0; x < MAX_PCI_HANDLERS; x++)
212 if (pci_int_handlers[2][x].handler != NULL) /* Is a routine installed */
213 if ((*pci_int_handlers[2][x].handler)(pci_int_handlers[2][x].arg) == 1)
221 isr_xint2_spurious++;
223 if (isr_xint2_spurious > MAX_SPURIOUS_CNT)
227 isr_xint2_spurious = 0;
233 int sintd_handler(void)
238 /* cycle through connected interrupt handlers to determine which caused int */
239 for (x = 0; x < MAX_PCI_HANDLERS; x++)
241 if (pci_int_handlers[3][x].handler != NULL) /* Is a routine installed */
242 if ((*pci_int_handlers[3][x].handler)(pci_int_handlers[3][x].arg) == 1)
250 isr_xint3_spurious++;
252 if (isr_xint3_spurious > MAX_SPURIOUS_CNT)
256 isr_xint3_spurious = 0;
264 /******************************************************************************
266 * Installs an interrupt handler in the PCI dispatch table, to be called
267 * by the appropriate PCI isr (above) when an interrupt occurs.
269 * Note: the intline parameter refers to which PCI interrupt INT A - INT D
271 * device identifies the PCI device number
273 * Note: isrs connected with this function must return 1 if an interrupt is
274 * serviced in order to support the PCI interrupt sharing mechanism
277 STATUS pci_isr_connect (int intline, int bus, int device, int (*handler)(int), int arg)
282 /* check to see if we are attempting to connect to a PPCI interrupt and we are not
284 if ((isHost() == FALSE) && (off_ppci_bus(bus) == TRUE))
287 if ((intline < INTA) || (intline > INTD))
290 (void)pci_to_xint(device, intline, &which_xint);
292 for (handler_index = 0; handler_index < MAX_PCI_HANDLERS; handler_index++)
294 if (pci_int_handlers[which_xint][handler_index].handler == NULL)
296 pci_int_handlers[which_xint][handler_index].handler = handler;
297 pci_int_handlers[which_xint][handler_index].arg = arg;
298 pci_int_handlers[which_xint][handler_index].bus = bus;
299 pci_int_handlers[which_xint][handler_index].device = device;
304 /* if there is no more room in the table return an error */
305 if (handler_index == MAX_PCI_HANDLERS)
312 /******************************************************************************
314 * Uninstalls an interrupt handler in the PCI dispatch table
316 * Note: the intline parameter refers to which PCI interrupt INTA - INTD
318 * the device parameter refers to which SPCI device number is sourcing the
322 STATUS pci_isr_disconnect (int intline, int bus, int device)
327 /* check to see if we are attempting to disconnect a PPCI interrupt and we are not
329 if ((isHost() == FALSE) && (off_ppci_bus(bus) == TRUE))
332 if ((intline < INTA) || (intline > INTD))
335 (void)pci_to_xint(device, intline, &which_xint);
337 for (handler_index = 0; handler_index < MAX_PCI_HANDLERS; handler_index++)
339 if ((pci_int_handlers[which_xint][handler_index].bus == bus) &&
340 (pci_int_handlers[which_xint][handler_index].device == device))
342 pci_int_handlers[which_xint][handler_index].handler = NULL;
343 pci_int_handlers[which_xint][handler_index].arg = (int)NULL;
344 pci_int_handlers[which_xint][handler_index].bus = (int)NULL;
345 pci_int_handlers[which_xint][handler_index].device = (int)NULL;
349 /* if the handler was not found in the table return an error */
350 if (handler_index == MAX_PCI_HANDLERS)
357 /**********************************************************************************
358 * iq80310_irq_handler - Interrupt dispatcher for IQ80310 IRQ Interrupts
360 * This function determines the source of the IRQ Interrupt, and calls the
361 * corresponding interrupt service routine. If multiple sources are interrupting
362 * the dispatcher will call all interrupt handles. Users must clear the interrupt
363 * within the interrupt service routine before exiting.
365 * IRQ Interrupts are multiplexed from SPCI INTA - INTD, External Device Interrupts,
366 * and XINT6 and XINT7 Internal device interrupts.
368 int iq80310_irq_handler(void)
370 UINT8* int_status_reg;
376 unsigned char ri_state;
377 unsigned char board_rev;
378 unsigned char sint_status; /* holds interrupt status for SINTA-SINTC */
379 ri_state = *( unsigned char * ) 0xfe810006; /* access uart u2 msr reg at addr fe810006 */
381 if(ri_state == RI_MASK) /* RI# pin on UART2 is grounded */
383 board_rev = *BOARD_REV_REG_ADDR; /* read Board Revision register */
384 board_rev &= BOARD_REV_MASK; /* isolate LSN */
385 if (board_rev >= BOARD_REV_E) /* Board Rev is at E or higher */
387 sint_status = *SINT_REG_ADDR; /* read current secondary pci interrupt status */
388 sint_status &= SINT_MASK; /* isolate SINTA, SINTB, and SINTC */
392 num_sources += sinta_handler(); /* IRQ0 = SINTA? */
393 /* printf(" sinta status = %#x\n", sint_status); */
396 num_sources += sintb_handler(); /* IRQ1 = SINTB? */
397 /* printf(" sintb status = %#x\n", sint_status); */
400 num_sources += sintc_handler(); /* IRQ2 = SINTC? */
401 /* printf(" sintc status = %#x\n", sint_status); */
404 /* printf(" sint? status = %#x\n", sint_status); */
405 break; /* probably should test for more conditions: 011b, 101b, 110b, 111b */
409 else /* RI# pin on UART2 is pulled up to 3.3V. Cannot read board revision register, not implemented */
411 num_sources += sinta_handler(); /* IRQ0 = SINTA? */
412 num_sources += sintb_handler(); /* IRQ1 = SINTB? */
413 num_sources += sintc_handler(); /* IRQ2 = SINTC? */
419 /* No S_INTA - S_INTC status register, call handlers always */
420 /* This may change in next revision of board */
421 /*num_sources += sinta_handler();*/ /* IRQ0 = SINTA? */
422 /*num_sources += sintb_handler();*/ /* IRQ1 = SINTB? */
423 /*num_sources += sintc_handler();*/ /* IRQ2 = SINTC? */
426 /* Read IRQ3 Status Register, and if any of the multiple sources are
427 interrupting, call corresponding handler */
428 int_status_reg = (UINT8 *)X3ISR_ADDR;
429 int_status = *int_status_reg;
431 if (int_status & TIMER_INT) /* timer interrupt? */
433 /* call user ISR, if connected */
434 if (usr_timer_isr != NULL)
435 (*usr_timer_isr)(usr_timer_arg);
437 printf ("\nUnhandled Timer Interrupt Detected!\n");
442 if (int_status & ENET_INT) /* ethernet interrupt? */
444 /* call user ISR, if connected */
445 if (usr_enet_isr != NULL)
446 (*usr_enet_isr)(usr_enet_arg);
448 printf ("\nUnhandled Ethernet Interrupt Detected!\n");
453 if (int_status & UART1_INT) /* uart1 interrupt? */
455 /* call user ISR, if connected */
456 if (usr_uart1_isr != NULL)
457 (*usr_uart1_isr)(usr_uart1_arg);
459 printf ("\nUnhandled UART1 Interrupt Detected!\n");
464 if (int_status & UART2_INT) /* uart2 interrupt? */
466 /* call user ISR, if connected */
467 if (usr_uart2_isr != NULL)
468 (*usr_uart2_isr)(usr_uart2_arg);
470 printf ("\nUnhandled UART2 Interrupt Detected!\n");
474 if (int_status & SINTD_INT) /* SPCI_INTD? */
476 num_sources += sintd_handler();
481 /* Read XINT6 Status Register, and if any of the multiple sources are
482 interrupting, call corresponding handler */
483 int_status_reg = (UINT8 *)X6ISR_ADDR;
484 int_status = *int_status_reg;
486 if (int_status & DMA0_INT) /* dma0 interrupt? */
488 if (usr_dma0_isr != NULL)
489 (*usr_dma0_isr)(usr_dma0_arg);
491 printf ("\nUnhandled DMA Channel 0 Interrupt Detected!\n");
495 if (int_status & DMA1_INT) /* dma1 interrupt? */
497 if (usr_dma1_isr != NULL)
498 (*usr_dma1_isr)(usr_dma1_arg);
500 printf ("\nUnhandled DMA Channel 1 Interrupt Detected!\n");
504 if (int_status & DMA2_INT) /* dma2 interrupt? */
506 if (usr_dma2_isr != NULL)
507 (*usr_dma2_isr)(usr_dma2_arg);
509 printf ("\nUnhandled DMA Channel 2 Interrupt Detected!\n");
513 if (int_status & PM_INT) /* performance monitoring interrupt? */
515 if (usr_pm_isr != NULL)
516 (*usr_pm_isr)(usr_pm_arg);
518 printf ("\nUnhandled Performance Monitoring Unit Interrupt Detected!\n");
522 if (int_status & AA_INT) /* application accelerator interrupt? */
524 if (usr_aa_isr != NULL)
525 (*usr_aa_isr)(usr_aa_arg);
527 printf ("\nUnhandled Application Accelerating Unit Interrupt Detected!\n");
533 /* Read XINT7 Status Register, and if any of the multiple sources are
534 interrupting, call corresponding handler */
535 int_status_reg = (UINT8 *)X7ISR_ADDR;
536 int_status = *int_status_reg;
538 if (int_status & I2C_INT) /* i2c interrupt? */
540 if (usr_i2c_isr != NULL)
541 (*usr_i2c_isr)(usr_i2c_arg);
543 printf ("\nUnhandled I2C Unit Interrupt Detected!\n");
547 if (int_status & MU_INT) /* messaging unit interrupt? */
549 if (usr_mu_isr != NULL)
550 (*usr_mu_isr)(usr_mu_arg);
552 printf ("\nUnhandled Messaging Unit Interrupt Detected!\n");
556 if (int_status & PATU_INT) /* primary ATU / BIST start interrupt? */
558 if (usr_patu_isr != NULL)
559 (*usr_patu_isr)(usr_patu_arg);
561 printf ("\nUnhandled Primary ATU Interrupt Detected!\n");
566 /* return the number of interrupt sources found */
567 return (num_sources);
574 /****************************************************************
575 * nmi_ecc_isr - ECC NMI Interrupt Handler
577 * This module handles the NMI caused by an ECC error.
578 * For a Single-bit error it does a read-nodify-write
579 * to correct the error in memory. For a multi-bit or
580 * nibble error it does absolutely nothing.
582 void nmi_ecc_isr(void)
584 UINT32 eccr_register;
587 /* Read current state of ECC register */
588 eccr_register = *(UINT32 *)ECCR_ADDR;
590 /* Turn off all ecc error reporting */
591 *(UINT32 *)ECCR_ADDR = 0x4;
593 /* Check for ECC Error 0 */
594 if(*(UINT32 *)MCISR_ADDR & 0x1)
596 reg32 = (UINT32*)ELOG0_ADDR;
597 error_print("ELOG0 = 0x%X\n",*reg32,0,0,0);
599 reg32 = (UINT32*)ECAR0_ADDR;
600 error_print("ECC Error Detected at Address 0x%X\n",*reg32,0,0,0);
602 /* Check for single-bit error */
603 if(!(*(UINT32 *)ELOG0_ADDR & 0x00000100))
605 /* call ECC restoration function */
608 /* Clear the MCISR */
609 *(UINT32 *)MCISR_ADDR = 0x1;
612 error_print("Multi-bit or nibble error\n",0,0,0,0);
615 /* Check for ECC Error 1 */
616 if(*(UINT32 *)MCISR_ADDR & 0x2)
618 reg32 = (UINT32*)ELOG1_ADDR;
619 error_print("ELOG0 = 0x%X\n",*reg32,0,0,0);
621 reg32 = (UINT32*)ECAR1_ADDR;
622 error_print("ECC Error Detected at Address 0x%X\n",*reg32,0,0,0);
624 /* Check for single-bit error */
625 if(!(*(UINT32 *)ELOG1_ADDR & 0x00000100))
627 /* call ECC restoration function */
630 /* Clear the MCISR */
631 *(UINT32 *)MCISR_ADDR = 0x2;
634 error_print("Multi-bit or nibble error\n",0,0,0,0);
637 /* Check for ECC Error N */
638 if(*(UINT32 *)MCISR_ADDR & 0x4)
640 /* Clear the MCISR */
641 *(UINT32 *)MCISR_ADDR = 0x4;
642 error_print("Uncorrectable error during RMW\n",0,0,0,0);
645 /* Turn on ecc error reporting */
646 *(UINT32 *)ECCR_ADDR = eccr_register;
652 /******************************************************************************
653 * iq80310_fiq_handler - Interrupt dispatcher for IQ80310 FIQ Interrupts
657 int iq80310_fiq_handler(void)
660 unsigned long nmi_status = *(volatile unsigned long *)NISR_ADDR;
661 unsigned long status;
664 if (nmi_status & MCU_ERROR)
666 status = *(volatile unsigned long *)MCISR_ADDR;
667 *MSB_DISPLAY_REG = LETTER_E;
669 *LSB_DISPLAY_REG = ONE;
671 *LSB_DISPLAY_REG = TWO;
673 *LSB_DISPLAY_REG = FOUR;
676 error_print ("**** 80312 Memory Controller Error ****\n",0,0,0,0);
677 if (status & 0x001) error_print ("One ECC Error Detected and Recorded in ELOG0\n",0,0,0,0);
678 if (status & 0x002) error_print ("Second ECC Error Detected and Recorded in ELOG1\n",0,0,0,0);
679 if (status & 0x004) error_print ("Multiple ECC Errors Detected\n",0,0,0,0);
682 /* call ecc interrupt handler */
685 /* clear the interrupt condition*/
686 AND_WORD((volatile unsigned long *)MCISR_ADDR, 0x07);
689 ecc_error_reported = TRUE;
694 if (nmi_status & PATU_ERROR)
697 error_print ("**** Primary ATU Error ****\n",0,0,0,0);
698 status = *(volatile unsigned long *)PATUISR_ADDR;
699 if (status & 0x001) error_print ("PPCI Master Parity Error\n",0,0,0,0);
700 if (status & 0x002) error_print ("PPCI Target Abort (target)\n",0,0,0,0);
701 if (status & 0x004) error_print ("PPCI Target Abort (master)\n",0,0,0,0);
702 if (status & 0x008) error_print ("PPCI Master Abort\n",0,0,0,0);
703 if (status & 0x010) error_print ("Primary P_SERR# Detected\n",0,0,0,0);
704 if (status & 0x080) error_print ("Internal Bus Master Abort\n",0,0,0,0);
705 if (status & 0x100) error_print ("PATU BIST Interrupt\n",0,0,0,0);
706 if (status & 0x200) error_print ("PPCI Parity Error Detected\n",0,0,0,0);
707 if (status & 0x400) error_print ("Primary P_SERR# Asserted\n",0,0,0,0);
709 /* clear the interrupt conditions */
710 AND_WORD((volatile unsigned long *)PATUISR_ADDR, 0x79f);
713 /* tell the config cleanup code about error */
714 if (pci_config_cycle == 1)
715 pci_config_error = TRUE;
718 if (nmi_status & SATU_ERROR)
721 error_print ("**** Secondary ATU Error ****\n",0,0,0,0);
722 status = *(volatile unsigned long *)SATUISR_ADDR;
723 if (status & 0x001) error_print ("SPCI Master Parity Error\n",0,0,0,0);
724 if (status & 0x002) error_print ("SPCI Target Abort (target)\n",0,0,0,0);
725 if (status & 0x004) error_print ("SPCI Target Abort (master)\n",0,0,0,0);
726 if (status & 0x008) error_print ("SPCI Master Abort\n",0,0,0,0);
727 if (status & 0x010) error_print ("Secondary P_SERR# Detected\n",0,0,0,0);
728 if (status & 0x080) error_print ("Internal Bus Master Abort\n",0,0,0,0);
729 if (status & 0x200) error_print ("SPCI Parity Error Detected\n",0,0,0,0);
730 if (status & 0x400) error_print ("Secondary S_SERR# Asserted\n",0,0,0,0);
732 /* clear the interrupt conditions */
733 AND_WORD((volatile unsigned long *)SATUISR_ADDR, 0x69f);
736 /* tell the config cleanup code about error */
737 if (pci_config_cycle == 1)
738 pci_config_error = TRUE;
741 if (nmi_status & PBRIDGE_ERROR)
744 error_print ("**** Primary Bridge Error ****\n",0,0,0,0);
745 status = *(volatile unsigned long *)PBISR_ADDR;
746 if (status & 0x001) error_print ("PPCI Master Parity Error\n",0,0,0,0);
747 if (status & 0x002) error_print ("PPCI Target Abort (Target)\n",0,0,0,0);
748 if (status & 0x004) error_print ("PPCI Target Abort (Master)\n",0,0,0,0);
749 if (status & 0x008) error_print ("PPCI Master Abort\n",0,0,0,0);
750 if (status & 0x010) error_print ("Primary P_SERR# Asserted\n",0,0,0,0);
751 if (status & 0x020) error_print ("PPCI Parity Error Detected\n",0,0,0,0);
753 /* clear the interrupt condition */
754 AND_WORD((volatile unsigned long *)PBISR_ADDR, 0x3f);
755 CLEAR_PBRIDGE_STATUS();
757 /* tell the config cleanup code about error */
758 if (pci_config_cycle == 1)
759 pci_config_error = TRUE;
762 if (nmi_status & SBRIDGE_ERROR)
766 /* don't print configuration secondary bridge errors */
768 /* clear the interrupt condition */
769 AND_WORD((volatile unsigned long *)SBISR_ADDR, 0x7f);
770 CLEAR_SBRIDGE_STATUS();
772 /* tell the config cleanup code about error */
773 if (pci_config_cycle == 1)
774 pci_config_error = TRUE;
777 if (nmi_status & DMA_0_ERROR)
780 error_print ("**** DMA Channel 0 Error ****\n",0,0,0,0);
781 status = *(volatile unsigned long *)CSR0_ADDR;
782 if (status & 0x001) error_print ("DMA Channel 0 PCI Parity Error\n",0,0,0,0);
783 if (status & 0x004) error_print ("DMA Channel 0 PCI Target Abort\n",0,0,0,0);
784 if (status & 0x008) error_print ("DMA Channel 0 PCI Master Abort\n",0,0,0,0);
785 if (status & 0x020) error_print ("Internal PCI Master Abort\n",0,0,0,0);
786 /* clear the interrupt condition */
787 AND_WORD((volatile unsigned long *)CSR0_ADDR, 0x2D);
790 if (nmi_status & DMA_1_ERROR)
793 error_print ("**** DMA Channel 1 Error ****\n",0,0,0,0);
794 status = *(volatile unsigned long *)CSR1_ADDR;
795 if (status & 0x001) error_print ("DMA Channel 1 PCI Parity Error\n",0,0,0,0);
796 if (status & 0x004) error_print ("DMA Channel 1 PCI Target Abort\n",0,0,0,0);
797 if (status & 0x008) error_print ("DMA Channel 1 PCI Master Abort\n",0,0,0,0);
798 if (status & 0x020) error_print ("Internal PCI Master Abort\n",0,0,0,0);
800 /* clear the interrupt condition */
801 AND_WORD((volatile unsigned long *)CSR1_ADDR, 0x2D);
804 if (nmi_status & DMA_2_ERROR)
807 error_print ("**** DMA Channel 2 Error ****\n",0,0,0,0);
808 status = *(volatile unsigned long *)CSR2_ADDR;
809 if (status & 0x001) error_print ("DMA Channel 2 PCI Parity Error\n",0,0,0,0);
810 if (status & 0x004) error_print ("DMA Channel 2 PCI Target Abort\n",0,0,0,0);
811 if (status & 0x008) error_print ("DMA Channel 2 PCI Master Abort\n",0,0,0,0);
812 if (status & 0x020) error_print ("Internal PCI Master Abort\n",0,0,0,0);
814 /* clear the interrupt condition */
815 AND_WORD((volatile unsigned long *)CSR2_ADDR, 0x2D);
818 if (nmi_status & MU_ERROR)
820 status = *(volatile unsigned long *)IISR_ADDR;
824 error_print ("Messaging Unit Outbound Free Queue Overflow\n",0,0,0,0);
826 /* clear the interrupt condition; note that the clearing of the NMI doorbell
827 is handled by the PCI comms code */
828 } AND_WORD((volatile unsigned long *)IISR_ADDR, 0x20);
831 if (nmi_status & AAU_ERROR)
834 error_print ("**** Application Accelerator Unit Error ****\n",0,0,0,0);
835 status = *(volatile unsigned long *)ASR_ADDR;
836 if (status & 0x020) error_print ("Internal PCI Master Abort\n",0,0,0,0);
838 /* clear the interrupt condition */
839 AND_WORD((volatile unsigned long *)ASR_ADDR, 0x20);
842 if (nmi_status & BIU_ERROR)
845 error_print ("**** Bus Interface Unit Error ****\n",0,0,0,0);
846 status = *(volatile unsigned long *)BIUISR_ADDR;
847 if (status & 0x004) error_print ("Internal PCI Master Abort\n",0,0,0,0);
849 /* clear the interrupt condition */
850 AND_WORD((volatile unsigned long *)BIUISR_ADDR, 0x04);
858 /**********************************************************************
859 * isr_connect - Disconnect a user Interrupt Service Routine
861 * NOT TO BE USED FOR SPCI INTERRUPTS! - use pci_isr_connect instead
864 int isr_connect(int int_num, void (*handler)(int), int arg)
870 usr_dma0_isr = handler;
874 usr_dma1_isr = handler;
878 usr_dma2_isr = handler;
882 usr_pm_isr = handler;
886 usr_aa_isr = handler;
890 usr_i2c_isr = handler;
894 usr_mu_isr = handler;
898 usr_patu_isr = handler;
902 usr_timer_isr = handler;
906 usr_enet_isr = handler;
910 usr_uart1_isr = handler;
914 usr_uart2_isr = handler;
925 /**********************************************************************
926 * isr_disconnect - Disconnect a user Interrupt Service Routine
928 * NOT TO BE USED FOR SPCI INTERRUPTS! - use pci_isr_disconnect instead
931 int isr_disconnect(int int_num)
969 usr_timer_isr = NULL;
977 usr_uart1_isr = NULL;
981 usr_uart2_isr = NULL;
989 /* i960 disabled interrupt here - should we? */
994 /********************************************************************
995 * disable_external_interrupt - Mask an external interrupt
998 int disable_external_interrupt(int int_id)
1001 unsigned char* ext_mask_reg = (unsigned char*) X3MASK_ADDR;
1002 unsigned char new_mask_value;
1004 /* make sure interrupt to enable is an external interrupt */
1005 if ((int_id < TIMER_INT_ID) || (int_id > SINTD_INT_ID))
1008 new_mask_value = *ext_mask_reg; /* read current mask status */
1013 new_mask_value |= TIMER_INT;
1016 new_mask_value |= ENET_INT;
1019 new_mask_value |= UART1_INT;
1022 new_mask_value |= UART2_INT;
1025 new_mask_value |= SINTD_INT;
1028 break; /* leave mask register as it was */
1031 *ext_mask_reg = new_mask_value; /* set new mask value */
1039 /********************************************************************
1040 * enable_external_interrupt - Unmask an external interrupt
1043 int enable_external_interrupt(int int_id)
1046 unsigned char* ext_mask_reg = (unsigned char*) X3MASK_ADDR;
1047 unsigned char new_mask_value;
1049 /* make sure interrupt to enable is an external interrupt */
1050 if ((int_id < TIMER_INT_ID) || (int_id > SINTD_INT_ID))
1054 new_mask_value = *ext_mask_reg; /* read current mask status */
1059 new_mask_value &= ~(TIMER_INT);
1062 new_mask_value &= ~(ENET_INT);
1065 new_mask_value &= ~(UART1_INT);
1068 new_mask_value &= ~(UART2_INT);
1071 new_mask_value &= ~(SINTD_INT);
1074 break; /* leave mask register as it was */
1077 *ext_mask_reg = new_mask_value; /* set new mask value */
1091 /* Wait until host configures the boards to start printing NMI errors */
1092 UINT32* atu_reg = (UINT32*)PIABAR_ADDR;
1093 if ((*atu_reg & 0xfffffff0) == 0)
1095 if (nmi_verbose) printf (fmt, arg0, arg1, arg2, arg3);
1099 extern void __diag_IRQ(void);
1100 extern void __diag_FIQ(void);
1102 void config_ints(void)
1106 unsigned int* pirsr_ptr = (unsigned int*)PIRSR_ADDR;
1107 *pirsr_ptr = 0xf; /* this is an errata in the original Yavapai manual.
1108 The interrupt steering bits are reversed, so a '1'
1109 routes XINT interrupts to FIQ
1112 /* install diag IRQ handlers */
1113 ((volatile unsigned *)0x20)[6] = (unsigned)__diag_IRQ;
1114 ((volatile unsigned *)0x20)[7] = (unsigned)__diag_FIQ;
1117 /* make sure interrupts are enabled in CSPR */
1119 _cspr_enable_irq_int();
1121 _cspr_enable_fiq_int();
1123 /* initialize the PCI interrupt table */
1124 for (xint = 0; xint < NUM_PCI_XINTS; xint++)
1126 for (x = 0; x < MAX_PCI_HANDLERS; x++)
1128 pci_int_handlers[xint][x].handler = NULL;
1129 pci_int_handlers[xint][x].arg = (int)NULL;
1130 pci_int_handlers[xint][x].bus = (int)NULL;
1131 pci_int_handlers[xint][x].device = (int)NULL;