1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 /*=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
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41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //=============================================================================
44 //#####DESCRIPTIONBEGIN####
47 // Contributors: msalter
49 // Purpose: Motorola PRPMC1100 specific support routines
51 // Usage: #include <cyg/hal/hal_platform_setup.h>
52 // Only used by "vectors.S"
54 //####DESCRIPTIONEND####
56 //===========================================================================*/
58 #include <pkgconf/system.h> // System-wide configuration info
59 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
60 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
61 #include <cyg/hal/hal_ixp425.h> // Variant specific hardware definitions
62 #include <cyg/hal/hal_mmu.h> // MMU definitions
63 #include <cyg/hal/hal_mm.h> // more MMU definitions
64 #include <cyg/hal/prpmc1100.h> // Platform specific hardware definitions
66 #if defined(CYG_HAL_STARTUP_ROM)
67 #define PLATFORM_SETUP1 _platform_setup1
68 #define PLATFORM_EXTRAS <cyg/hal/hal_platform_extras.h>
69 #define CYGHWR_HAL_ARM_HAS_MMU
71 // ------------------------------------------------------------------------
72 // Define macro used to diddle the LEDs during early initialization.
73 // Can use r0+r1. Argument in \x.
74 #define CYGHWR_LED_MACRO
77 .macro DELAY cycles, reg0
85 // ------------------------------------------------------------------------
86 // This macro represents the initial startup code for the platform
87 .macro _platform_setup1
89 #if CYGINT_HAL_ARM_BIGENDIAN
91 mrc p15, 0, r0, c1, c0, 0
93 mcr p15, 0, r0, c1, c0, 0
97 ldr r0,=(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE)
100 // invalidate I & D caches & BTB
101 mcr p15, 0, r0, c7, c7, 0
104 // invalidate I & Data TLB
105 mcr p15, 0, r0, c8, c7, 0
108 // drain write and fill buffers
109 mcr p15, 0, r0, c7, c10, 4
112 // disable write buffer coalescing
113 mrc p15, 0, r0, c1, c0, 1
115 mcr p15, 0, r0, c1, c0, 1
118 // Setup chip selects
119 ldr r1, =IXP425_EXP_CFG_BASE
120 #ifdef IXP425_EXP_CS0_INIT
121 ldr r0, =IXP425_EXP_CS0_INIT
122 str r0, [r1, #IXP425_EXP_CS0]
124 #ifdef IXP425_EXP_CS1_INIT
125 ldr r0, =IXP425_EXP_CS1_INIT
126 str r0, [r1, #IXP425_EXP_CS1]
128 #ifdef IXP425_EXP_CS2_INIT
129 ldr r0, =IXP425_EXP_CS2_INIT
130 str r0, [r1, #IXP425_EXP_CS2]
132 #ifdef IXP425_EXP_CS3_INIT
133 ldr r0, =IXP425_EXP_CS3_INIT
134 str r0, [r1, #IXP425_EXP_CS3]
136 #ifdef IXP425_EXP_CS4_INIT
137 ldr r0, =IXP425_EXP_CS4_INIT
138 str r0, [r1, #IXP425_EXP_CS4]
140 #ifdef IXP425_EXP_CS5_INIT
141 ldr r0, =IXP425_EXP_CS5_INIT
142 str r0, [r1, #IXP425_EXP_CS5]
144 #ifdef IXP425_EXP_CS6_INIT
145 ldr r0, =IXP425_EXP_CS6_INIT
146 str r0, [r1, #IXP425_EXP_CS6]
148 #ifdef IXP425_EXP_CS7_INIT
149 ldr r0, =IXP425_EXP_CS7_INIT
150 str r0, [r1, #IXP425_EXP_CS7]
154 mrc p15, 0, r0, c1, c0, 0
155 orr r0, r0, #MMU_Control_I
156 mcr p15, 0, r0, c1, c0, 0
159 // Setup SDRAM controller
161 ldr r0, =IXP425_SDRAM_CFG_BASE
163 ldr r1, =IXP425_SDRAM_CONFIG_INIT
164 str r1, [r0, #IXP425_SDRAM_CONFIG]
166 // disable refresh cycles
168 str r1, [r0, #IXP425_SDRAM_REFRESH]
171 mov r1, #SDRAM_IR_NOP
172 str r1, [r0, #IXP425_SDRAM_IR]
175 // set SDRAM internal refresh val
176 ldr r1, =IXP425_SDRAM_REFRESH_CNT
177 str r1, [r0, #IXP425_SDRAM_REFRESH]
180 // send precharge-all command to close all open banks
181 mov r1, #SDRAM_IR_PRECHARGE
182 str r1, [r0, #IXP425_SDRAM_IR]
185 // provide 8 auto-refresh cycles
186 mov r1, #SDRAM_IR_AUTO_REFRESH
189 str r1, [r0, #IXP425_SDRAM_IR]
194 // set mode register in sdram
195 mov r1, #IXP425_SDRAM_SET_MODE_CMD
196 str r1, [r0, #IXP425_SDRAM_IR]
199 // start normal operation
200 mov r1, #SDRAM_IR_NORMAL
201 str r1, [r0, #IXP425_SDRAM_IR]
204 // value to load into pc to jump to real runtime address
207 // Setup EXP_CNFG0 value to switch EXP bus out of low memory
208 ldr r2, =IXP425_EXP_CFG_BASE
209 ldr r1, [r2, #IXP425_EXP_CNFG0]
210 bic r1, r1, #EXP_CNFG0_MEM_MAP
215 // Here is where we switch from boot address (0x000000000) to the
216 // actual flash runtime address. We align to cache boundary so we
217 // execute from cache during the switchover. Cachelines are 8 words.
218 str r1, [r2, #IXP425_EXP_CNFG0] // make the EXP bus switch
225 // display FFFF and loop forever.
229 // Move mmu tables into RAM so page table walks by the cpu
230 // don't interfere with FLASH programming.
232 add r2, r0, #0x4000 // End of tables
233 mov r1, #SDRAM_PHYS_BASE
234 orr r1, r1, #0x4000 // RAM tables
236 // everything can go as-is
243 mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers
246 // Set the TTB register to DRAM mmu_table
247 ldr r0, =(SDRAM_PHYS_BASE | 0x4000) // RAM tables
248 mcr p15, 0, r0, c2, c0, 0 // load page table pointer
251 // enable permission checks in all domains
253 mcr p15, 0, r0, c3, c0, 0
257 mrc p15, 0, r0, c1, c0, 0
258 orr r0, r0, #MMU_Control_M
259 orr r0, r0, #MMU_Control_R
260 mcr p15, 0, r0, c1, c0, 0
264 mrc p15, 0, r0, c1, c0, 0
265 orr r0, r0, #MMU_Control_C
266 mcr p15, 0, r0, c1, c0, 0
269 // Enable branch target buffer
270 mrc p15, 0, r0, c1, c0, 0
271 orr r0, r0, #MMU_Control_BTB
272 mcr p15, 0, r0, c1, c0, 0
275 mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers
278 mcr p15, 0, r0, c7, c7, 0 // flush Icache, Dcache and BTB
281 mcr p15, 0, r0, c8, c7, 0 // flush instuction and data TLBs
284 mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers
288 ldr r1, =hal_dram_size /* [see hal_intr.h] */
292 .endm // _platform_setup1
294 #else // defined(CYG_HAL_STARTUP_ROM)
295 #define PLATFORM_SETUP1
298 #define PLATFORM_VECTORS _platform_vectors
299 .macro _platform_vectors
302 /*---------------------------------------------------------------------------*/
303 /* end of hal_platform_setup.h */
304 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */