1 #ifndef CYGONCE_HAL_VAR_INTS_H
2 #define CYGONCE_HAL_VAR_INTS_H
3 //==========================================================================
7 // HAL Interrupt and clock support
9 //==========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 // eCos is free software; you can redistribute it and/or modify it under
16 // the terms of the GNU General Public License as published by the Free
17 // Software Foundation; either version 2 or (at your option) any later version.
19 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
20 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 // You should have received a copy of the GNU General Public License along
25 // with eCos; if not, write to the Free Software Foundation, Inc.,
26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28 // As a special exception, if other files instantiate templates or use macros
29 // or inline functions from this file, or you compile this file and link it
30 // with other works to produce a work based on this file, this file does not
31 // by itself cause the resulting work to be covered by the GNU General Public
32 // License. However the source code for this file must still be made available
33 // in accordance with section (3) of the GNU General Public License.
35 // This exception does not invalidate any other reasons why a work based on
36 // this file might be covered by the GNU General Public License.
38 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
39 // at http://sources.redhat.com/ecos/ecos-license/
40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 //==========================================================================
43 //#####DESCRIPTIONBEGIN####
45 // Author(s): <knud.woehler@microplex.de>
48 //####DESCRIPTIONEND####
50 //==========================================================================
52 #include <cyg/hal/hal_pxa2x0.h>
56 #define CYGNUM_HAL_INTERRUPT_GPIO0 8
57 #define CYGNUM_HAL_INTERRUPT_GPIO1 9
58 #define CYGNUM_HAL_INTERRUPT_GPIO 10
59 #define CYGNUM_HAL_INTERRUPT_USB 11
60 #define CYGNUM_HAL_INTERRUPT_PMU 12
61 #define CYGNUM_HAL_INTERRUPT_I2S 13
62 #define CYGNUM_HAL_INTERRUPT_AC97 14
64 #define CYGNUM_HAL_INTERRUPT_LCD 17
65 #define CYGNUM_HAL_INTERRUPT_I2C 18
66 #define CYGNUM_HAL_INTERRUPT_ICP 19
67 #define CYGNUM_HAL_INTERRUPT_STUART 20
68 #define CYGNUM_HAL_INTERRUPT_BTUART 21
69 #define CYGNUM_HAL_INTERRUPT_FFUART 22
70 #define CYGNUM_HAL_INTERRUPT_MMC 23
71 #define CYGNUM_HAL_INTERRUPT_SSP 24
72 #define CYGNUM_HAL_INTERRUPT_DMA 25
73 #define CYGNUM_HAL_INTERRUPT_TIMER0 26
74 #define CYGNUM_HAL_INTERRUPT_TIMER1 27
75 #define CYGNUM_HAL_INTERRUPT_TIMER2 28
76 #define CYGNUM_HAL_INTERRUPT_TIMER3 29
77 #define CYGNUM_HAL_INTERRUPT_HZ 30
78 #define CYGNUM_HAL_INTERRUPT_ALARM 31
82 #define CYGNUM_HAL_INTERRUPT_GPIO2 (32+2)
83 #define CYGNUM_HAL_INTERRUPT_GPIO3 (32+3)
84 #define CYGNUM_HAL_INTERRUPT_GPIO4 (32+4)
85 #define CYGNUM_HAL_INTERRUPT_GPIO5 (32+5)
86 #define CYGNUM_HAL_INTERRUPT_GPIO6 (32+6)
87 #define CYGNUM_HAL_INTERRUPT_GPIO7 (32+7)
88 #define CYGNUM_HAL_INTERRUPT_GPIO8 (32+8)
89 #define CYGNUM_HAL_INTERRUPT_GPIO9 (32+9)
90 #define CYGNUM_HAL_INTERRUPT_GPIO10 (32+10)
91 #define CYGNUM_HAL_INTERRUPT_GPIO11 (32+11)
92 #define CYGNUM_HAL_INTERRUPT_GPIO12 (32+12)
93 #define CYGNUM_HAL_INTERRUPT_GPIO13 (32+13)
94 #define CYGNUM_HAL_INTERRUPT_GPIO14 (32+14)
95 #define CYGNUM_HAL_INTERRUPT_GPIO15 (32+15)
96 #define CYGNUM_HAL_INTERRUPT_GPIO16 (32+16)
97 #define CYGNUM_HAL_INTERRUPT_GPIO17 (32+17)
98 #define CYGNUM_HAL_INTERRUPT_GPIO18 (32+18)
99 #define CYGNUM_HAL_INTERRUPT_GPIO19 (32+19)
100 #define CYGNUM_HAL_INTERRUPT_GPIO20 (32+20)
101 #define CYGNUM_HAL_INTERRUPT_GPIO21 (32+21)
102 #define CYGNUM_HAL_INTERRUPT_GPIO22 (32+22)
103 #define CYGNUM_HAL_INTERRUPT_GPIO23 (32+23)
104 #define CYGNUM_HAL_INTERRUPT_GPIO24 (32+24)
105 #define CYGNUM_HAL_INTERRUPT_GPIO25 (32+25)
106 #define CYGNUM_HAL_INTERRUPT_GPIO26 (32+26)
107 #define CYGNUM_HAL_INTERRUPT_GPIO27 (32+27)
108 #define CYGNUM_HAL_INTERRUPT_GPIO28 (32+28)
109 #define CYGNUM_HAL_INTERRUPT_GPIO29 (32+29)
110 #define CYGNUM_HAL_INTERRUPT_GPIO30 (32+30)
111 #define CYGNUM_HAL_INTERRUPT_GPIO31 (32+31)
113 #define CYGNUM_HAL_INTERRUPT_GPIO32 (64+0)
114 #define CYGNUM_HAL_INTERRUPT_GPIO33 (64+1)
115 #define CYGNUM_HAL_INTERRUPT_GPIO34 (64+2)
116 #define CYGNUM_HAL_INTERRUPT_GPIO35 (64+3)
117 #define CYGNUM_HAL_INTERRUPT_GPIO36 (64+4)
118 #define CYGNUM_HAL_INTERRUPT_GPIO37 (64+5)
119 #define CYGNUM_HAL_INTERRUPT_GPIO38 (64+6)
120 #define CYGNUM_HAL_INTERRUPT_GPIO39 (64+7)
121 #define CYGNUM_HAL_INTERRUPT_GPIO40 (64+8)
122 #define CYGNUM_HAL_INTERRUPT_GPIO41 (64+9)
123 #define CYGNUM_HAL_INTERRUPT_GPIO42 (64+10)
124 #define CYGNUM_HAL_INTERRUPT_GPIO43 (64+11)
125 #define CYGNUM_HAL_INTERRUPT_GPIO44 (64+12)
126 #define CYGNUM_HAL_INTERRUPT_GPIO45 (64+13)
127 #define CYGNUM_HAL_INTERRUPT_GPIO46 (64+14)
128 #define CYGNUM_HAL_INTERRUPT_GPIO47 (64+15)
129 #define CYGNUM_HAL_INTERRUPT_GPIO48 (64+16)
130 #define CYGNUM_HAL_INTERRUPT_GPIO49 (64+17)
131 #define CYGNUM_HAL_INTERRUPT_GPIO50 (64+18)
132 #define CYGNUM_HAL_INTERRUPT_GPIO51 (64+19)
133 #define CYGNUM_HAL_INTERRUPT_GPIO52 (64+20)
134 #define CYGNUM_HAL_INTERRUPT_GPIO53 (64+21)
135 #define CYGNUM_HAL_INTERRUPT_GPIO54 (64+22)
136 #define CYGNUM_HAL_INTERRUPT_GPIO55 (64+23)
137 #define CYGNUM_HAL_INTERRUPT_GPIO56 (64+24)
138 #define CYGNUM_HAL_INTERRUPT_GPIO57 (64+25)
139 #define CYGNUM_HAL_INTERRUPT_GPIO58 (64+26)
140 #define CYGNUM_HAL_INTERRUPT_GPIO59 (64+27)
141 #define CYGNUM_HAL_INTERRUPT_GPIO60 (64+28)
142 #define CYGNUM_HAL_INTERRUPT_GPIO61 (64+29)
143 #define CYGNUM_HAL_INTERRUPT_GPIO62 (64+30)
144 #define CYGNUM_HAL_INTERRUPT_GPIO63 (64+31)
146 #define CYGNUM_HAL_INTERRUPT_GPIO64 (96+0)
147 #define CYGNUM_HAL_INTERRUPT_GPIO65 (96+1)
148 #define CYGNUM_HAL_INTERRUPT_GPIO66 (96+2)
149 #define CYGNUM_HAL_INTERRUPT_GPIO67 (96+3)
150 #define CYGNUM_HAL_INTERRUPT_GPIO68 (96+4)
151 #define CYGNUM_HAL_INTERRUPT_GPIO69 (96+5)
152 #define CYGNUM_HAL_INTERRUPT_GPIO70 (96+6)
153 #define CYGNUM_HAL_INTERRUPT_GPIO71 (96+7)
154 #define CYGNUM_HAL_INTERRUPT_GPIO72 (96+8)
155 #define CYGNUM_HAL_INTERRUPT_GPIO73 (96+9)
156 #define CYGNUM_HAL_INTERRUPT_GPIO74 (96+10)
157 #define CYGNUM_HAL_INTERRUPT_GPIO75 (96+11)
158 #define CYGNUM_HAL_INTERRUPT_GPIO76 (96+12)
159 #define CYGNUM_HAL_INTERRUPT_GPIO77 (96+13)
160 #define CYGNUM_HAL_INTERRUPT_GPIO78 (96+14)
161 #define CYGNUM_HAL_INTERRUPT_GPIO79 (96+15)
162 #define CYGNUM_HAL_INTERRUPT_GPIO80 (96+16)
163 #define CYGNUM_HAL_INTERRUPT_GPIO81 (96+17)
164 #define CYGNUM_HAL_INTERRUPT_GPIO82 (96+18)
165 #define CYGNUM_HAL_INTERRUPT_GPIO83 (96+19)
166 #define CYGNUM_HAL_INTERRUPT_GPIO84 (96+20)
167 #define CYGNUM_HAL_INTERRUPT_GPIO85 (96+21)
170 #define CYGNUM_HAL_INTERRUPT_NONE -1
172 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0
174 #define CYGNUM_HAL_ISR_MIN 0
175 #define CYGNUM_HAL_ISR_MAX (96+21)
176 #define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX-CYGNUM_HAL_ISR_MIN+1)
178 #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
179 externC void hal_clock_latency(cyg_uint32 *);
180 # define HAL_CLOCK_LATENCY( _pvalue_ ) hal_clock_latency( (cyg_uint32 *)(_pvalue_) )
185 #define HAL_PLATFORM_RESET() \
188 HAL_DISABLE_INTERRUPTS(ctrl); \
189 *PXA2X0_OWER = PXA2X0_OWER_WME; \
190 *PXA2X0_OSMR3 = *PXA2X0_OSCR + 1000; \
194 #define HAL_PLATFORM_RESET_ENTRY 0x00000000
196 #endif // CYGONCE_HAL_VAR_INTS_H