1 #ifndef CYGONCE_HAL_PLATFORM_INTS_H
2 #define CYGONCE_HAL_PLATFORM_INTS_H
3 //==========================================================================
7 // HAL Interrupt and clock support
9 //#####ECOSGPLCOPYRIGHTBEGIN####
10 //## -------------------------------------------
11 //## This file is part of eCos, the Embedded Configurable Operating System.
12 //## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
14 //## eCos is free software; you can redistribute it and/or modify it under
15 //## the terms of the GNU General Public License as published by the Free
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19 //## WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 //## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
21 //## for more details.
23 //## You should have received a copy of the GNU General Public License along
24 //## with eCos; if not, write to the Free Software Foundation, Inc.,
25 //## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 //## As a special exception, if other files instantiate templates or use macros
28 //## or inline functions from this file, or you compile this file and link it
29 //## with other works to produce a work based on this file, this file does not
30 //## by itself cause the resulting work to be covered by the GNU General Public
31 //## License. However the source code for this file must still be made available
32 //## in accordance with section (3) of the GNU General Public License.
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35 //## this file might be covered by the GNU General Public License.
37 //## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
38 //## at http://sources.redhat.com/ecos/ecos-license/
39 //## -------------------------------------------
40 //#####ECOSGPLCOPYRIGHTEND####
41 //#####DESCRIPTIONBEGIN####
46 // Purpose: Define Interrupt support
47 // Description: The interrupt details for the INPHINITY are defined here.
49 // #include <cyg/hal/hal_platform_ints.h>
53 //####DESCRIPTIONEND####
55 //==========================================================================
62 #define CYGNUM_HAL_INTERRUPT_SSP3 0
63 #define CYGNUM_HAL_INTERRUPT_MSL 1
64 #define CYGNUM_HAL_INTERRUPT_USBH2 2
65 #define CYGNUM_HAL_INTERRUPT_USBH1 3
66 #define CYGNUM_HAL_INTERRUPT_KEY 4
67 #define CYGNUM_HAL_INTERRUPT_MSTICK 5
68 #define CYGNUM_HAL_INTERRUPT_PI2C 6
69 #define CYGNUM_HAL_INTERRUPT_UTIMER 7
72 #define CYGNUM_HAL_INTERRUPT_GPIO0 8
73 #define CYGNUM_HAL_INTERRUPT_GPIO1 9
74 #define CYGNUM_HAL_INTERRUPT_GPIO 10
75 #define CYGNUM_HAL_INTERRUPT_USB 11
76 #define CYGNUM_HAL_INTERRUPT_PMU 12
77 #define CYGNUM_HAL_INTERRUPT_I2S 13
78 #define CYGNUM_HAL_INTERRUPT_AC97 14
79 #define CYGNUM_HAL_INTERRUPT_USIM 15
80 #define CYGNUM_HAL_INTERRUPT_SSP2 16
86 #define CYGNUM_HAL_INTERRUPT_LCD 17
87 #define CYGNUM_HAL_INTERRUPT_I2C 18
88 #define CYGNUM_HAL_INTERRUPT_ICP 19
89 #define CYGNUM_HAL_INTERRUPT_STUART 20
90 #define CYGNUM_HAL_INTERRUPT_BTUART 21
91 #define CYGNUM_HAL_INTERRUPT_FFUART 22
92 #define CYGNUM_HAL_INTERRUPT_MMC 23
93 #define CYGNUM_HAL_INTERRUPT_SSP 24
94 #define CYGNUM_HAL_INTERRUPT_DMA 25
95 #define CYGNUM_HAL_INTERRUPT_TIMER0 26
96 #define CYGNUM_HAL_INTERRUPT_TIMER1 27
97 #define CYGNUM_HAL_INTERRUPT_TIMER2 28
98 #define CYGNUM_HAL_INTERRUPT_TIMER3 29
99 #define CYGNUM_HAL_INTERRUPT_HZ 30
100 #define CYGNUM_HAL_INTERRUPT_ALARM 31
103 #define CYGNUM_HAL_INTERRUPT_GPIO2 (32+2)
104 #define CYGNUM_HAL_INTERRUPT_GPIO3 (32+3)
105 #define CYGNUM_HAL_INTERRUPT_GPIO4 (32+4)
106 #define CYGNUM_HAL_INTERRUPT_GPIO5 (32+5)
107 #define CYGNUM_HAL_INTERRUPT_GPIO6 (32+6)
108 #define CYGNUM_HAL_INTERRUPT_GPIO7 (32+7)
109 #define CYGNUM_HAL_INTERRUPT_GPIO8 (32+8)
110 #define CYGNUM_HAL_INTERRUPT_GPIO9 (32+9)
111 #define CYGNUM_HAL_INTERRUPT_GPIO10 (32+10)
112 #define CYGNUM_HAL_INTERRUPT_GPIO11 (32+11)
113 #define CYGNUM_HAL_INTERRUPT_GPIO12 (32+12)
114 #define CYGNUM_HAL_INTERRUPT_GPIO13 (32+13)
115 #define CYGNUM_HAL_INTERRUPT_GPIO14 (32+14)
116 #define CYGNUM_HAL_INTERRUPT_GPIO15 (32+15)
117 #define CYGNUM_HAL_INTERRUPT_GPIO16 (32+16)
118 #define CYGNUM_HAL_INTERRUPT_GPIO17 (32+17)
119 #define CYGNUM_HAL_INTERRUPT_GPIO18 (32+18)
120 #define CYGNUM_HAL_INTERRUPT_GPIO19 (32+19)
121 #define CYGNUM_HAL_INTERRUPT_GPIO20 (32+20)
122 #define CYGNUM_HAL_INTERRUPT_GPIO21 (32+21)
123 #define CYGNUM_HAL_INTERRUPT_GPIO22 (32+22)
124 #define CYGNUM_HAL_INTERRUPT_GPIO23 (32+23)
125 #define CYGNUM_HAL_INTERRUPT_GPIO24 (32+24)
126 #define CYGNUM_HAL_INTERRUPT_GPIO25 (32+25)
127 #define CYGNUM_HAL_INTERRUPT_GPIO26 (32+26)
128 #define CYGNUM_HAL_INTERRUPT_GPIO27 (32+27)
129 #define CYGNUM_HAL_INTERRUPT_GPIO28 (32+28)
130 #define CYGNUM_HAL_INTERRUPT_GPIO29 (32+29)
131 #define CYGNUM_HAL_INTERRUPT_GPIO30 (32+30)
132 #define CYGNUM_HAL_INTERRUPT_GPIO31 (32+31)
134 #define CYGNUM_HAL_INTERRUPT_GPIO32 (64+0)
135 #define CYGNUM_HAL_INTERRUPT_GPIO33 (64+1)
136 #define CYGNUM_HAL_INTERRUPT_GPIO34 (64+2)
137 #define CYGNUM_HAL_INTERRUPT_GPIO35 (64+3)
138 #define CYGNUM_HAL_INTERRUPT_GPIO36 (64+4)
139 #define CYGNUM_HAL_INTERRUPT_GPIO37 (64+5)
140 #define CYGNUM_HAL_INTERRUPT_GPIO38 (64+6)
141 #define CYGNUM_HAL_INTERRUPT_GPIO39 (64+7)
142 #define CYGNUM_HAL_INTERRUPT_GPIO40 (64+8)
143 #define CYGNUM_HAL_INTERRUPT_GPIO41 (64+9)
144 #define CYGNUM_HAL_INTERRUPT_GPIO42 (64+10)
145 #define CYGNUM_HAL_INTERRUPT_GPIO43 (64+11)
146 #define CYGNUM_HAL_INTERRUPT_GPIO44 (64+12)
147 #define CYGNUM_HAL_INTERRUPT_GPIO45 (64+13)
148 #define CYGNUM_HAL_INTERRUPT_GPIO46 (64+14)
149 #define CYGNUM_HAL_INTERRUPT_GPIO47 (64+15)
150 #define CYGNUM_HAL_INTERRUPT_GPIO48 (64+16)
151 #define CYGNUM_HAL_INTERRUPT_GPIO49 (64+17)
152 #define CYGNUM_HAL_INTERRUPT_GPIO50 (64+18)
153 #define CYGNUM_HAL_INTERRUPT_GPIO51 (64+19)
154 #define CYGNUM_HAL_INTERRUPT_GPIO52 (64+20)
155 #define CYGNUM_HAL_INTERRUPT_GPIO53 (64+21)
156 #define CYGNUM_HAL_INTERRUPT_GPIO54 (64+22)
157 #define CYGNUM_HAL_INTERRUPT_GPIO55 (64+23)
158 #define CYGNUM_HAL_INTERRUPT_GPIO56 (64+24)
159 #define CYGNUM_HAL_INTERRUPT_GPIO57 (64+25)
160 #define CYGNUM_HAL_INTERRUPT_GPIO58 (64+26)
161 #define CYGNUM_HAL_INTERRUPT_GPIO59 (64+27)
162 #define CYGNUM_HAL_INTERRUPT_GPIO60 (64+28)
163 #define CYGNUM_HAL_INTERRUPT_GPIO61 (64+29)
164 #define CYGNUM_HAL_INTERRUPT_GPIO62 (64+30)
165 #define CYGNUM_HAL_INTERRUPT_GPIO63 (64+31)
167 #define CYGNUM_HAL_INTERRUPT_GPIO64 (96+0)
168 #define CYGNUM_HAL_INTERRUPT_GPIO65 (96+1)
169 #define CYGNUM_HAL_INTERRUPT_GPIO66 (96+2)
170 #define CYGNUM_HAL_INTERRUPT_GPIO67 (96+3)
171 #define CYGNUM_HAL_INTERRUPT_GPIO68 (96+4)
172 #define CYGNUM_HAL_INTERRUPT_GPIO69 (96+5)
173 #define CYGNUM_HAL_INTERRUPT_GPIO70 (96+6)
174 #define CYGNUM_HAL_INTERRUPT_GPIO71 (96+7)
175 #define CYGNUM_HAL_INTERRUPT_GPIO72 (96+8)
176 #define CYGNUM_HAL_INTERRUPT_GPIO73 (96+9)
177 #define CYGNUM_HAL_INTERRUPT_GPIO74 (96+10)
178 #define CYGNUM_HAL_INTERRUPT_GPIO75 (96+11)
179 #define CYGNUM_HAL_INTERRUPT_GPIO76 (96+12)
180 #define CYGNUM_HAL_INTERRUPT_GPIO77 (96+13)
181 #define CYGNUM_HAL_INTERRUPT_GPIO78 (96+14)
182 #define CYGNUM_HAL_INTERRUPT_GPIO79 (96+15)
183 #define CYGNUM_HAL_INTERRUPT_GPIO80 (96+16)
184 #define CYGNUM_HAL_INTERRUPT_GPIO81 (96+17)
185 #define CYGNUM_HAL_INTERRUPT_GPIO82 (96+18)
186 #define CYGNUM_HAL_INTERRUPT_GPIO83 (96+19)
187 #define CYGNUM_HAL_INTERRUPT_GPIO84 (96+20)
188 #define CYGNUM_HAL_INTERRUPT_GPIO85 (96+21)
189 #define CYGNUM_HAL_INTERRUPT_GPIO86 (96+22)
190 #define CYGNUM_HAL_INTERRUPT_GPIO87 (96+23)
191 #define CYGNUM_HAL_INTERRUPT_GPIO88 (96+24)
192 #define CYGNUM_HAL_INTERRUPT_GPIO89 (96+25)
193 #define CYGNUM_HAL_INTERRUPT_GPIO90 (96+26)
194 #define CYGNUM_HAL_INTERRUPT_GPIO91 (96+27)
195 #define CYGNUM_HAL_INTERRUPT_GPIO92 (96+28)
196 #define CYGNUM_HAL_INTERRUPT_GPIO93 (96+29)
197 #define CYGNUM_HAL_INTERRUPT_GPIO94 (96+30)
198 #define CYGNUM_HAL_INTERRUPT_GPIO95 (96+31)
200 #define CYGNUM_HAL_INTERRUPT_GPIO96 (128+0)
201 #define CYGNUM_HAL_INTERRUPT_GPIO97 (128+1)
202 #define CYGNUM_HAL_INTERRUPT_GPIO98 (128+2)
203 #define CYGNUM_HAL_INTERRUPT_GPIO99 (128+3)
204 #define CYGNUM_HAL_INTERRUPT_GPIO100 (128+4)
205 #define CYGNUM_HAL_INTERRUPT_GPIO101 (128+5)
206 #define CYGNUM_HAL_INTERRUPT_GPIO102 (128+6)
207 #define CYGNUM_HAL_INTERRUPT_GPIO103 (128+7)
208 #define CYGNUM_HAL_INTERRUPT_GPIO104 (128+8)
209 #define CYGNUM_HAL_INTERRUPT_GPIO105 (128+9)
210 #define CYGNUM_HAL_INTERRUPT_GPIO106 (128+10)
211 #define CYGNUM_HAL_INTERRUPT_GPIO107 (128+11)
212 #define CYGNUM_HAL_INTERRUPT_GPIO108 (128+12)
213 #define CYGNUM_HAL_INTERRUPT_GPIO109 (128+13)
214 #define CYGNUM_HAL_INTERRUPT_GPIO110 (128+14)
215 #define CYGNUM_HAL_INTERRUPT_GPIO111 (128+15)
216 #define CYGNUM_HAL_INTERRUPT_GPIO112 (128+16)
217 #define CYGNUM_HAL_INTERRUPT_GPIO113 (128+17)
218 #define CYGNUM_HAL_INTERRUPT_GPIO114 (128+18)
219 #define CYGNUM_HAL_INTERRUPT_GPIO115 (128+19)
220 #define CYGNUM_HAL_INTERRUPT_GPIO116 (128+20)
221 #define CYGNUM_HAL_INTERRUPT_GPIO117 (128+21)
222 #define CYGNUM_HAL_INTERRUPT_GPIO118 (128+22)
223 #define CYGNUM_HAL_INTERRUPT_GPIO119 (128+23)
224 #define CYGNUM_HAL_INTERRUPT_GPIO120 (128+24)
225 #define CYGNUM_HAL_INTERRUPT_GPIO121 (128+25)
226 #define CYGNUM_HAL_INTERRUPT_GPIO122 (128+26)
227 #define CYGNUM_HAL_INTERRUPT_GPIO123 (128+27)
228 #define CYGNUM_HAL_INTERRUPT_GPIO124 (128+28)
229 #define CYGNUM_HAL_INTERRUPT_GPIO125 (128+29)
230 #define CYGNUM_HAL_INTERRUPT_GPIO126 (128+30)
231 #define CYGNUM_HAL_INTERRUPT_GPIO127 (128+31)
233 externC void cyg_hal_xscale_soft_reset(CYG_ADDRESS);
234 #define HAL_PLATFORM_RESET() cyg_hal_xscale_soft_reset(HAL_PLATFORM_RESET_ENTRY);
236 #define HAL_PLATFORM_RESET_ENTRY 0x00000000
238 // *** remainder are reserved ****
239 #define CYGNUM_HAL_INT_
241 #define CYGNUM_HAL_ISR_MIN 0
242 #define CYGNUM_HAL_ISR_MAX 48
244 #define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX + 1)
246 // The vector used by the Real time clock
247 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER
248 //#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_PMU_CCNT_OVFL
250 extern void hal_delay_us(cyg_uint32 usecs);
252 #define HAL_DELAY_US(n) hal_delay_us(n);
254 #endif // CYGONCE_HAL_PLATFORM_INTS_H