1 //==========================================================================
5 // HAL misc board support code for XScale TRITON270
7 //==========================================================================
8 //#####ECOSGPLCOPYRIGHTBEGIN####
9 //## -------------------------------------------
10 //## This file is part of eCos, the Embedded Configurable Operating System.
11 //## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 //## eCos is free software; you can redistribute it and/or modify it under
14 //## the terms of the GNU General Public License as published by the Free
15 //## Software Foundation; either version 2 or (at your option) any later version.
17 //## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 //## WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 //## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 //## for more details.
22 //## You should have received a copy of the GNU General Public License along
23 //## with eCos; if not, write to the Free Software Foundation, Inc.,
24 //## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 //## As a special exception, if other files instantiate templates or use macros
27 //## or inline functions from this file, or you compile this file and link it
28 //## with other works to produce a work based on this file, this file does not
29 //## by itself cause the resulting work to be covered by the GNU General Public
30 //## License. However the source code for this file must still be made available
31 //## in accordance with section (3) of the GNU General Public License.
33 //## This exception does not invalidate any other reasons why a work based on
34 //## this file might be covered by the GNU General Public License.
36 //## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37 //## at http://sources.redhat.com/ecos/ecos-license/
38 //## -------------------------------------------
39 //#####ECOSGPLCOPYRIGHTEND####
40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
43 // Author(s): msalter, usteinkohl
44 // Contributors: msalter, usteinkohl
45 // Date: 20th August 2004 (last modification)
46 // Purpose: HAL board support
47 // Description: Implementations of HAL board interfaces
49 //####DESCRIPTIONEND####
51 //========================================================================*/
53 #include <flash_config.h>
55 #include <pkgconf/hal.h>
56 #include <pkgconf/system.h>
57 #include CYGBLD_HAL_PLATFORM_H
58 #include CYGHWR_MEMORY_LAYOUT_H
60 #include <cyg/infra/cyg_type.h> // base types
61 #include <cyg/infra/cyg_trac.h> // tracing macros
62 #include <cyg/infra/cyg_ass.h> // assertion macros
64 #include <cyg/hal/hal_io.h> // IO macros
65 #include <cyg/hal/hal_stub.h> // Stub macros
66 #include <cyg/hal/hal_if.h> // calling interface API
67 #include <cyg/hal/hal_arch.h> // Register state info
68 #include <cyg/hal/hal_diag.h>
69 #include <cyg/hal/hal_intr.h> // Interrupt names
70 #include <cyg/hal/hal_cache.h>
71 #include <cyg/hal/hal_triton270.h> // Hardware definitions
72 #include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED
74 extern int printf(char *fmt, ...);
76 inline unsigned long _fu_phys_address(unsigned long _x_)
80 return _x_ + 0xa0000000;
82 return _x_ & 0xfffffff;
88 /*------------------------------------------------------------------------*/
91 void cyg_hal_plf_ide_init(void)
99 HAL_WRITE_UINT32(OSCR, 0); // initialize os timer counter
100 HAL_WRITE_UINT32(RCNR, 0); // initialize rtc counter
101 HAL_WRITE_UINT32(RTTR, 0x7FFF); // divide RTC to get 1hz output
103 // initialize interrupt registers
105 HAL_WRITE_UINT32(ICMR, 0); // Pending Interrupts are masked from becoming active
106 HAL_WRITE_UINT32(ICMR2, 0);
107 HAL_WRITE_UINT32(ICLR, 0); // Route all Interrupts to CPU IRQ (none to FIQ)
108 HAL_WRITE_UINT32(ICLR2, 0);
109 HAL_WRITE_UINT32(ICCR, 1); // Only enabled and unmasked interrupt bring core out of idle
112 // setup general purpose I/Os (specific to TRITON270 board)
113 // must set GPSR/GPCR, then set GPDR, then set GPAFR
115 // this is already done in the assembly code.
117 // clear all edge detect status bits
118 HAL_WRITE_UINT32(GEDRa, 0xffffffff); // clear all bits
119 HAL_WRITE_UINT32(GEDRb, 0xffffffff);
120 HAL_WRITE_UINT32(GEDRc, 0xffffffff);
121 HAL_WRITE_UINT32(GEDRd, 0xffffffff);
123 // setup PCMCIA timing parameters (should be optimized (usteinkohl)
125 // this is SK3 specific
127 // for about 200 MHz MEMCLK:
128 // command setup: 30 nsec
129 // command minimum duration: 100 nsec
130 // command hold: 20 nsec
132 HAL_WRITE_UINT32(MCIO0, 0x00040286);
133 HAL_WRITE_UINT32(MCIO1, 0x00040286);
135 HAL_WRITE_UINT32(MCMEM0, 0x00040286);
136 HAL_WRITE_UINT32(MCMEM1, 0x00040286);
138 HAL_WRITE_UINT32(MCATT0, 0x00040286);
139 HAL_WRITE_UINT32(MCATT1, 0x00040286);
141 HAL_WRITE_UINT32(MECR, 0x3); // set CIT and NOS
143 HAL_WRITE_UINT32(PWRICR, ICR_UR); // reset i2c_unit;
144 HAL_WRITE_UINT32(PWRICR, ICR_IUE | ICR_SCLE | ICR_GCD);
146 HAL_READ_UINT32(PCFR, value);
147 //value |= 0x00000040; // enable PI2C
148 value = value & (~0x400); // disable voltage change sequencer
149 HAL_WRITE_UINT32(PCFR, value);
152 void hal_sio_print_string(char *buf)
157 HAL_READ_UINT32(STLSR, value);
158 while(!(value & 0x40)) {
159 HAL_READ_UINT32(STLSR, value);
161 value = (cyg_uint32)(*buf++) & 0xff;
165 HAL_WRITE_UINT32(STTHR, value);
171 void unlock_flash_all(void);
173 void hal_hardware_init(void)
179 HAL_READ_UINT32(CKEN, cken);
180 // enable FFUART clock and BTUART clock and STUART
181 HAL_WRITE_UINT32(CKEN, cken | 0xe0);
183 // Let the "OS" counter run
186 // Set up eCos/ROM interfaces
187 hal_if_init(); //ecos, not platform, specifc. Common to all. Do not change.
190 HAL_DCACHE_ENABLE(); //leave this
191 HAL_ICACHE_ENABLE(); //leave this
193 //diag_printf("CKEN register: 0x%08X\n", cken);
195 // check if we restart from sleep mode
196 HAL_READ_UINT32(RCSR, val);
197 //HAL_WRITE_UINT32(RCSR, 0xf); // clear all bits
199 const char *sep = " ";
200 diag_printf("\nReset caused by:");
202 diag_printf("%shardware reset pin", sep);
206 diag_printf("%swatchdog reset", sep);
210 diag_printf("%sGPIO reset\n", sep);
214 diag_printf("%ssleep reset", sep);
216 HAL_READ_UINT32(PSPR, val);
218 diag_printf("\nwarning, NULL pointer detected in PSPR register\n");
220 diag_printf("\nrestarting operating system ...\n");
222 "mov pc, %0;" // jump to pointer
230 diag_printf("\nwarning, unknown reset source !!!!\n");
231 diag_printf("RCSR register: 0x%08X\n", val);
234 ind = get_clock_table_index(208);
236 HAL_READ_UINT32(MDREFR, val);
237 val |= 0x20000000; // set K0DB4
238 HAL_WRITE_UINT32(MDREFR, val);
240 change_core_voltage(ind);
243 if (pclktab[ind].MDREFR_K0DB2) {
244 HAL_READ_UINT32(MDREFR, val); // set K0DB2
247 HAL_READ_UINT32(MDREFR, val); // reset K0DB0
248 val &= (~0x00004000);
250 HAL_WRITE_UINT32(MDREFR, val);
252 if (pclktab[ind].MDREFR_K0DB4) {
253 HAL_READ_UINT32(MDREFR, val); // set K0DB2
256 HAL_READ_UINT32(MDREFR, val); // reset K0DB2
257 val &= (~0x20000000);
259 HAL_WRITE_UINT32(MDREFR, val);
262 void enable_sdcard_power(void)
266 HAL_READ_UINT32(GAFR1c, value); // set alternate function of GPIO91 to 0
268 HAL_WRITE_UINT32(GAFR1c, value);
270 HAL_READ_UINT32(GPDRc, value); // config GPIO91 as output
272 HAL_WRITE_UINT32(GPDRc, value);
274 HAL_WRITE_UINT32(GPCRc, 0x08000000); // clear GPIO91
275 HAL_DELAY_US(1000*1000);
277 HAL_WRITE_UINT32(DRCMR21, 0x00000088); // map SDCARD receive to DMA channel No. 8
278 HAL_WRITE_UINT32(DCSR8, 0x40000000); // set DMA channel to no descriptor fetch mode
279 HAL_WRITE_UINT32(DALGN, 0x100); // allow byte allinement for channel 8
281 #if 0 // only for Debug
282 HAL_WRITE_UINT32(GPCRa, 0x800);
284 HAL_READ_UINT32(GPDRa, value);
286 HAL_WRITE_UINT32(GPDRa, value);
291 #include CYGHWR_MEMORY_LAYOUT_H
292 typedef void code_fun(void);
293 void triton270_program_new_stack(void *func)
295 register CYG_ADDRESS stack_ptr asm("sp");
296 register CYG_ADDRESS old_stack asm("r4");
297 register code_fun *new_func asm("r0");
299 old_stack = stack_ptr;
301 stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
302 new_func = (code_fun*)func;
305 stack_ptr = old_stack;
310 "ldr r1,=0x00000800;" // we use GPIO23 for controlling the debug LED
313 "ldr r0,=0x40E00024;" // GPCR0
314 "str r1, [r0];" // switch the LED on
316 "ldr r2,=0x00a00000;" // wait some time
323 "ldr r0,=0x40E00018;" // GPSR0
324 "str r1, [r0];" // switch the LED off
326 "ldr r2,=0x00a00000;" // wait some time
336 : "r0","r1","r2","r3"
340 // Initialize the clock
341 static cyg_uint32 clock_period;
343 void hal_clock_initialize(cyg_uint32 period)
348 HAL_WRITE_UINT32(OSMR0, period);
349 clock_period = period;
352 HAL_WRITE_UINT32(OSCR, 0);
353 // Clear any pending interrupt
354 HAL_WRITE_UINT32(OSSR, OSSR_TIMER0);
355 // Enable timer 0 interrupt
356 HAL_READ_UINT32(OIER, oier);
357 HAL_WRITE_UINT32(OIER, oier | OIER_TIMER0);
359 // Unmask timer 0 interrupt
360 HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_TIMER0);
363 // This routine is called during a clock interrupt.
364 void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
368 // Load new match value
369 HAL_READ_UINT32(OSCR, oscr);
370 HAL_WRITE_UINT32(OSMR0, oscr + period);
371 // Clear any pending interrupt
372 HAL_WRITE_UINT32(OSSR, OSSR_TIMER0);
375 // Read the current value of the clock, returning the number of hardware
376 // "ticks" that have occurred (i.e. how far away the current value is from
379 // Note: The "contract" for this function is that the value is the number
380 // of hardware clocks that have happened since the last interrupt (i.e.
381 // when it was reset). This value is used to measure interrupt latencies.
382 // However, since the hardware counter runs freely, this routine computes
383 // the difference between the current clock period and the number of hardware
384 // ticks left before the next timer interrupt.
385 void hal_clock_read(cyg_uint32 *pvalue)
391 HAL_DISABLE_INTERRUPTS(orig);
392 HAL_READ_UINT32(OSCR, oscr);
393 HAL_READ_UINT32(OSMR0, osmr0);
394 *pvalue = clock_period + oscr - osmr0;
395 HAL_RESTORE_INTERRUPTS(orig);
398 // Delay for some number of micro-seconds
399 void hal_delay_us(cyg_uint32 time)
404 HAL_READ_UINT32(OSCR, ctr);
409 HAL_READ_UINT32(OSCR, oscr);
411 // FIXME: DEFINE AND USE a global CLOCK_TICK_RATE somewhere!
412 // This value is WRONG for PXA270!
413 //val += 271267; // 271267ps (3.6864Mhz -> 271.267ns)
414 val += 307692; // 307692ps (3.25Mhz -> 307.692ns)
417 } while (val < 1000000);
422 typedef cyg_uint32 cyg_ISR(cyg_uint32 vector, CYG_ADDRWORD data);
424 extern void cyg_interrupt_post_dsr(CYG_ADDRWORD intr_obj);
426 static inline cyg_uint32 hal_call_isr(cyg_uint32 vector)
431 // Interrupt handling
433 // This routine is called to respond to a hardware interrupt (IRQ). It
434 // should interrogate the hardware and return the IRQ vector number.
435 int hal_IRQ_handler(void)
437 cyg_uint32 sources, index;
439 #ifdef HAL_EXTENDED_IRQ_HANDLER
440 // Use platform specific IRQ handler, if defined
441 // Note: this macro should do a 'return' with the appropriate
442 // interrupt number if such an extended interrupt exists. The
443 // assumption is that the line after the macro starts 'normal' processing.
444 HAL_EXTENDED_IRQ_HANDLER(index);
447 HAL_READ_UINT32(ICIP, sources);
448 if (sources & 0xff0000) {
450 } else if (sources & 0xff00) {
452 } else if (sources & 0xff) {
458 if ((1 << index) & sources) {
459 if (index == CYGNUM_HAL_INTERRUPT_GPIO) {
460 // Special case of GPIO cascade. Search for lowest set bit
461 HAL_READ_UINT32(GEDRa, sources);
464 if (sources & (1 << index)) {
468 } while (index < 32);
469 HAL_READ_UINT32(GEDRb, sources);
472 if (sources & (1 << index)) {
476 } while (index < 32);
477 HAL_READ_UINT32(GEDRc, sources);
480 if (sources & (1 << index)) {
484 } while (index < 32);
485 HAL_READ_UINT32(GEDRc, sources);
488 if (sources & (1 << index)) {
492 } while (index < 23); // GPIOs 96..118
499 return CYGNUM_HAL_INTERRUPT_NONE; // This shouldn't happen!
502 void hal_interrupt_mask(int vector)
506 #ifdef HAL_EXTENDED_INTERRUPT_MASK
507 // Use platform specific handling, if defined
508 // Note: this macro should do a 'return' for "extended" values of 'vector'
509 // Normal vectors are handled by code subsequent to the macro call.
510 HAL_EXTENDED_INTERRUPT_MASK(vector);
512 if (vector >= CYGNUM_HAL_INTERRUPT_GPIO2) {
513 vector = CYGNUM_HAL_INTERRUPT_GPIO;
515 HAL_READ_UINT32(ICMR, icmr);
516 HAL_WRITE_UINT32(ICMR, icmr & ~(1 << vector));
519 void hal_interrupt_unmask(int vector)
523 #ifdef HAL_EXTENDED_INTERRUPT_UNMASK
524 // Use platform specific handling, if defined
525 // Note: this macro should do a 'return' for "extended" values of 'vector'
526 // Normal vectors are handled by code subsequent to the macro call.
527 HAL_EXTENDED_INTERRUPT_UNMASK(vector);
530 if (vector >= CYGNUM_HAL_INTERRUPT_GPIO2) {
531 vector = CYGNUM_HAL_INTERRUPT_GPIO;
533 HAL_READ_UINT32(ICMR, icmr);
534 HAL_WRITE_UINT32(ICMR, icmr | (1 << vector));
537 void hal_interrupt_acknowledge(int vector)
542 diag_printf("void hal_interrupt_acknowledge(int vector) entered ...\n");
543 diag_printf("vector = %d \n", vector);
546 case CYGNUM_HAL_INTERRUPT_ALARM:
547 HAL_READ_UINT32(RTSR, rtsr);
548 HAL_WRITE_UINT32(RTSR, (rtsr & ~0x2553) | 0x1);
550 case CYGNUM_HAL_INTERRUPT_HZ:
551 HAL_READ_UINT32(RTSR, rtsr);
552 HAL_WRITE_UINT32(RTSR, (rtsr & ~0x2553) | 0x2);
554 case CYGNUM_HAL_INTERRUPT_TIMER3:
555 HAL_WRITE_UINT32(OSSR, 0x08);
557 case CYGNUM_HAL_INTERRUPT_TIMER2:
558 HAL_WRITE_UINT32(OSSR, 0x04);
560 case CYGNUM_HAL_INTERRUPT_TIMER1:
561 HAL_WRITE_UINT32(OSSR, 0x02);
563 case CYGNUM_HAL_INTERRUPT_TIMER0:
564 HAL_WRITE_UINT32(OSSR, 0x01);
566 case CYGNUM_HAL_INTERRUPT_DMA:
567 // user specific code here
569 case CYGNUM_HAL_INTERRUPT_SSP:
570 // user specific code here
572 case CYGNUM_HAL_INTERRUPT_MMC:
573 // user specific code here
575 case CYGNUM_HAL_INTERRUPT_FFUART:
576 // user specific code here
578 case CYGNUM_HAL_INTERRUPT_BTUART:
579 // user specific code here
581 case CYGNUM_HAL_INTERRUPT_STUART:
582 // user specific code here
584 case CYGNUM_HAL_INTERRUPT_ICP:
585 // user specific code here
587 case CYGNUM_HAL_INTERRUPT_I2S:
588 // user specific code here
590 case CYGNUM_HAL_INTERRUPT_LCD:
591 // user specific code here
593 case CYGNUM_HAL_INTERRUPT_AC97:
594 // user specific code here
596 case CYGNUM_HAL_INTERRUPT_I2C:
597 // user specific code here
599 case CYGNUM_HAL_INTERRUPT_PMU:
600 // user specific code here
602 case CYGNUM_HAL_INTERRUPT_USB:
603 // user specific code here
605 // GPIO interrupts are driven by an edge detection mechanism. This
606 // is latching so these interrupts must be acknowledged directly.
607 // All other interrupts simply go away when the interrupting unit
608 // has been serviced by the ISR.
609 case CYGNUM_HAL_INTERRUPT_GPIO1:
610 HAL_WRITE_UINT32(GEDRa, 0x2);
612 case CYGNUM_HAL_INTERRUPT_GPIO0:
613 HAL_WRITE_UINT32(GEDRa, 0x1);
615 default: // the rest is second level GPIO
616 if (vector >= CYGNUM_HAL_INTERRUPT_GPIO96) {
617 HAL_WRITE_UINT32(GEDRd, (1 << (vector - 128)));
618 } else if (vector >= CYGNUM_HAL_INTERRUPT_GPIO64) {
619 HAL_WRITE_UINT32(GEDRc, (1 << (vector - 96)));
620 } else if (vector >= CYGNUM_HAL_INTERRUPT_GPIO32) {
621 HAL_WRITE_UINT32(GEDRb, (1 << (vector - 64)));
622 } else if (vector >= CYGNUM_HAL_INTERRUPT_GPIO2) {
623 HAL_WRITE_UINT32(GEDRa, (1 << (vector - 32)));
630 void hal_interrupt_configure(int vector, int level, int up)
633 diag_printf("void hal_interrupt_configure(int vector, int level, int up) entered ...\n");
634 diag_printf("vector = %d level = %d up = %d \n", vector, level, up);
637 #ifdef HAL_EXTENDED_INTERRUPT_CONFIGURE
638 // Use platform specific handling, if defined
639 // Note: this macro should do a 'return' for "extended" values of 'vector'
640 // Normal vectors are handled by code subsequent to the macro call.
641 HAL_EXTENDED_INTERRUPT_CONFIGURE(vector, level, up);
643 if (vector >= CYGNUM_HAL_INTERRUPT_GPIO64) {
647 *(unsigned long*)GRERc |= (1 << (vector - 96));
648 *(unsigned long*)GFERc |= (1 << (vector - 96));
650 // Disable both edges
651 *(unsigned long*)GRERc &= ~(1 << (vector - 96));
652 *(unsigned long*)GFERc &= ~(1 << (vector - 96));
655 // Only interested in one edge
657 // Set rising edge detect and clear falling edge detect.
658 *(unsigned long*)GRERc |= (1 << (vector - 96));
659 *(unsigned long*)GFERc &= ~(1 << (vector - 96));
661 // Set falling edge detect and clear rising edge detect.
662 *(unsigned long*)GFERc |= (1 << (vector - 96));
663 *(unsigned long*)GRERc &= ~(1 << (vector - 96));
666 } else if (vector >= CYGNUM_HAL_INTERRUPT_GPIO32) {
670 *(unsigned long*)GRERb |= (1 << (vector - 64));
671 *(unsigned long*)GFERb |= (1 << (vector - 64));
673 // Disable both edges
674 *(unsigned long*)GRERb &= ~(1 << (vector - 64));
675 *(unsigned long*)GFERb &= ~(1 << (vector - 64));
678 // Only interested in one edge
680 // Set rising edge detect and clear falling edge detect.
681 *(unsigned long*)GRERb |= (1 << (vector - 64));
682 *(unsigned long*)GFERb &= ~(1 << (vector - 64));
684 // Set falling edge detect and clear rising edge detect.
685 *(unsigned long*)GFERb |= (1 << (vector - 64));
686 *(unsigned long*)GRERb &= ~(1 << (vector - 64));
689 } else if (vector >= CYGNUM_HAL_INTERRUPT_GPIO2) {
693 *(unsigned long*)GRERa |= (1 << (vector - 32));
694 *(unsigned long*)GFERa |= (1 << (vector - 32));
696 // Disable both edges
697 *(unsigned long*)GRERa &= ~(1 << (vector - 32));
698 *(unsigned long*)GFERa &= ~(1 << (vector - 32));
701 // Only interested in one edge
703 // Set rising edge detect and clear falling edge detect.
704 *(unsigned long*)GRERa |= (1 << (vector - 32));
705 *(unsigned long*)GFERa &= ~(1 << (vector - 32));
707 // Set falling edge detect and clear rising edge detect.
708 *(unsigned long*)GFERa |= (1 << (vector - 32));
709 *(unsigned long*)GRERa &= ~(1 << (vector - 32));
712 } else if (vector == CYGNUM_HAL_INTERRUPT_GPIO0 || vector == CYGNUM_HAL_INTERRUPT_GPIO1) {
716 *(unsigned long*)GRERa |= (1 << (vector - 8));
717 *(unsigned long*)GFERa |= (1 << (vector - 8));
719 // Disable both edges
720 *(unsigned long*)GRERa &= ~(1 << (vector - 8));
721 *(unsigned long*)GFERa &= ~(1 << (vector - 8));
724 // Only interested in one edge
726 // Set rising edge detect and clear falling edge detect.
727 *(unsigned long*)GRERa |= (1 << (vector - 8));
728 *(unsigned long*)GFERa &= ~(1 << (vector - 8));
730 // Set falling edge detect and clear rising edge detect.
731 *(unsigned long*)GFERa |= (1 << (vector - 8));
732 *(unsigned long*)GRERa &= ~(1 << (vector - 8));
739 void hal_interrupt_set_level(int vector, int level)
743 /*&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*/
744 /* Command and code to reset the hardware by issuing the reset vector */
745 /*&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&*/
746 void cyg_hal_xscale_soft_reset(CYG_ADDRESS entry)
750 diag_printf("\nDoing software reset now");
752 // clear reset status
753 HAL_WRITE_UINT32(RCSR, 0x0f);
755 HAL_READ_UINT32(OSCR, value);
757 HAL_WRITE_UINT32(OSMR3, value);
758 HAL_WRITE_UINT32(OWER, 1);
759 while (1) { // wait here for watchdog reset
761 HAL_DELAY_US(10 * 1000);
765 void do_triton_reset(int argc, char *argv[])
767 HAL_PLATFORM_RESET();
771 "Reset the board/hardware",
776 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
777 /*------------------------------------------------------------------------*/
780 static inline void set_ibcr0(unsigned x)
782 asm volatile ("mcr p15,0,%0,c14,c8,0" : : "r"(x));
785 static inline unsigned get_ibcr0(void)
788 asm volatile ("mrc p15,0,%0,c14,c8,0" : "=r"(x) :);
792 static inline void set_ibcr1(unsigned x)
794 asm volatile ("mcr p15,0,%0,c14,c9,0" : : "r"(x));
797 static inline unsigned get_ibcr1(void)
800 asm volatile ("mrc p15,0,%0,c14,c9,0" : "=r"(x) :);
804 static inline void set_dbr0(unsigned x)
806 asm volatile ("mcr p15,0,%0,c14,c0,0" : : "r"(x));
809 static inline unsigned get_dbr0(void)
812 asm volatile ("mrc p15,0,%0,c14,c0,0" : "=r"(x) :);
816 static inline void set_dbr1(unsigned x)
818 asm volatile ("mcr p15,0,%0,c14,c3,0" : : "r"(x));
821 static inline unsigned get_dbr1(void)
824 asm volatile ("mrc p15,0,%0,c14,c3,0" : "=r"(x) :);
828 static inline void set_dbcon(unsigned x)
830 asm volatile ("mcr p15,0,%0,c14,c4,0" : : "r"(x));
833 static inline unsigned get_dbcon(void)
836 asm volatile ("mrc p15,0,%0,c14,c4,0" : "=r"(x) :);
840 static inline void set_dcsr(unsigned x)
842 asm volatile ("mcr p14,0,%0,c10,c0,0" : : "r"(x));
845 static inline unsigned get_dcsr(void)
848 asm volatile ("mrc p14,0,%0,c10,c0,0" : "=r"(x) :);
852 int cyg_hal_plf_hw_breakpoint(int setflag, void *vaddr, int len)
854 unsigned int addr = (unsigned)vaddr;
857 if (!(get_ibcr0() & 1))
859 else if (!(get_ibcr1() & 1))
864 unsigned x = (addr | 1);
865 if (get_ibcr0() == x)
867 else if (get_ibcr0() == x)
875 int cyg_hal_plf_hw_watchpoint(int setflag, void *vaddr, int len, int type)
877 unsigned int mask, bit_nr, mode, addr = (unsigned)vaddr;
878 unsigned dbcon = get_dbcon();
888 mask = ~(0xffffffff << bit_nr);
891 /* set a watchpoint */
893 mode = 1; // break on write
895 mode = 3; // break on read
897 mode = 2; // break on any access
904 set_dbcon(dbcon | mode | 0x100);
908 /* clear a watchpoint */
910 set_dbcon(dbcon & ~3);
917 // Return indication of whether or not we stopped because of a
918 // watchpoint or hardware breakpoint. If stopped by a watchpoint,
919 // also set '*data_addr_p' to the data address which triggered the
921 int cyg_hal_plf_is_stopped_by_hardware(void **data_addr_p)
923 unsigned fsr, dcsr, dbcon, kind = 0;
925 // Check for debug event
926 asm volatile ("mrc p15,0,%0,c5,c0,0" : "=r"(fsr) :);
927 if ((fsr & 0x200) == 0)
928 return HAL_STUB_HW_STOP_NONE;
930 // There was a debug event. Check the MOE for details
932 switch ((dcsr >> 2) & 7) {
933 case 1: // HW breakpoint
934 return HAL_STUB_HW_STOP_BREAK;
935 case 2: // Watchpoint
938 // dbr1 is used as address mask
940 *data_addr_p = (void *)get_dbr0();
943 return HAL_STUB_HW_STOP_WATCH;
945 return HAL_STUB_HW_STOP_AWATCH;
947 return HAL_STUB_HW_STOP_RWATCH;
948 // should never get here
951 return HAL_STUB_HW_STOP_NONE;
953 #endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
955 #define SCL_LOW (unsigned char)0x00
956 #define SCL_HIGH (unsigned char)0x01
957 #define SDA_LOW (unsigned char)0x00
958 #define SDA_HIGH (unsigned char)0x02
959 #define I2C_WRITE (unsigned char)0x00
960 #define I2C_READ (unsigned char)0x01
962 #define WRITE_REG32(__regadr, __val) ((__regadr) = (__val))
963 #define READ_REG32(__regadr) (__regadr)
965 #define PXA250_AFREG_BASE 0x40e00054
966 #define PXA250_PINDIR_BASE 0x40e0000c
967 #define PXA250_PINSET_BASE 0x40e00018
968 #define PXA250_PINCLEAR_BASE 0x40e00024
969 #define PXA250_REDGE_BASE 0x40e00030
970 #define PXA250_FEDGE_BASE 0x40e0003c
971 #define PXA250_DEDGE_BASE 0x40e00048
972 #define PXA250_PINLEVEL_BASE 0x40e00000
974 void pin_i2c_setup(pin_i2c_t *pin_data)
976 // configure pins as GPIO function
977 set_alternate_function((unsigned char)pin_data->scl_no, 0);
978 set_alternate_function((unsigned char)pin_data->sda_no, 0);
980 // set both pins to input
981 set_pin_dir((unsigned char)pin_data->scl_no, 0); /* 0=input 1=output */
982 set_pin_dir((unsigned char)pin_data->sda_no, 0); /* 0=input 1=output */
984 // clear all output registers
985 clear_pin((unsigned char)pin_data->scl_no);
986 clear_pin((unsigned char)pin_data->sda_no);
989 void bus_out(pin_i2c_t *pin_data, unsigned char pdata)
991 switch (pdata & 0x03) {
993 set_pin_dir((unsigned char)pin_data->scl_no, 1); /* 0=input 1=output */
994 set_pin_dir((unsigned char)pin_data->sda_no, 1); /* 0=input 1=output */
997 set_pin_dir((unsigned char)pin_data->scl_no, 0); /* 0=input 1=output */
998 set_pin_dir((unsigned char)pin_data->sda_no, 1); /* 0=input 1=output */
1001 set_pin_dir((unsigned char)pin_data->scl_no, 1); /* 0=input 1=output */
1002 set_pin_dir((unsigned char)pin_data->sda_no, 0); /* 0=input 1=output */
1005 set_pin_dir((unsigned char)pin_data->scl_no, 0); /* 0=input 1=output */
1006 set_pin_dir((unsigned char)pin_data->sda_no, 0); /* 0=input 1=output */
1012 int bus_in(pin_i2c_t *pin_data)
1016 result = get_pin_status((unsigned char)pin_data->sda_no);
1018 //dprintf("get_pin_status returned error \n");
1025 void i2c_start(pin_i2c_t *pin_data)
1027 //dprintf("pin status is %d\n", get_pin_status((unsigned char)pin_data->sda_no));
1029 bus_out(pin_data, SCL_HIGH | SDA_LOW);
1032 bus_out(pin_data, SCL_HIGH | SDA_HIGH);
1035 bus_out(pin_data, SCL_HIGH | SDA_LOW);
1038 bus_out(pin_data, SCL_LOW | SDA_LOW);
1042 void i2c_stop(pin_i2c_t *pin_data)
1044 bus_out(pin_data, SCL_LOW | SDA_LOW);
1046 bus_out(pin_data, SCL_HIGH | SDA_LOW);
1048 bus_out(pin_data, SCL_HIGH | SDA_HIGH);
1052 int i2c_read_ack(pin_i2c_t *pin_data)
1054 bus_out(pin_data, SCL_LOW | SDA_HIGH);
1056 bus_out(pin_data, SCL_HIGH | SDA_HIGH);
1058 if (bus_in(pin_data)) {
1059 bus_out(pin_data, SCL_LOW | SDA_HIGH);
1063 bus_out(pin_data, SCL_LOW | SDA_HIGH);
1069 void i2c_write_ack(pin_i2c_t *pin_data)
1071 bus_out(pin_data, SCL_LOW | SDA_LOW);
1073 bus_out(pin_data, SCL_HIGH | SDA_LOW);
1075 bus_out(pin_data, SCL_LOW | SDA_LOW);
1079 void i2c_write_nack(pin_i2c_t *pin_data)
1081 bus_out(pin_data, SCL_LOW | SDA_HIGH);
1083 bus_out(pin_data, SCL_HIGH | SDA_HIGH);
1085 bus_out(pin_data, SCL_LOW | SDA_HIGH);
1089 void i2c_slave_addr(pin_i2c_t *pin_data, unsigned char dev, unsigned char mode)
1091 i2c_write(pin_data, dev | mode);
1094 void i2c_read(pin_i2c_t *pin_data, unsigned char *res)
1096 unsigned char in = 0;
1097 unsigned char bit = 0x80;
1100 bus_out(pin_data, SCL_LOW | SDA_HIGH);
1102 bus_out(pin_data, SCL_HIGH | SDA_HIGH);
1104 if (bus_in(pin_data))
1106 bus_out(pin_data, SCL_LOW | SDA_HIGH);
1113 void i2c_write(pin_i2c_t *pin_data, unsigned char val)
1116 unsigned char bit = 0x80;
1119 out = (bit & val) ? SDA_HIGH : SDA_LOW;
1120 bus_out(pin_data, SCL_LOW | out);
1122 bus_out(pin_data, SCL_HIGH | out);
1124 bus_out(pin_data, SCL_LOW | out);
1130 /* ================================================================ */
1134 paramters: unsigned char addr start address in ser. EEPROM
1135 unsigned int numb number of bytes to be read
1136 char *dat pointer to data buffer
1138 ret. val.: int = 0, every thing ok
1139 else, device not av., or not ready
1142 int se_read(pin_i2c_t *pin_data, unsigned char addr, unsigned char dev_address,
1143 unsigned int numb, char *dat)
1147 i2c_start(pin_data);
1148 i2c_slave_addr(pin_data, dev_address, I2C_WRITE);
1149 if (i2c_read_ack(pin_data) < 0) {
1153 i2c_write(pin_data, addr); /* read from start address */
1154 if (i2c_read_ack(pin_data) < 0) {
1159 i2c_start(pin_data);
1160 i2c_slave_addr(pin_data, dev_address, I2C_READ);
1161 if (i2c_read_ack(pin_data) < 0) {
1166 for (i = 0; i < numb - 1; i++) {
1167 i2c_read(pin_data, dat++);
1168 i2c_write_ack(pin_data);
1170 i2c_read(pin_data, dat);
1176 /* ================================================================ */
1180 paramters: unsigned char addr start address in ser. EEPROM
1181 unsigned char val value to write
1183 ret. val.: int = 0, every thing ok
1184 else, device not av., or not ready
1187 int se_write(pin_i2c_t *pin_data, unsigned char addr,unsigned char dev_address, unsigned char val)
1189 i2c_start(pin_data);
1190 i2c_slave_addr(pin_data, dev_address, I2C_WRITE);
1191 if (i2c_read_ack(pin_data) < 0) {
1195 i2c_write(pin_data, addr);
1196 if (i2c_read_ack(pin_data) < 0) {
1200 i2c_write(pin_data, val);
1201 if (i2c_read_ack(pin_data) < 0) {
1206 HAL_DELAY_US(10000);
1210 /* ================================================================ */
1212 function: ltc1663_pwrite
1214 paramters: unsigned dev_address device address of chip
1215 unsigned char command command byte
1216 unsigned short val value to write
1218 ret. val.: int = 0, every thing ok
1219 else, device not av., or not ready
1222 int ltc1663_write(pin_i2c_t *pin_data, unsigned char dev_address, unsigned char command,
1225 i2c_start(pin_data);
1226 i2c_slave_addr(pin_data, dev_address, I2C_WRITE);
1227 if (i2c_read_ack(pin_data) < 0) {
1231 i2c_write(pin_data, command);
1232 if (i2c_read_ack(pin_data) < 0) {
1236 i2c_write(pin_data, (unsigned char)val&0xff);
1237 if (i2c_read_ack(pin_data) < 0) {
1241 i2c_write(pin_data, (unsigned char)((val&0xff00)>>8));
1242 if (i2c_read_ack(pin_data) < 0) {
1251 // -----------------------------------------------------------------------
1252 int set_alternate_function(unsigned char gpio_number, unsigned char function_code)
1254 unsigned int register_offset;
1255 unsigned int bit_offset;
1257 unsigned long reg_adr;
1258 unsigned long org_value;
1259 unsigned long new_value;
1262 if (gpio_number >= NUM_GPIOS) {
1263 //dprintf("GPIO pin number %d is out of range!\n", gpio_number);
1267 if (function_code > 3) {
1268 //dprintf("GPIO alternate function code %d is out of range\n", function_code);
1272 register_offset = gpio_number / 16;
1274 bit_offset = gpio_number % 16;
1275 mask = 3 << (bit_offset*2);
1277 reg_adr = PXA250_AFREG_BASE + register_offset * 4;
1279 org_value = READ_REG32(reg_adr);
1281 new_value = (org_value & (~mask)) | (function_code << (bit_offset*2));
1283 WRITE_REG32(reg_adr, new_value);
1287 int set_pin_dir(unsigned char gpio_number, unsigned char dir_code)
1289 unsigned int register_offset;
1290 unsigned int bit_offset;
1292 unsigned long reg_adr;
1293 unsigned long org_value;
1294 unsigned long new_value;
1297 if (gpio_number >= NUM_GPIOS) {
1298 //dprintf("GPIO pin number %d is out of range!\n", gpio_number);
1303 //dprintf("GPIO alternate function code %d is out of range\n", dir_code);
1307 register_offset = gpio_number / 32;
1309 bit_offset = gpio_number % 32;
1310 mask = 1 << (bit_offset);
1312 reg_adr = PXA250_PINDIR_BASE + register_offset * 4;
1314 org_value = READ_REG32(reg_adr);
1316 new_value = (org_value & (~mask)) | (dir_code << (bit_offset));
1318 WRITE_REG32(reg_adr, new_value);
1322 int set_rising_edge(unsigned char gpio_number, unsigned char edge_code)
1324 unsigned int register_offset;
1325 unsigned int bit_offset;
1327 unsigned long reg_adr;
1328 unsigned long org_value;
1329 unsigned long new_value;
1332 if (gpio_number >= NUM_GPIOS) {
1333 //dprintf("GPIO pin number %d is out of range!\n", gpio_number);
1336 if (edge_code > 1) {
1337 //dprintf("rising edge value sould be 0 or 1, not %d\n", edge_code);
1340 register_offset = gpio_number / 32;
1342 bit_offset = gpio_number % 32;
1343 mask = 1 << (bit_offset);
1345 reg_adr = PXA250_REDGE_BASE + register_offset * 4;
1347 org_value = READ_REG32(reg_adr);
1349 new_value = (org_value & (~mask)) | (edge_code << (bit_offset));
1350 WRITE_REG32(reg_adr, new_value);
1354 int set_falling_edge(unsigned char gpio_number, unsigned char edge_code)
1356 unsigned int register_offset;
1357 unsigned int bit_offset;
1359 unsigned long reg_adr;
1360 unsigned long org_value;
1361 unsigned long new_value;
1364 if (gpio_number >= NUM_GPIOS) {
1365 //dprintf("GPIO pin number %d is out of range!\n", gpio_number);
1369 if (edge_code > 1) {
1370 //dprintf("falling edge value sould be 0 or 1, not %d\n", edge_code);
1374 register_offset = gpio_number / 32;
1376 bit_offset = gpio_number % 32;
1377 mask = 1 << (bit_offset);
1379 reg_adr = PXA250_FEDGE_BASE + register_offset * 4;
1381 org_value = READ_REG32(reg_adr);
1383 new_value = (org_value & (~mask)) | (edge_code << (bit_offset));
1384 WRITE_REG32(reg_adr, new_value);
1388 int set_pin(unsigned char gpio_number)
1390 unsigned int register_offset;
1391 unsigned int bit_offset;
1393 unsigned long reg_adr;
1394 unsigned long org_value;
1395 unsigned long new_value;
1398 if (gpio_number >= NUM_GPIOS) {
1399 //dprintf("GPIO pin number %d is out of range!\n", gpio_number);
1403 register_offset = gpio_number / 32;
1405 bit_offset = gpio_number % 32;
1406 mask = 1 << (bit_offset);
1408 reg_adr = PXA250_PINSET_BASE + register_offset * 4;
1412 new_value = (org_value & (~mask)) | (1 << (bit_offset));
1414 WRITE_REG32(reg_adr, new_value);
1419 int clear_pin(unsigned char gpio_number)
1421 unsigned int register_offset;
1422 unsigned int bit_offset;
1424 unsigned long reg_adr;
1425 unsigned long org_value;
1426 unsigned long new_value;
1429 if (gpio_number >= NUM_GPIOS) {
1430 //dprintf("GPIO pin number %d is out of range!\n", gpio_number);
1434 register_offset = gpio_number / 32;
1436 bit_offset = gpio_number % 32;
1437 mask = 1 << (bit_offset);
1439 reg_adr = PXA250_PINCLEAR_BASE + register_offset * 4;
1443 new_value = (org_value & (~mask)) | (1 << (bit_offset));
1445 WRITE_REG32(reg_adr, new_value);
1450 int get_pin_status(unsigned char gpio_number)
1452 unsigned int register_offset;
1453 unsigned int bit_offset;
1455 unsigned long reg_adr;
1456 unsigned long return_value;
1459 if (gpio_number >= NUM_GPIOS) {
1460 //dprintf("GPIO pin number %d is out of range!\n", gpio_number);
1464 register_offset = gpio_number / 32;
1466 bit_offset = gpio_number % 32;
1467 mask = 1 << (bit_offset);
1469 reg_adr = PXA250_PINLEVEL_BASE + register_offset * 4;
1471 return_value = (READ_REG32(reg_adr) & mask) >> bit_offset;
1473 return return_value;
1476 int clear_edge(unsigned char gpio_number)
1478 unsigned int register_offset;
1479 unsigned int bit_offset;
1481 unsigned long reg_adr;
1482 unsigned long org_value;
1483 unsigned long new_value;
1486 if (gpio_number >= NUM_GPIOS) {
1487 //dprintf("GPIO pin number %d is out of range!\n", gpio_number);
1491 register_offset = gpio_number / 32;
1493 bit_offset = gpio_number % 32;
1494 mask = 1 << (bit_offset);
1496 reg_adr = PXA250_DEDGE_BASE + register_offset * 4;
1498 org_value = READ_REG32(reg_adr);
1500 new_value = (org_value & (~mask)) | (1 << (bit_offset));
1501 WRITE_REG32(reg_adr, new_value);
1506 int detect_edge(unsigned char gpio_number)
1508 unsigned int register_offset;
1509 unsigned int bit_offset;
1511 unsigned long reg_adr;
1512 unsigned long org_value;
1515 if (gpio_number >= NUM_GPIOS) {
1516 //dprintf("GPIO pin number %d is out of range!\n", gpio_number);
1520 register_offset = gpio_number / 32;
1522 bit_offset = gpio_number % 32;
1523 mask = 1 << (bit_offset);
1525 reg_adr = PXA250_DEDGE_BASE + register_offset * 4;
1527 org_value = READ_REG32(reg_adr);
1529 return !!(org_value & mask);
1534 HAL_WRITE_UINT32(ICR, ICR_UR); // reset i2c_unit;
1535 HAL_WRITE_UINT32(ICR, ICR_IUE | ICR_SCLE | ICR_GCD);
1538 //FIXME: insert timeout into while loop
1539 cyg_int32 write_i2c_pcf8574(cyg_uint8 device_adr, cyg_uint8 dat_value)
1542 unsigned int retries;
1544 // write device address now
1545 HAL_WRITE_UINT32(IDBR, (device_adr & 0xfe));
1546 HAL_READ_UINT32(ICR, value);
1547 value = value & ~(ICR_STOP | ICR_ALDIE);
1548 HAL_WRITE_UINT32(ICR, value | ICR_START | ICR_TB);
1550 HAL_READ_UINT32(ISR, value);
1552 while (!value) { // wait for Transmit Empty
1553 HAL_READ_UINT32(ISR, value);
1556 HAL_READ_UINT32(ISR, value);
1557 if (value & ISR_BED) {
1559 //diag_printf("I2C: bus error, status after write device address is: %06X\n", value);
1560 HAL_READ_UINT32(ICR, value);
1561 HAL_WRITE_UINT32(ICR, value | ICR_MA); // send master abort
1562 HAL_DELAY_US(10000);
1563 HAL_WRITE_UINT32(ICR, value & ~ICR_MA);
1566 HAL_WRITE_UINT32(ISR, ISR_ITE); // clear ITE status
1569 HAL_WRITE_UINT32(IDBR, (dat_value & 0xff));
1570 HAL_READ_UINT32(ICR, value);
1571 value &= ~ICR_START;
1572 HAL_WRITE_UINT32(ICR, value | ICR_TB | ICR_STOP);
1574 HAL_READ_UINT32(ISR, value);
1576 while (!(value & ISR_ITE)) { // wait for Transmit Empty
1577 HAL_READ_UINT32(ISR, value);
1579 if (!(value & ISR_ITE)) {
1580 diag_printf("I2C: timeout waiting for ITE\n");
1583 if (value & ISR_BED) {
1584 //diag_printf("I2C: bus error, status after write device address is: %06X\n", value);
1585 HAL_READ_UINT32(ICR, value);
1586 HAL_WRITE_UINT32(ICR, value | ICR_MA); // send master abort
1587 HAL_DELAY_US(10000);
1588 HAL_WRITE_UINT32(ICR, value & ~ICR_MA);
1591 HAL_WRITE_UINT32(ISR, ISR_ITE); // clear ITE status
1593 HAL_READ_UINT32(ICR, value);
1594 value = value & ~(ICR_STOP | ICR_START | ICR_TB);
1595 HAL_WRITE_UINT32(ICR, value);
1600 //FIXME: insert timeout into while loop
1601 cyg_int32 read_i2c_pcf8574(cyg_uint8 device_adr)
1604 unsigned int retries;
1606 // write device address now
1607 HAL_WRITE_UINT32(IDBR, (device_adr | 0x01));
1609 HAL_READ_UINT32(ICR, value);
1611 HAL_WRITE_UINT32(ICR, value | ICR_START | ICR_TB);
1613 HAL_READ_UINT32(ISR, value);
1615 while (!(value & ISR_ITE)) { // wait for Transmit Empty
1616 HAL_READ_UINT32(ISR, value);
1618 if (!(value & ISR_ITE)) {
1619 diag_printf("I2C: timeout waiting for ITE\n");
1622 if (value & ISR_BED) {
1623 //diag_printf("I2C: bus error, status after write device address is: %06X\n", value);
1624 HAL_READ_UINT32(ICR, value);
1625 HAL_WRITE_UINT32(ICR, value | ICR_MA); // send master abort
1626 HAL_DELAY_US(10000);
1627 HAL_WRITE_UINT32(ICR, value & ~ICR_MA);
1630 HAL_WRITE_UINT32(ISR, ISR_ITE); // clear ITE status
1633 HAL_READ_UINT32(ICR, value);
1634 value &= ~ICR_START;
1635 HAL_WRITE_UINT32(ICR, value |ICR_TB | ICR_STOP | ICR_ACKNAK);
1637 HAL_READ_UINT32(ISR, value);
1639 while (!value) { // wait for Receive Buffer full
1640 HAL_READ_UINT32(ISR, value);
1644 HAL_WRITE_UINT32(ISR, ISR_IRF); // clear ITE status
1646 HAL_READ_UINT32(ICR, value);
1647 value = value & ~(ICR_STOP | ICR_START | ICR_TB | ICR_ACKNAK);
1648 HAL_WRITE_UINT32(ICR, value);
1650 HAL_READ_UINT32(IDBR, value);
1652 return value & 0xff;
1654 /*------------------------------------------------------------------------*/
1655 // EOF triton270_misc.c