packages/hal/h8300/arch/v2_0/include/hal_intr.h

   1 #ifndef CYGONCE_HAL_HAL_INTR_H
   2 #define CYGONCE_HAL_HAL_INTR_H
   3 //==========================================================================
   4 //
   5 //      hal_intr.h
   6 //
   7 //      HAL Interrupt and clock support
   8 //
   9 //==========================================================================
  10 //####ECOSGPLCOPYRIGHTBEGIN####
  11 // -------------------------------------------
  12 // This file is part of eCos, the Embedded Configurable Operating System.
  13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  14 //
  15 // eCos is free software; you can redistribute it and/or modify it under
  16 // the terms of the GNU General Public License as published by the Free
  17 // Software Foundation; either version 2 or (at your option) any later version.
  18 //
  19 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  20 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  21 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  22 // for more details.
  23 //
  24 // You should have received a copy of the GNU General Public License along
  25 // with eCos; if not, write to the Free Software Foundation, Inc.,
  26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  27 //
  28 // As a special exception, if other files instantiate templates or use macros
  29 // or inline functions from this file, or you compile this file and link it
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  32 // License. However the source code for this file must still be made available
  33 // in accordance with section (3) of the GNU General Public License.
  34 //
  35 // This exception does not invalidate any other reasons why a work based on
  36 // this file might be covered by the GNU General Public License.
  37 //
  38 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  39 // at http://sources.redhat.com/ecos/ecos-license/
  40 // -------------------------------------------
  41 //####ECOSGPLCOPYRIGHTEND####
  42 //==========================================================================
  43 //#####DESCRIPTIONBEGIN####
  44 //
  45 // Author(s):    yoshinori sato
  46 // Contributors: yoshinori sato
  47 // Date:         2002-02-13
  48 // Purpose:      Define Interrupt support
  49 // Description:  The macros defined here provide the HAL APIs for handling
  50 //               interrupts and the clock.
  51 // Usage:
  52 //               #include <cyg/hal/hal_intr.h>
  53 //               ...
  54 //
  55 //
  56 //####DESCRIPTIONEND####
  57 //
  58 //==========================================================================
  59
  60 #include <pkgconf/hal.h>
  61
  62 #include <cyg/infra/cyg_type.h>
  63 #include <cyg/hal/hal_io.h>
  64
  65 #include <cyg/hal/var_intr.h>
  66
  67 //--------------------------------------------------------------------------
  68 // Static data used by HAL
  69
  70 // ISR tables
  71 externC volatile CYG_ADDRESS    hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
  72 externC volatile CYG_ADDRWORD   hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
  73 externC volatile CYG_ADDRESS    hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
  74
  75 // VSR table
  76 externC volatile CYG_ADDRESS    hal_vsr_table[CYGNUM_HAL_VSR_COUNT];
  77
  78 //--------------------------------------------------------------------------
  79 // Default ISR
  80 // The #define is used to test whether this routine exists, and to allow
  81 // us to call it.
  82
  83 externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
  84
  85 #define HAL_DEFAULT_ISR hal_default_isr
  86
  87 //--------------------------------------------------------------------------
  88 // Interrupt state storage
  89
  90 typedef cyg_uint32 CYG_INTERRUPT_STATE;
  91
  92 //--------------------------------------------------------------------------
  93
  94 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
  95
  96 // Routine to execute DSRs using separate interrupt stack
  97 externC void hal_interrupt_stack_call_pending_DSRs(void);
  98 #define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
  99     hal_interrupt_stack_call_pending_DSRs()
 100
 101 // these are offered solely for stack usage testing
 102 // if they are not defined, then there is no interrupt stack.
 103 #define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
 104 #define HAL_INTERRUPT_STACK_TOP  cyg_interrupt_stack
 105 // use them to declare these extern however you want:
 106 //       extern char HAL_INTERRUPT_STACK_BASE[];
 107 //       extern char HAL_INTERRUPT_STACK_TOP[];
 108 // is recommended
 109
 110 #endif
 111
 112
 113 #ifndef HAL_TRANSLATE_VECTOR
 114
 115 #define HAL_TRANSLATE_VECTOR(_vector_,_index_) _index_ = (_vector_)
 116
 117 #endif
 118
 119 //--------------------------------------------------------------------------
 120 // Interrupt and VSR attachment macros
 121
 122 #define HAL_INTERRUPT_IN_USE( _vector_, _state_)                                \
 123 CYG_MACRO_START                                                                 \
 124     cyg_uint32 _index_;                                                         \
 125     HAL_TRANSLATE_VECTOR ((_vector_), _index_);                                 \
 126                                                                                 \
 127     if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR )       \
 128         (_state_) = 0;                                                          \
 129     else                                                                        \
 130         (_state_) = 1;                                                          \
 131 CYG_MACRO_END
 132
 133 #define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ )               \
 134 CYG_MACRO_START                                                                 \
 135     cyg_uint32 _index_;                                                         \
 136     HAL_TRANSLATE_VECTOR(_vector_,_index_);                                     \
 137                                                                                 \
 138     if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR )       \
 139     {                                                                           \
 140         hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_;                   \
 141         hal_interrupt_data[_index_] = (CYG_ADDRWORD)_data_;                     \
 142         hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_;                 \
 143     }                                                                           \
 144 CYG_MACRO_END
 145
 146 #define HAL_INTERRUPT_DETACH( _vector_, _isr_ )                         \
 147 CYG_MACRO_START                                                         \
 148     cyg_uint32 _index_;                                                 \
 149     HAL_TRANSLATE_VECTOR(_vector_,_index_);                             \
 150                                                                         \
 151     if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ )         \
 152     {                                                                   \
 153         hal_interrupt_handlers[_index_] = (CYG_ADDRESS)HAL_DEFAULT_ISR; \
 154         hal_interrupt_data[_index_] = 0;                                \
 155         hal_interrupt_objects[_index_] = 0;                             \
 156     }                                                                   \
 157 CYG_MACRO_END
 158
 159 #define HAL_VSR_GET( _vector_, _pvsr_ )                                 \
 160     *((CYG_ADDRESS *)_pvsr_) = hal_vsr_table[_vector_];
 161
 162
 163 #define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ )                       \
 164     if( _poldvsr_ != NULL )                                             \
 165         *(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_];            \
 166     hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_;
 167
 168
 169 //--------------------------------------------------------------------------
 170 // Interrupt controller access
 171 // Read interrupt control registers back after writing to them. This
 172 // ensures that the written value is not sitting in the store buffers
 173 // when interrupts are re-enabled.
 174
 175 #define HAL_INTERRUPT_MASK( _vector_ )                          \
 176         hal_interrupt_mask( _vector_ )
 177
 178 #define HAL_INTERRUPT_UNMASK( _vector_ )                        \
 179         hal_interrupt_unmask( _vector_ )
 180
 181 #define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ )                   \
 182         hal_interrupt_acknowledge( _vector_ )
 183
 184 #if !defined(HAL_INTERRUPT_CONFIGURE)
 185
 186 #error HAL_INTERRUPT_CONFIGURE not defined by variant
 187
 188 #endif
 189
 190 #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )            \
 191         hal_interrupt_set_level( _vector_, _level_ )
 192
 193
 194 externC void hal_interrupt_mask(int vector);
 195 externC void hal_interrupt_unmask(int vector);
 196 externC void hal_interrupt_acknowledge(int vector);
 197 externC void hal_interrupt_set_level(int vector,int level);
 198 //--------------------------------------------------------------------------
 199 // Clock control.
 200 // This is almost all handled in the var_intr.h.
 201
 202 #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
 203 #define HAL_CLOCK_LATENCY(_pvalue_) HAL_CLOCK_READ(_pvalue_)
 204 #endif
 205
 206 //--------------------------------------------------------------------------
 207 #endif // ifndef CYGONCE_HAL_HAL_INTR_H
 208 // EOF hal_intr.h