1 #ifndef CYGONCE_HAL_HAL_IO_H
2 #define CYGONCE_HAL_HAL_IO_H
4 //=============================================================================
8 // HAL device IO register support.
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
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41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //=============================================================================
44 //#####DESCRIPTIONBEGIN####
46 // Author(s): yoshinori sato
47 // Contributors: yoshinori sato
49 // Purpose: Define IO register support
50 // Description: The macros defined here provide the HAL APIs for handling
51 // device IO control registers.
54 // #include <cyg/hal/hal_io.h>
58 //####DESCRIPTIONEND####
60 //=============================================================================
62 #include <cyg/infra/cyg_type.h>
63 #if defined(CYGBLD_HAL_PLATFORM_IO_H)
64 #include CYGBLD_HAL_PLATFORM_IO_H
67 //-----------------------------------------------------------------------------
68 // IO Register address.
69 // This type is for recording the address of an IO register.
71 typedef volatile CYG_ADDRWORD HAL_IO_REGISTER;
73 //-----------------------------------------------------------------------------
74 // BYTE Register access.
75 // Individual and vectorized access to 8 bit registers.
77 #define HAL_READ_UINT8( _register_, _value_ ) \
78 ((_value_) = *((volatile CYG_BYTE *)(_register_)))
80 #define HAL_WRITE_UINT8( _register_, _value_ ) \
81 (*((volatile CYG_BYTE *)(_register_)) = (_value_))
83 #define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
85 cyg_count32 _i_,_j_; \
86 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
87 (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_]; \
90 #define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
92 cyg_count32 _i_,_j_; \
93 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
94 ((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_]; \
98 //-----------------------------------------------------------------------------
100 // Individual and vectorized access to 16 bit registers.
102 #define HAL_READ_UINT16( _register_, _value_ ) \
103 ((_value_) = *((volatile CYG_WORD16 *)(_register_)))
105 #define HAL_WRITE_UINT16( _register_, _value_ ) \
106 (*((volatile CYG_WORD16 *)(_register_)) = (_value_))
108 #define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
110 cyg_count32 _i_,_j_; \
111 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
112 (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_]; \
115 #define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
117 cyg_count32 _i_,_j_; \
118 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
119 ((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_]; \
122 //-----------------------------------------------------------------------------
124 // Individual and vectorized access to 32 bit registers.
126 #define HAL_READ_UINT32( _register_, _value_ ) \
127 ((_value_) = *((volatile CYG_WORD32 *)(_register_)))
129 #define HAL_WRITE_UINT32( _register_, _value_ ) \
130 (*((volatile CYG_WORD32 *)(_register_)) = (_value_))
132 #define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
134 cyg_count32 _i_,_j_; \
135 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
136 (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_]; \
139 #define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
141 cyg_count32 _i_,_j_; \
142 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
143 ((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_]; \
146 //-----------------------------------------------------------------------------
147 #endif // ifndef CYGONCE_HAL_HAL_IO_H