packages/hal/h8300/h8300h/v2_0/include/var_intr.h

   1 #ifndef CYGONCE_HAL_VAR_INTR_H
   2 #define CYGONCE_HAL_VAR_INTR_H
   3
   4 //==========================================================================
   5 //
   6 //      var_intr.h
   7 //
   8 //      H8/300H Interrupt and clock support
   9 //
  10 //==========================================================================
  11 //####ECOSGPLCOPYRIGHTBEGIN####
  12 // -------------------------------------------
  13 // This file is part of eCos, the Embedded Configurable Operating System.
  14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  15 //
  16 // eCos is free software; you can redistribute it and/or modify it under
  17 // the terms of the GNU General Public License as published by the Free
  18 // Software Foundation; either version 2 or (at your option) any later version.
  19 //
  20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  22 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  23 // for more details.
  24 //
  25 // You should have received a copy of the GNU General Public License along
  26 // with eCos; if not, write to the Free Software Foundation, Inc.,
  27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  28 //
  29 // As a special exception, if other files instantiate templates or use macros
  30 // or inline functions from this file, or you compile this file and link it
  31 // with other works to produce a work based on this file, this file does not
  32 // by itself cause the resulting work to be covered by the GNU General Public
  33 // License. However the source code for this file must still be made available
  34 // in accordance with section (3) of the GNU General Public License.
  35 //
  36 // This exception does not invalidate any other reasons why a work based on
  37 // this file might be covered by the GNU General Public License.
  38 //
  39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  40 // at http://sources.redhat.com/ecos/ecos-license/
  41 // -------------------------------------------
  42 //####ECOSGPLCOPYRIGHTEND####
  43 //==========================================================================
  44 //#####DESCRIPTIONBEGIN####
  45 //
  46 // Author(s):    yoshinori sato
  47 // Contributors: yoshinori sato
  48 // Date:         2002-02-14
  49 // Purpose:      H8/300H Interrupt Support
  50 // Description:  The macros defined here provide the HAL APIs for handling
  51 //               interrupts and the clock for H8/300H variants of the H8/300
  52 //               architecture.
  53 //
  54 // Usage:
  55 //              #include <cyg/hal/var_intr.h>
  56 //              ...
  57 //
  58 //
  59 //####DESCRIPTIONEND####
  60 //
  61 //==========================================================================
  62
  63 #include <pkgconf/hal.h>
  64
  65 #include <cyg/infra/cyg_type.h>
  66
  67 #include <cyg/hal/plf_intr.h>
  68 #include <cyg/hal/var_arch.h>
  69
  70 //--------------------------------------------------------------------------
  71 // Interrupt vectors.
  72
  73 // The level-specific hardware vectors
  74 // These correspond to VSRs and are the values to use for HAL_VSR_GET/SET
  75 #define CYGNUM_HAL_VECTOR_RESET                0
  76 #define CYGNUM_HAL_VECTOR_RSV1                 1
  77 #define CYGNUM_HAL_VECTOR_RSV2                 2
  78 #define CYGNUM_HAL_VECTOR_RSV3                 3
  79 #define CYGNUM_HAL_VECTOR_RSV4                 4
  80 #define CYGNUM_HAL_VECTOR_RSV5                 5
  81 #define CYGNUM_HAL_VECTOR_RSV6                 6
  82 #define CYGNUM_HAL_VECTOR_NMI                  7
  83 #define CYGNUM_HAL_VECTOR_TRAP0                8
  84 #define CYGNUM_HAL_VECTOR_TRAP1                9
  85 #define CYGNUM_HAL_VECTOR_TRAP2                10
  86 #define CYGNUM_HAL_VECTOR_TRAP3                11
  87
  88 #define CYGNUM_HAL_VSR_MIN                     0
  89 #define CYGNUM_HAL_VSR_MAX                     11
  90 #define CYGNUM_HAL_VSR_COUNT                   12
  91
  92 // Exception numbers. These are the values used when passed out to an
  93 // external exception handler using cyg_hal_deliver_exception()
  94
  95 #define CYGNUM_HAL_EXCEPTION_NMI               CYGNUM_HAL_VECTOR_NMI
  96
  97 #if 0
  98 #define CYGNUM_HAL_EXCEPTION_DATA_ACCESS       0
  99 #endif
 100
 101 #define CYGNUM_HAL_EXCEPTION_MIN               CYGNUM_HAL_VSR_MIN
 102 #define CYGNUM_HAL_EXCEPTION_MAX               CYGNUM_HAL_VSR_MAX
 103 #define CYGNUM_HAL_EXCEPTION_COUNT             CYGNUM_HAL_VSR_COUNT
 104
 105 // The decoded interrupts
 106 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_0        12
 107 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_1        13
 108 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_2        14
 109 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_3        15
 110 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_4        16
 111 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_5        17
 112 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_6        18
 113 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_7        19
 114
 115 #define CYGNUM_HAL_INTERRUPT_WDT               20
 116 #define CYGNUM_HAL_INTERRUPT_RFSHCMI           21
 117 #define CYGNUM_HAL_INTERRUPT_RSV22             22
 118 #define CYGNUM_HAL_INTERRUPT_ADI               23
 119
 120 #define CYGNUM_HAL_INTERRUPT_IMIA0             24
 121 #define CYGNUM_HAL_INTERRUPT_IMIB0             25
 122 #define CYGNUM_HAL_INTERRUPT_OVI0              26
 123 #define CYGNUM_HAL_INTERRUPT_RSV27             27
 124
 125 #define CYGNUM_HAL_INTERRUPT_IMIA1             28
 126 #define CYGNUM_HAL_INTERRUPT_IMIB1             29
 127 #define CYGNUM_HAL_INTERRUPT_OVI1              30
 128 #define CYGNUM_HAL_INTERRUPT_RSV31             31
 129
 130 #define CYGNUM_HAL_INTERRUPT_IMIA2             32
 131 #define CYGNUM_HAL_INTERRUPT_IMIB2             33
 132 #define CYGNUM_HAL_INTERRUPT_OVI2              34
 133 #define CYGNUM_HAL_INTERRUPT_RSV35             35
 134
 135 #define CYGNUM_HAL_INTERRUPT_CMIA0             36
 136 #define CYGNUM_HAL_INTERRUPT_CMIB0             37
 137 #define CYGNUM_HAL_INTERRUPT_CMIAB1            38
 138 #define CYGNUM_HAL_INTERRUPT_TOVI01            39
 139
 140 #define CYGNUM_HAL_INTERRUPT_CMIA2             40
 141 #define CYGNUM_HAL_INTERRUPT_CMIB2             41
 142 #define CYGNUM_HAL_INTERRUPT_CMIAB3            42
 143 #define CYGNUM_HAL_INTERRUPT_TOVI23            43
 144
 145 #define CYGNUM_HAL_INTERRUPT_DEND0A            44
 146 #define CYGNUM_HAL_INTERRUPT_DEND0B            45
 147 #define CYGNUM_HAL_INTERRUPT_DEND1A            46
 148 #define CYGNUM_HAL_INTERRUPT_DEND1B            47
 149
 150 #define CYGNUM_HAL_INTERRUPT_RSV48             48
 151 #define CYGNUM_HAL_INTERRUPT_RSV49             49
 152 #define CYGNUM_HAL_INTERRUPT_RSV50             50
 153 #define CYGNUM_HAL_INTERRUPT_RSV51             51
 154
 155 #define CYGNUM_HAL_INTERRUPT_ERI0              52
 156 #define CYGNUM_HAL_INTERRUPT_RXI0              53
 157 #define CYGNUM_HAL_INTERRUPT_TXI0              54
 158 #define CYGNUM_HAL_INTERRUPT_TEI0              55
 159
 160 #define CYGNUM_HAL_INTERRUPT_ERI1              56
 161 #define CYGNUM_HAL_INTERRUPT_RXI1              57
 162 #define CYGNUM_HAL_INTERRUPT_TXI1              58
 163 #define CYGNUM_HAL_INTERRUPT_TEI1              59
 164
 165 #define CYGNUM_HAL_INTERRUPT_ERI2              60
 166 #define CYGNUM_HAL_INTERRUPT_RXI2              61
 167 #define CYGNUM_HAL_INTERRUPT_TXI2              62
 168 #define CYGNUM_HAL_INTERRUPT_TEI2              63
 169
 170 #define CYGNUM_HAL_ISR_MIN                     0
 171 #define CYGNUM_HAL_ISR_MAX                     63
 172
 173 #define CYGNUM_HAL_ISR_COUNT                   (3+((CYGNUM_HAL_ISR_MAX+1)/4))
 174
 175 // The vector used by the Real time clock
 176
 177 #define CYGNUM_HAL_INTERRUPT_RTC                CYGNUM_HAL_INTERRUPT_CMIAB3
 178
 179 //--------------------------------------------------------------------------
 180 // Interrupt vector translation.
 181
 182 #if !defined(HAL_TRANSLATE_VECTOR) && !defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN)
 183
 184 #define HAL_TRANSLATE_VECTOR(_vector_,_index_)                             \
 185               _index_ = (_vector_)
 186
 187 #endif
 188
 189 //--------------------------------------------------------------------------
 190 // H8/300H specific version of HAL_INTERRUPT_CONFIGURE
 191
 192 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ )                \
 193         hal_interrupt_configure( _vector_, _level_, _up_ )
 194
 195 externC void hal_interrupt_configure(int vector,int level,int up);
 196
 197 #define HAL_INTERRUPT_CONFIGURE_DEFINED
 198
 199 //--------------------------------------------------------------------------
 200 // Interrupt control macros
 201
 202 #define HAL_DISABLE_INTERRUPTS(_old_)   \
 203         asm volatile (                  \
 204             "sub.l er0,er0\n\t"         \
 205             "stc ccr,r0l\n\t"           \
 206             "orc #0x80,ccr\n\t"        \
 207             "and.b #0xc0,r0l\n\t"       \
 208             "mov.l er0,%0"          \
 209             : "=r"(_old_)               \
 210             :                           \
 211             : "er0"                      \
 212             );
 213
 214 #define HAL_ENABLE_INTERRUPTS()         \
 215         asm volatile (                  \
 216             "andc #0x3f,ccr"             \
 217             );
 218
 219 #define HAL_RESTORE_INTERRUPTS(_old_)   \
 220         asm volatile (                  \
 221             "mov.l %0,er0\n\t"          \
 222             "and.b #0xc0,r0l\n\t"       \
 223             "stc ccr,r0h\n\t"           \
 224             "and.b #0x3f,r0h\n\t"       \
 225             "or.b r0h,r0l\n\t"          \
 226             "ldc r0l,ccr"               \
 227             :                           \
 228             : "r"(_old_)                \
 229             : "er0"                     \
 230             );
 231
 232 #define HAL_QUERY_INTERRUPTS(_old_)     \
 233         asm volatile (                  \
 234             "sub.l er0,er0\n\t"         \
 235             "stc ccr,r0l\n\t"           \
 236             "and.b #0xc0,r0l\n\t"       \
 237             "mov.l er0,%0"              \
 238             : "=r"(_old_)               \
 239             );
 240
 241 //--------------------------------------------------------------------------
 242 // Clock control.
 243
 244 externC void hal_clock_initialize(cyg_uint32 period);
 245 externC void hal_clock_reset(cyg_uint32 vector,cyg_uint32 period);
 246 externC void hal_clock_read(cyg_uint32 *pvalue);
 247
 248 #define HAL_CLOCK_INITIALIZE( _period_ ) \
 249         hal_clock_initialize( _period_ )
 250
 251 #define HAL_CLOCK_RESET( _vector_, _period_ ) \
 252         hal_clock_reset( _vector_, _period_ )
 253
 254 #define HAL_CLOCK_READ( _pvalue_ ) \
 255         hal_clock_read( _pvalue_ )
 256
 257 // FIXME: above line should not use CYGNUM_KERNEL_COUNTERS_RTC_PERIOD since
 258 // this means the HAL gets configured by kernel options even when the
 259 // kernel is disabled!
 260
 261
 262 //--------------------------------------------------------------------------
 263 #endif // ifndef CYGONCE_HAL_VAR_INTR_H
 264 // End of var_intr.h