1 #ifndef CYGONCE_HAL_IDT32334SIO_H
2 #define CYGONCE_HAL_IDT32334SIO_H
4 /*=============================================================================
8 // IDT 32334 serial I/O definitions
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
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41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //==========================================================================
44 //#####DESCRIPTIONBEGIN####
46 // Author(s): Tim Michals
47 // Contributors: nickg
49 // Purpose: IDT 32334 serial I/O definitions
52 //####DESCRIPTIONEND####
53 //========================================================================*/
55 // Interrupt Enable Register
61 // Line Control Register
62 #define LCR_WL5 0x00 // Word length
66 #define LCR_SB1 0x00 // Number of stop bits
67 #define LCR_SB1_5 0x04 // 1.5 -> only valid with 5 bit words
69 #define LCR_PN 0x00 // Parity mode - none
70 #define LCR_PE 0x0C // Parity mode - even
71 #define LCR_PO 0x08 // Parity mode - odd
72 #define LCR_PM 0x28 // Forced "mark" parity
73 #define LCR_PS 0x38 // Forced "space" parity
74 #define LCR_DL 0x80 // Enable baud rate latch
76 // Line Status Register
80 // Modem Control Register
83 #define MCR_INT 0x08 // Enable interrupts
85 // Interrupt status register
89 // FIFO control register
90 #define FCR_ENABLE 0x01
91 #define FCR_CLEAR_RCVR 0x02
92 #define FCR_CLEAR_XMIT 0x04
96 ////////////////////////////////////////////////////////////
99 //-----------------------------------------------------------------------------
100 // There are two serial ports.
101 #define CMA_SER_16550_BASE_A 0xb8000803 // port A
102 #define CMA_SER_16550_BASE_B 0xb8000823 // port B
103 #define SER_16550_BASE CMA_SER_16550_BASE_A
105 //-----------------------------------------------------------------------------
106 // Define the serial registers. The Cogent board is equipped with a 16552
108 #define SER_16550_RBR 0x00 // receiver buffer register, read, dlab = 0
109 #define SER_16550_THR 0x00 // transmitter holding register, write, dlab = 0
110 #define SER_16550_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
111 #define SER_16550_IER 0x04 // interrupt enable register, read/write, dlab = 0
112 #define SER_16550_DLM 0x04 // divisor latch (MS), read/write, dlab = 1
113 #define SER_16550_IIR 0x08 // interrupt identification reg, read, dlab = 0
114 #define SER_16550_FCR 0x08 // fifo control register, write, dlab = 0
115 #define SER_16550_AFR 0x10 // alternate function reg, read/write, dlab = 1
116 #define SER_16550_LCR 0x0c // line control register, read/write
117 #define SER_16550_MCR 0x10 // modem control register, read/write
118 #define SER_16550_LSR 0x14 // line status register, read
119 #define SER_16550_MSR 0x18 // modem status register, read
120 #define SER_16550_SCR 0x1C // scratch pad register
122 // The interrupt enable register bits.
123 #define SIO_IER_ERDAI 0x01 // enable received data available irq
124 #define SIO_IER_ETHREI 0x02 // enable THR empty interrupt
125 #define SIO_IER_ELSI 0x04 // enable receiver line status irq
126 #define SIO_IER_EMSI 0x08 // enable modem status interrupt
128 // The interrupt identification register bits.
129 #define SIO_IIR_IP 0x01 // 0 if interrupt pending
130 #define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits
132 // The line status register bits.
133 #define SIO_LSR_DR 0x01 // data ready
134 #define SIO_LSR_OE 0x02 // overrun error
135 #define SIO_LSR_PE 0x04 // parity error
136 #define SIO_LSR_FE 0x08 // framing error
137 #define SIO_LSR_BI 0x10 // break interrupt
138 #define SIO_LSR_THRE 0x20 // transmitter holding register empty
139 #define SIO_LSR_TEMT 0x40 // transmitter register empty
140 #define SIO_LSR_ERR 0x80 // any error condition
142 // The modem status register bits.
143 #define SIO_MSR_DCTS 0x01 // delta clear to send
144 #define SIO_MSR_DDSR 0x02 // delta data set ready
145 #define SIO_MSR_TERI 0x04 // trailing edge ring indicator
146 #define SIO_MSR_DDCD 0x08 // delta data carrier detect
147 #define SIO_MSR_CTS 0x10 // clear to send
148 #define SIO_MSR_DSR 0x20 // data set ready
149 #define SIO_MSR_RI 0x40 // ring indicator
150 #define SIO_MSR_DCD 0x80 // data carrier detect
152 // The line control register bits.
153 #define SIO_LCR_WLS0 0x01 // word length select bit 0
154 #define SIO_LCR_WLS1 0x02 // word length select bit 1
155 #define SIO_LCR_STB 0x04 // number of stop bits
156 #define SIO_LCR_PEN 0x08 // parity enable
157 #define SIO_LCR_EPS 0x10 // even parity select
158 #define SIO_LCR_SP 0x20 // stick parity
159 #define SIO_LCR_SB 0x40 // set break
160 #define SIO_LCR_DLAB 0x80 // divisor latch access bit
162 // The FIFO control register
163 #define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos
164 #define SIO_FCR_FCR1 0x02 // clear RCVR FIFO
165 #define SIO_FCR_FCR2 0x04 // clear XMIT FIFO
166 /////////////////////////////////////////
169 static unsigned char select_word_length[] = {
170 LCR_WL5, // 5 bits / word (char)
176 static unsigned char select_stop_bits[] = {
178 LCR_SB1, // 1 stop bit
179 LCR_SB1_5, // 1.5 stop bit
180 LCR_SB2 // 2 stop bits
183 static unsigned char select_parity[] = {
185 LCR_PE, // Even parity
186 LCR_PO, // Odd parity
187 LCR_PM, // Mark parity
188 LCR_PS, // Space parity
191 // FIXME: calc all properly
192 // The Cogent board has a 3.6864 MHz crystal
193 static unsigned short select_baud[] = {
219 #define NS16550_XTAL_FREQ (75 * 1000000)
220 #define IDT_BAUD_RATE 115200
222 #endif /* CYGONCE_HAL_IDT32334SIO_H */
223 /*---------------------------------------------------------------------------*/
224 /* end of idt32334sio.h */