1 #ifndef CYGONCE_VAR_CACHE_H
2 #define CYGONCE_VAR_CACHE_H
4 //=============================================================================
8 // HAL cache control API
10 //=============================================================================
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43 //=============================================================================
44 //#####DESCRIPTIONBEGIN####
47 // Contributors: nickg
49 // Purpose: Cache control API
50 // Description: The macros defined here provide the HAL APIs for handling
51 // cache control operations.
53 // #include <cyg/hal/var_cache.h>
57 //####DESCRIPTIONEND####
59 //=============================================================================
61 #include <pkgconf/hal.h>
62 #include <cyg/infra/cyg_type.h>
64 #include <cyg/hal/plf_cache.h>
66 //-----------------------------------------------------------------------------
70 #define HAL_DCACHE_SIZE (8*1024) // Size of data cache in bytes
71 #define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
72 #define HAL_DCACHE_WAYS 1 // Associativity of the cache
75 #define HAL_ICACHE_SIZE (16*1024) // Size of cache in bytes
76 #define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line
77 #define HAL_ICACHE_WAYS 1 // Associativity of the cache
79 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
80 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
82 //-----------------------------------------------------------------------------
83 // The VR4300 mostly uses the default MIPS cache controls defined in hal_cache.h
84 // Here we define the cache enable and disable macros. The only control we appear
85 // to have is the kseg0 cache state in config0. So all these macros at present
88 #ifndef HAL_DCACHE_ENABLE_DEFINED
89 #define HAL_DCACHE_ENABLE() \
91 asm volatile ( "mfc0 $2,$16\n" \
93 "la $3,0xFFFFFFF8\n" \
103 #define HAL_DCACHE_ENABLE_DEFINED
106 // Disable the data cache
107 #ifndef HAL_DCACHE_DISABLE_DEFINED
108 #define HAL_DCACHE_DISABLE() \
110 asm volatile ( "mfc0 $2,$16\n" \
112 "la $3,0xFFFFFFF8\n" \
122 #define HAL_DCACHE_DISABLE_DEFINED
125 #ifndef HAL_DCACHE_IS_ENABLED_DEFINED
126 #define HAL_DCACHE_IS_ENABLED(_state_) \
128 CYG_WORD32 _cstate_; \
129 asm volatile ( "mfc0 %0,$16\n" \
132 if( (_cstate_ & 7) == 2 ) _state_ = 0; \
135 #define HAL_DCACHE_IS_ENABLED_DEFINED
138 #ifndef HAL_ICACHE_ENABLE_DEFINED
139 #define HAL_ICACHE_ENABLE() HAL_DCACHE_ENABLE()
140 #define HAL_ICACHE_ENABLE_DEFINED
143 // Disable the instruction cache
144 #ifndef HAL_ICACHE_DISABLE_DEFINED
145 #define HAL_ICACHE_DISABLE() HAL_DCACHE_DISABLE()
146 #define HAL_ICACHE_DISABLE_DEFINED
149 #ifndef HAL_ICACHE_IS_ENABLED_DEFINED
150 #define HAL_ICACHE_IS_ENABLED(_state_) HAL_DCACHE_IS_ENABLED(_state_)
151 #define HAL_ICACHE_IS_ENABLED_DEFINED
154 //-----------------------------------------------------------------------------
155 // The VR4300 has no cache locking facility so we define the guard macros
156 // to disable the definitions in hal_arch.h.
158 #define HAL_DCACHE_LOCK_DEFINED
159 #define HAL_DCACHE_UNLOCK_DEFINED
160 #define HAL_DCACHE_UNLOCK_ALL_DEFINED
162 #define HAL_ICACHE_LOCK_DEFINED
163 #define HAL_ICACHE_UNLOCK_DEFINED
165 //-----------------------------------------------------------------------------
166 #endif // ifndef CYGONCE_VAR_CACHE_H
167 // End of var_cache.h