1 ##=============================================================================
5 ## MN10300 AM33 variant code
7 ##=============================================================================
8 #####ECOSGPLCOPYRIGHTBEGIN####
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38 ## -------------------------------------------
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40 ##=============================================================================
41 #######DESCRIPTIONBEGIN####
44 ## Contributors: nickg
46 ## Purpose: MN10300 AM33 variant code
47 ## Description: This file contains variant specific assembly code for the AM33.
49 ######DESCRIPTIONEND####
51 ##=============================================================================
53 #include <pkgconf/hal.h>
55 #include <cyg/hal/arch.inc>
58 ##-----------------------------------------------------------------------------
59 ## NMI trampoline VSRs. All NMI interrupts are routed here initially, where we
60 ## decode the NMICR and ISR register contents and vector to the
61 ## correct VSR later in the table.
65 .extern hal_lsbit_table
67 .globl nmi_vsr_trampoline
69 movhu (NMICR),d0 # D0 = NMI control register
70 and 0x7,d0 # LS 3 bits only
71 mov 3,d1 # search from bit 3
72 bsch d0,d1 # get ms bit in d1
73 bcs 2f # jump if no bits there
74 add 9,d1 # D1 = offset into VSR table
75 jmp 3f # go to rest of code
77 .globl nmi_sysef_trampoline
79 movhu (ISR),d0 # D0 = Interrupt Status Register
80 mov d0,d1 # D1 = copy of D0
82 not d1 # D1 = ~(D0-1) = -D0
83 and d1,d0 # D0 = D0 & -D0 = ls bit only
84 mov 16,d1 # D1 = start of search bit
85 bsch d0,d1 # search for 1 bit in d0
86 bcs 2f # jump if failed
87 add 12,d1 # d1 = offset in VSR table
89 asl 2,d1 # D1 = word offset in vsr table
90 mov _hal_vsr_table,a0 # A0 = VSR table base
91 add d1,a0 # A0 = address of table entry we want
92 mov (a0),a0 # A0 = VSR to call
96 # no bits set in ISR or NMICR when we expected them.
97 # This should never happen, but if it does, use an otherwise
98 # unused VSR table entry to indicate this.
100 mov 27,d1 # use last VSR table entry.
104 ##-----------------------------------------------------------------------------
106 #define HAL_CHCTR 0xC0000070
107 #define HAL_DCACHE_PURGE_WAY0 0xC8400000
108 #define HAL_CHCTR_DCEN 0x0002
109 #define HAL_CHCTR_DCBUSY 0x0008
113 .globl _cyg_hal_dcache_store
114 _cyg_hal_dcache_store:
117 mov HAL_CHCTR,a0 # A0 = control reg
118 mov HAL_DCACHE_PURGE_WAY0,a1 # A1 = purge base address
120 # Disable DCACHE if it is enabled
122 movhu (a0),d2 # D2 = old value of control reg
124 btst HAL_CHCTR_DCEN,d2 # check for cache enabled
125 beq 1f # if not, skip disable
127 mov d2,d3 # make a copy of CHCTR
128 and ~HAL_CHCTR_DCEN,d3 # clear DCEN bit
129 movhu d3,(a0) # store in reg
131 2: movhu (a0),d3 # get CHCTR
132 btst HAL_CHCTR_DCBUSY,d3 # test DCBUSY bit
133 bne 2b # loop while set
136 # The cache is now disabled
138 and 0x000003f0,d0 # isolate index bits of base addr
139 add d0,a1 # offset a1 to base address
141 add 63,d1 # adjust size to whole multiple of
142 and 0xFFFFFFC0,d1 # set size.
144 mov (0x0000,a1),d0 # purge way 0
145 mov (0x1000,a1),d0 # purge way 1
146 mov (0x2000,a1),d0 # purge way 2
147 mov (0x3000,a1),d0 # purge way 3
149 add 16,a1 # advance to next set
151 sub 64,d1 # decrement count
152 bne 3b # loop while non zero
154 # Restore original cache state from saved CHCTR in D2
158 movm (sp),[d2,d3] # restore work regs
163 ##-----------------------------------------------------------------------------