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4 <title>README - eCos OpenRISC Port</title>
8 For those unfamiliar with OpenRISC, it is an open-source RISC/DSP processor
9 architecture. OpenCores.org makes available an <a
10 href="http://www.opencores.org/projects/or1k">implementation</a> of this
11 architecture that can be synthesized, for example, as part of an FPGA or ASIC.
12 The port of eCos to OpenRISC was sponsored by the <a
13 href="http://www.rosum.com">Rosum Corporation</a>.<br>
15 A few notes and caveats about the eCos OpenRISC port:
17 <li>The only platform supported at this time is ORP (OpenRISC Reference
19 <li>The only ORP devices supported so far are serial ports used for
20 diagnostic and debugging purposes and AM29LVxxxx Flash ROM.</li>
21 <li>To build and debug, you must build the GNU development tools from
23 href="#%20http://www.opencores.org/projects/or1k/GNU%20Toolchain%20Port">source
24 available at the OpenCores web site</a> -- not the versions available
25 from the GNU web site or elsewhere. There is a <a
26 href="./build_or32_elf_tools.sh">shell script</a> in this directory that
27 will assist in downloading and building the GNU toolchain.</li>
28 <li>For debugging, you can use either gdb's JTAG target or the serial
29 target. The latter has some advantages, e.g. the gdb serial target is
30 thread-aware, but it is much slower, especially while simulating.<br>
35 <i>sfurman at rosum dot com</i><br>