packages/hal/powerpc/ec555/v2_0/src/ec555.S

   1 ##=============================================================================
   2 ##
   3 ##      ec555.S
   4 ##
   5 ##      ec555 board hardware setup
   6 ##
   7 ##=============================================================================
   8 #####ECOSGPLCOPYRIGHTBEGIN####
   9 ## -------------------------------------------
  10 ## This file is part of eCos, the Embedded Configurable Operating System.
  11 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  12 ##
  13 ## eCos is free software; you can redistribute it and/or modify it under
  14 ## the terms of the GNU General Public License as published by the Free
  15 ## Software Foundation; either version 2 or (at your option) any later version.
  16 ##
  17 ## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  18 ## WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19 ## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  20 ## for more details.
  21 ##
  22 ## You should have received a copy of the GNU General Public License along
  23 ## with eCos; if not, write to the Free Software Foundation, Inc.,
  24 ## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  25 ##
  26 ## As a special exception, if other files instantiate templates or use macros
  27 ## or inline functions from this file, or you compile this file and link it
  28 ## with other works to produce a work based on this file, this file does not
  29 ## by itself cause the resulting work to be covered by the GNU General Public
  30 ## License. However the source code for this file must still be made available
  31 ## in accordance with section (3) of the GNU General Public License.
  32 ##
  33 ## This exception does not invalidate any other reasons why a work based on
  34 ## this file might be covered by the GNU General Public License.
  35 ##
  36 ## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  37 ## at http://sources.redhat.com/ecos/ecos-license/
  38 ## -------------------------------------------
  39 #####ECOSGPLCOPYRIGHTEND####
  40 ##=============================================================================
  41 #######DESCRIPTIONBEGIN####
  42 ##
  43 ## Author(s):   Bob Koninckx
  44 ## Contributors:Bob Koninckx
  45 ## Date:        2002-01-01
  46 ## Purpose:     ec555 board hardware setup
  47 ## Description: This file contains any code needed to initialize the
  48 ##              hardware on a ec555 mpc555 board.
  49 ##
  50 ######DESCRIPTIONEND####
  51 ##
  52 ##=============================================================================
  53
  54 #include <pkgconf/hal.h>
  55
  56 #include <cyg/hal/ppc_regs.h>
  57 #include <cyg/hal/arch.inc>
  58
  59 #include <pkgconf/system.h>
  60 #ifdef CYGPKG_DEVS_ETH_POWERPC_EC555
  61 #include <pkgconf/devs_eth_powerpc_ec555.h>
  62 #endif
  63
  64 ## FIXME
  65 ## The following probably belongs in the variant hal rather than the board specifics ...
  66 #ifdef CYGPKG_DEVICES_WATCHDOG_MPC5xx
  67 #include <pkgconf/devices_watchdog_mpc5xx.h>
  68 #define CYG_SYPCR 0x0000ff8e | (CYGNUM_DEVICES_WATCHDOG_POWERPC_MPC5XX_RELOAD << 16) | CYGDAT_DEVICES_WATCHDOG_POWERPC_MPC5XX_PRESCALE
  69 #else
  70 #define CYG_SYPCR 0x0000ff88
  71 #endif
  72
  73 #define ADDRESS_MASK_1MB         0xfff00000
  74 #define ADDRESS_MASK_2MB         0xffe00000
  75 #define ADDRESS_MASK_4MB         0xffc00000
  76 #define ADDRESS_MASK_8MB         0xff800000
  77 #define ADDRESS_MASK_16MB        0xff000000
  78
  79 #define EC555_RAM_BASE_ADDRESS   0x01000000
  80 #define EC555_FLASH_BASE_ADDRESS 0x02000000
  81 #define EC555_CS2_BASE_ADDRESS   0x04000000
  82 #define EC555_CS3_BASE_ADDRESS   0x08000000
  83
  84 #if defined(CYGHWR_HAL_EC555_BOARD_VARIANT_F02_S01)
  85 #define EC555_RAM_ADDRESS_MASK   ADDRESS_MASK_1MB
  86 #define EC555_FLASH_ADDRESS_MASK ADDRESS_MASK_2MB
  87 #elif defined(CYGHWR_HAL_EC555_BOARD_VARIANT_F04_S02)
  88 #define EC555_RAM_ADDRESS_MASK   ADDRESS_MASK_2MB
  89 #define EC555_FLASH_ADDRESS_MASK ADDRESS_MASK_4MB
  90 #elif defined(CYGHWR_HAL_EC555_BOARD_VARIANT_F08_S04)
  91 #define EC555_RAM_ADDRESS_MASK   ADDRESS_MASK_4MB
  92 #define EC555_FLASH_ADDRESS_MASK ADDRESS_MASK_8MB
  93 #elif defined(CYGHWR_HAL_EC555_BOARD_VARIANT_F08_S08)
  94 #define EC555_RAM_ADDRESS_MASK   ADDRESS_MASK_8MB
  95 #define EC555_FLASH_ADDRESS_MASK ADDRESS_MASK_16MB
  96 #else
  97 #error "EC555 Board variant unspecified"
  98 #endif
  99
 100 #define EC555_CS2_ADDRESS_MASK   0xffff8000
 101 #define EC555_CS3_ADDRESS_MASK   0xffff8000
 102
 103 #------------------------------------------------------------------------------
 104
 105         .globl  hal_hardware_init
 106 hal_hardware_init:
 107 #if defined(CYGPKG_HAL_POWERPC_EC555) && defined(CYGPKG_HAL_POWERPC_MPC5xx)
 108         lwi     r3, CYGARC_REG_IMM_BASE             # Base address of control registers
 109
 110 #if defined(CYG_HAL_STARTUP_ROM)
 111         // Burst enable
 112         lwi     r0, 0x00002000
 113         mtspr   560, r0
 114
 115         // FIXME
 116         // The following probably belongs in the variant hal rather than the board specifics ...
 117         // Disable / enable the Watchdog
 118         lwi     r4, CYG_SYPCR
 119         stw     r4, (CYGARC_REG_IMM_SYPCR-CYGARC_REG_IMM_BASE)(r3)
 120         lwi     r4, 0x00000000
 121         stw     r4, (CYGARC_REG_IMM_SIUMCR-CYGARC_REG_IMM_BASE)(r3)
 122
 123         // Unlock locked registers
 124         lwi     r4, 0x55ccaa33
 125         stw     r4, (CYGARC_REG_IMM_TBSCRK-CYGARC_REG_IMM_BASE)(r3)
 126         stw     r4, (CYGARC_REG_IMM_TBREF0K-CYGARC_REG_IMM_BASE)(r3)
 127         stw     r4, (CYGARC_REG_IMM_TBREF1K-CYGARC_REG_IMM_BASE)(r3)
 128         stw     r4, (CYGARC_REG_IMM_TBK-CYGARC_REG_IMM_BASE)(r3)
 129         stw     r4, (CYGARC_REG_IMM_RTCSCK-CYGARC_REG_IMM_BASE)(r3)
 130         stw     r4, (CYGARC_REG_IMM_RTCK-CYGARC_REG_IMM_BASE)(r3)
 131         stw     r4, (CYGARC_REG_IMM_RTSECK-CYGARC_REG_IMM_BASE)(r3)
 132         stw     r4, (CYGARC_REG_IMM_RTCALK-CYGARC_REG_IMM_BASE)(r3)
 133         stw     r4, (CYGARC_REG_IMM_PISCRK-CYGARC_REG_IMM_BASE)(r3)
 134         stw     r4, (CYGARC_REG_IMM_PITCK-CYGARC_REG_IMM_BASE)(r3)
 135         stw     r4, (CYGARC_REG_IMM_SCCRK-CYGARC_REG_IMM_BASE)(r3)
 136         stw     r4, (CYGARC_REG_IMM_PLPRCRK-CYGARC_REG_IMM_BASE)(r3)
 137         stw     r4, (CYGARC_REG_IMM_RSRK-CYGARC_REG_IMM_BASE)(r3)
 138
 139         // Either Redboot or BDM will have already done it otherwise
 140         // Boost the clock to 40MHz
 141         lwi     r4, 0x03000000
 142         stw     r4, (CYGARC_REG_IMM_SCCR-CYGARC_REG_IMM_BASE)(r3)
 143         lwi     r4, 0x009150c0
 144         stw     r4, (CYGARC_REG_IMM_PLPRCR-CYGARC_REG_IMM_BASE)(r3)
 145         lwi     r4, 0x0080
 146         sth     r4, (CYGARC_REG_IMM_COLIR-CYGARC_REG_IMM_BASE)(r3)
 147
 148         // Set up the memory map
 149         // Do NOT write protect the flash memory, flash drivers won't work
 150         // if we do
 151
 152         // flash banks
 153         lwi     r4, (EC555_FLASH_BASE_ADDRESS | 0x00000003)
 154         stw     r4, (CYGARC_REG_IMM_BR0-CYGARC_REG_IMM_BASE)(r3)
 155         lwi     r4, (EC555_FLASH_ADDRESS_MASK | 0x00000530)
 156         stw     r4, (CYGARC_REG_IMM_OR0-CYGARC_REG_IMM_BASE)(r3)
 157
 158         // ram banks
 159         lwi     r4, (EC555_RAM_BASE_ADDRESS | 0x00000011)
 160         stw     r4, (CYGARC_REG_IMM_BR1-CYGARC_REG_IMM_BASE)(r3)
 161         lwi     r4, (EC555_RAM_ADDRESS_MASK | 0x00000000)
 162         stw     r4, (CYGARC_REG_IMM_OR1-CYGARC_REG_IMM_BASE)(r3)
 163 #endif
 164
 165 #ifdef CYGPKG_DEVS_ETH_POWERPC_EC555
 166 #if   (CYGNUM_DEVS_ETH_POWERPC_EC555_ETH0_CS == 2)
 167         lwi     r4, (EC555_CS2_BASE_ADDRESS | 0x00000803)
 168         stw     r4, (CYGARC_REG_IMM_BR2-CYGARC_REG_IMM_BASE)(r3)
 169         lwi     r4, 0xffff8ca0
 170         stw     r4, (CYGARC_REG_IMM_OR2-CYGARC_REG_IMM_BASE)(r3)
 171
 172         lwi     r4, EC555_CS3_BASE_ADDRESS
 173         stw     r4, (CYGARC_REG_IMM_BR3-CYGARC_REG_IMM_BASE)(r3)
 174         lwi     r4, EC555_CS3_ADDRESS_MASK
 175         stw     r4, (CYGARC_REG_IMM_OR3-CYGARC_REG_IMM_BASE)(r3)
 176 #elif (CYGNUM_DEVS_ETH_POWERPC_EC555_ETH0_CS == 3)
 177         lwi     r4, EC555_CS2_BASE_ADDRESS
 178         stw     r4, (CYGARC_REG_IMM_BR2-CYGARC_REG_IMM_BASE)(r3)
 179         lwi     r4, EC555_CS2_ADDRESS_MASK
 180         stw     r4, (CYGARC_REG_IMM_OR2-CYGARC_REG_IMM_BASE)(r3)
 181
 182         lwi     r4, (EC555_CS3_BASE_ADDRESS | 0x00000803)
 183         stw     r4, (CYGARC_REG_IMM_BR3-CYGARC_REG_IMM_BASE)(r3)
 184         lwi     r4, 0xffff8ca0
 185         stw     r4, (CYGARC_REG_IMM_OR3-CYGARC_REG_IMM_BASE)(r3)
 186 #else
 187 #error "Invalid chip select for ethernet card specified"
 188 #endif
 189 #else
 190         lwi     r4, EC555_CS2_BASE_ADDRESS
 191         stw     r4, (CYGARC_REG_IMM_BR2-CYGARC_REG_IMM_BASE)(r3)
 192         lwi     r4, EC555_CS2_ADDRESS_MASK
 193         stw     r4, (CYGARC_REG_IMM_OR2-CYGARC_REG_IMM_BASE)(r3)
 194
 195         lwi     r4, EC555_CS3_BASE_ADDRESS
 196         stw     r4, (CYGARC_REG_IMM_BR3-CYGARC_REG_IMM_BASE)(r3)
 197         lwi     r4, EC555_CS3_ADDRESS_MASK
 198         stw     r4, (CYGARC_REG_IMM_OR3-CYGARC_REG_IMM_BASE)(r3)
 199 #endif
 200
 201 #if defined(CYGSEM_HAL_POWERPC_MPC5XX_IFLASH_DUAL_MAP)
 202         lwi     r4, 1
 203 #else
 204         lwi     r4, 0
 205 #endif
 206         stw     r4, (CYGARC_REG_IMM_DMBR-CYGARC_REG_IMM_BASE)(r3)
 207         lwi     r4, 0
 208         stw     r4, (CYGARC_REG_IMM_DMOR-CYGARC_REG_IMM_BASE)(r3)
 209
 210         // Enable the time base, but do _not_ set the freeze flag
 211         lwi     r4, 0xc1
 212         sth     r4, (CYGARC_REG_IMM_TBSCR-CYGARC_REG_IMM_BASE)(r3)
 213
 214         // RTC is clocked by 4MHz crystal, set the freeze flag
 215         lwi     r4, 0xd2
 216         sth     r4, (CYGARC_REG_IMM_RTCSC-CYGARC_REG_IMM_BASE)(r3)
 217
 218         // Set the freeze flag for the Periodic interrupt timer
 219         lwi     r4, 0x82
 220         sth     r4, (CYGARC_REG_IMM_PISCR-CYGARC_REG_IMM_BASE)(r3)
 221
 222         // USIU rest.
 223         lwi     r4, 0x00000000
 224         lwi     r5, (CYGARC_REG_IMM_SGPIODT1-CYGARC_REG_IMM_BASE)
 225         stwx    r4, r3, r5
 226         lwi     r5, (CYGARC_REG_IMM_SGPIODT2-CYGARC_REG_IMM_BASE)
 227         stwx    r4, r3, r5
 228         lwi     r5, (CYGARC_REG_IMM_SGPIOCR-CYGARC_REG_IMM_BASE)
 229         stwx    r4, r3, r5
 230         lwi     r4, 0x00000ac6
 231         lwi     r5, (CYGARC_REG_IMM_EMCR-CYGARC_REG_IMM_BASE)
 232         stwx    r4, r3, r5
 233
 234         // Dual ported TPU RAM
 235         lwi     r4, 0x0000
 236         lwi     r5, (CYGARC_REG_IMM_DPTMCR-CYGARC_REG_IMM_BASE)
 237         sthx    r4, r3, r5
 238
 239         lwi     r4, 0xffa0
 240         lwi     r5, (CYGARC_REG_IMM_RAMBAR-CYGARC_REG_IMM_BASE)
 241         sthx    r4, r3, r5
 242
 243         lwi     r4, 0x00
 244         lwi     r5, (CYGARC_REG_IMM_PORTQS-CYGARC_REG_IMM_BASE)
 245         sthx    r4, r3, r5
 246
 247         lwi     r4, 0x00
 248         lwi     r5, (CYGARC_REG_IMM_PQSPAR_DDRQST-CYGARC_REG_IMM_BASE)
 249         sthx    r4, r3, r5
 250         lwi     r5, (CYGARC_REG_IMM_MPIOSMDR-CYGARC_REG_IMM_BASE)
 251         sthx    r4, r3, r5
 252         lwi     r5, (CYGARC_REG_IMM_MPIOSMDDR-CYGARC_REG_IMM_BASE)
 253         sthx    r4, r3, r5
 254         lwi     r5, (CYGARC_REG_IMM_SRAMMCR_A-CYGARC_REG_IMM_BASE)
 255         sthx    r4, r3, r5
 256
 257         // They are assigned OCD functionality on this board
 258         // Change the following to anything else  and BDM will not work anymore
 259         // on the ec555. This is not true for all MPC555 based boards, eg. cme555
 260         // does not have this requirement
 261         lwi     r4, 0x3
 262         lwi     r5, (CYGARC_REG_IMM_MIOS1TPCR-CYGARC_REG_IMM_BASE)
 263         sthx    r4, r3, r5
 264
 265         // Enable 32 interrupt priorities on the IMB3 unit
 266         lwi     r4, 0x60000000
 267         lwi     r5, (CYGARC_REG_IMM_UMCR-CYGARC_REG_IMM_BASE)
 268         stwx    r4, r3, r5
 269 #endif
 270         sync
 271         blr
 272
 273 #------------------------------------------------------------------------------
 274 # end of ec555.S