1 #ifndef CYGONCE_HAL_PPC_QUICC2_MPC8260_H
2 #define CYGONCE_HAL_PPC_QUICC2_MPC8260_H
4 //==========================================================================
8 // PowerPC QUICC2 register definitions
10 //==========================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 // Copyright (C) 2002 Gary Thomas
17 // eCos is free software; you can redistribute it and/or modify it under
18 // the terms of the GNU General Public License as published by the Free
19 // Software Foundation; either version 2 or (at your option) any later version.
21 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
22 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
26 // You should have received a copy of the GNU General Public License along
27 // with eCos; if not, write to the Free Software Foundation, Inc.,
28 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
30 // As a special exception, if other files instantiate templates or use macros
31 // or inline functions from this file, or you compile this file and link it
32 // with other works to produce a work based on this file, this file does not
33 // by itself cause the resulting work to be covered by the GNU General Public
34 // License. However the source code for this file must still be made available
35 // in accordance with section (3) of the GNU General Public License.
37 // This exception does not invalidate any other reasons why a work based on
38 // this file might be covered by the GNU General Public License.
40 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
41 // at http://sources.redhat.com/ecos/ecos-license/
42 // -------------------------------------------
43 //####ECOSGPLCOPYRIGHTEND####
44 //==========================================================================
45 //#####DESCRIPTIONBEGIN####
50 // Purpose: Provide PPC QUICC2 definitions
51 // Description: Provide PPC QUICC2 definitions
52 // Usage: THIS IS NOT AN EXTERNAL API
53 // This file is in the include dir to share it between
54 // QUICCII serial code and MPC8260 initialization code.
55 // #include <cyg/hal/quicc/mpc8260.h>
59 //####DESCRIPTIONEND####
61 //==========================================================================
63 /*-------------------------*/
64 /* Single buffer component */
65 /*-------------------------*/
67 typedef struct BufferPool
76 /*--------------------------*/
77 /* Buffer Descriptor Format */
78 /*--------------------------*/
80 typedef struct BufferDescriptor
83 CYG_WORD16 bd_cstatus; /* control and status */
84 CYG_WORD16 bd_length; /* transfer length */
85 volatile CYG_BYTE *bd_addr; /* buffer address */
90 /*-------------------------------*/
91 /* Buffer Descriptor Ring format */
92 /*-------------------------------*/
94 typedef struct BufferDescRings
97 BD RxBD; /* Rx BD ring */
98 BD TxBD; /* Tx BD ring */
103 #define _PackedType __attribute__((packed))
105 /******************************************************************************
107 * PARAMETER RAM (PRAM) FOR EACH PERIPHERAL
109 * Each subsection contains protocol-specific PRAM for each peripheral,
110 * followed by the PRAM common to all protocols for that peripheral. These
111 * structs are used as needed in the main MPC8260 memory map structure. Note
112 * that different modes of operation will require the use of different PRAM
113 * structs, and that certain structs may overlay and conflict with the use of
114 * other PRAM areas. Consult the MPC8260 User Manual for details as to what
115 * is unavailable when certain protocols are run on certain peripherals.
117 ******************************************************************************/
121 /*---------------------------------------------------------------------------*/
122 /* SERIAL COMMUNICATION CONTROLLER (SCC) */
123 /*---------------------------------------------------------------------------*/
129 typedef _Packed struct
131 CYG_BYTE reserved1[4]; /* Reserved area */
132 CYG_WORD c_mask; /* CRC constant */
133 CYG_WORD c_pres; /* CRC preset */
134 CYG_WORD16 disfc; /* discarded frame counter */
135 CYG_WORD16 crcec; /* CRC error counter */
136 CYG_WORD16 abtsc; /* abort sequence counter */
137 CYG_WORD16 nmarc; /* nonmatching address rx cnt */
138 CYG_WORD16 retrc; /* frame transmission counter. */
139 /* For FCC this area is reserved.*/
140 CYG_WORD16 mflr; /* maximum frame length reg */
141 CYG_WORD16 max_cnt; /* maximum length counter */
142 CYG_WORD16 rfthr; /* received frames threshold */
143 CYG_WORD16 rfcnt; /* received frames count */
144 CYG_WORD16 hmask; /* user defined frm addr mask */
145 CYG_WORD16 haddr1; /* user defined frm address 1 */
146 CYG_WORD16 haddr2; /* user defined frm address 2 */
147 CYG_WORD16 haddr3; /* user defined frm address 3 */
148 CYG_WORD16 haddr4; /* user defined frm address 4 */
149 CYG_WORD16 tmp; /* temp */
150 CYG_WORD16 tmp_mb; /* temp */
151 } _PackedType t_HdlcScc_Pram;
158 typedef _Packed struct
160 CYG_WORD c_pres; /* CRC preset */
161 CYG_WORD c_mask; /* CRC constant mask*/
162 CYG_WORD crcec; /* CRC error counter */
163 CYG_WORD alec; /* alignment error counter */
164 CYG_WORD disfc; /* discarded frame counter */
165 CYG_WORD16 pads; /* Short frame pad character. */
166 CYG_WORD16 ret_lim; /* Retry limit threshold. */
167 CYG_WORD16 ret_cnt; /* Retry limit counter. */
168 CYG_WORD16 mflr; /* maximum frame length reg */
169 CYG_WORD16 minflr; /* minimum frame length reg */
170 CYG_WORD16 maxd1; /* max DMA1 length register. */
171 CYG_WORD16 maxd2; /* max DMA2 length register. */
172 CYG_WORD16 maxd; /* Rx max DMA. */
173 CYG_WORD16 dma_cnt; /* Rx DMA counter. */
174 CYG_WORD16 max_b; /* max buffer descriptor byte count. */
175 CYG_WORD16 gaddr1; /* group address filter */
176 CYG_WORD16 gaddr2; /* group address filter */
177 CYG_WORD16 gaddr3; /* group address filter */
178 CYG_WORD16 gaddr4; /* group address filter */
179 CYG_WORD tbuf0_data0; /* Saved area 0, current frame. */
180 CYG_WORD tbuf0_data1; /* Saved area 1, current frame. */
183 CYG_WORD16 tbuf0_bcnt;
184 CYG_WORD16 paddr1_h; /* physical address (MSB) */
185 CYG_WORD16 paddr1_m; /* physical address */
186 CYG_WORD16 paddr1_l; /* physical address (LSB) */
187 CYG_WORD16 p_per; /* persistence */
188 CYG_WORD16 rfbd_ptr; /* Rx first BD pointer. */
189 CYG_WORD16 tfbd_ptr; /* Tx first BD pointer. */
190 CYG_WORD16 tlbd_ptr; /* Tx last BD pointer. */
191 CYG_WORD tbuf1_data0; /* Saved area 0, next frame. */
192 CYG_WORD tbuf1_data1; /* Saved area 1, next frame. */
195 CYG_WORD16 tbuf1_bcnt;
196 CYG_WORD16 tx_len; /* tx frame length counter */
197 CYG_WORD16 iaddr1; /* individual address filter. */
198 CYG_WORD16 iaddr2; /* individual address filter. */
199 CYG_WORD16 iaddr3; /* individual address filter. */
200 CYG_WORD16 iaddr4; /* individual address filter. */
201 CYG_WORD16 boff_cnt; /* back-off counter */
202 CYG_WORD16 taddr_h; /* temp address (MSB) */
203 CYG_WORD16 taddr_m; /* temp address */
204 CYG_WORD16 taddr_l; /* temp address (LSB) */
205 } _PackedType t_EnetScc_Pram;
211 typedef _Packed struct
213 CYG_BYTE reserved1[8]; /* Reserved area */
214 CYG_WORD16 max_idl; /* maximum idle characters */
215 CYG_WORD16 idlc; /* rx idle counter (internal) */
216 CYG_WORD16 brkcr; /* break count register */
217 CYG_WORD16 parec; /* Rx parity error counter */
218 CYG_WORD16 frmec; /* Rx framing error counter */
219 CYG_WORD16 nosec; /* Rx noise counter */
220 CYG_WORD16 brkec; /* Rx break character counter */
221 CYG_WORD16 brkln; /* Receive break length */
222 CYG_WORD16 uaddr1; /* address character 1 */
223 CYG_WORD16 uaddr2; /* address character 2 */
224 CYG_WORD16 rtemp; /* temp storage */
225 CYG_WORD16 toseq; /* Tx out of sequence char */
226 CYG_WORD16 cc[8]; /* Rx control characters */
227 CYG_WORD16 rccm; /* Rx control char mask */
228 CYG_WORD16 rccr; /* Rx control char register */
229 CYG_WORD16 rlbc; /* Receive last break char */
230 } _PackedType t_UartScc_Pram;
233 /*-----------------*/
234 /* SCC Transparent */
235 /*-----------------*/
237 typedef _Packed struct
239 CYG_WORD c_mask; /* CRC constant */
240 CYG_WORD c_pres; /* CRC preset */
241 } _PackedType t_TransScc_Pram;
248 typedef _Packed struct
250 CYG_BYTE reserved1[4]; /* Reserved area */
251 CYG_WORD crcc; /* CRC Constant Temp Value */
252 CYG_WORD16 prcrc; /* Preset Receiver CRC-16/LRC */
253 CYG_WORD16 ptcrc; /* Preset Transmitter CRC-16/LRC */
254 CYG_WORD16 parec; /* Receive Parity Error Counter */
255 CYG_WORD16 bsync; /* BISYNC SYNC Character */
256 CYG_WORD16 bdle; /* BISYNC DLE Character */
257 CYG_WORD16 cc[8]; /* Rx control characters */
258 CYG_WORD16 rccm; /* Receive Control Character Mask */
259 } _PackedType t_BisyncScc_Pram;
262 /*-----------------*/
263 /* SCC Common PRAM */
264 /*-----------------*/
266 typedef _Packed struct
268 CYG_WORD16 rbase; /* RX BD base address */
269 CYG_WORD16 tbase; /* TX BD base address */
270 CYG_BYTE rfcr; /* Rx function code */
271 CYG_BYTE tfcr; /* Tx function code */
272 CYG_WORD16 mrblr; /* Rx buffer length */
273 CYG_WORD rstate; /* Rx internal state */
274 CYG_WORD rptr; /* Rx internal data pointer */
275 CYG_WORD16 rbptr; /* rb BD Pointer */
276 CYG_WORD16 rcount; /* Rx internal byte count */
277 CYG_WORD rtemp; /* Rx temp */
278 CYG_WORD tstate; /* Tx internal state */
279 CYG_WORD tptr; /* Tx internal data pointer */
280 CYG_WORD16 tbptr; /* Tx BD pointer */
281 CYG_WORD16 tcount; /* Tx byte count */
282 CYG_WORD ttemp; /* Tx temp */
283 CYG_WORD rcrc; /* temp receive CRC */
284 CYG_WORD tcrc; /* temp transmit CRC */
293 volatile CYG_BYTE COMPLETE_SIZE_OF_DPRAM_PAGE[0x5c];
294 } _PackedType t_Scc_Pram;
298 /*---------------------------------------------------------------------------*/
299 /* FAST COMMUNICATION CONTROLLER (FCC) */
300 /*---------------------------------------------------------------------------*/
306 typedef _Packed struct
308 CYG_BYTE reserved1[8]; /* Reserved area */
309 CYG_WORD c_mask; /* CRC constant */
310 CYG_WORD c_pres; /* CRC preset */
311 CYG_WORD16 disfc; /* discarded frame counter */
312 CYG_WORD16 crcec; /* CRC error counter */
313 CYG_WORD16 abtsc; /* abort sequence counter */
314 CYG_WORD16 nmarc; /* nonmatching address rx cnt */
315 CYG_WORD max_cnt; /* maximum length counter */
316 CYG_WORD16 mflr; /* maximum frame length reg */
317 CYG_WORD16 rfthr; /* received frames threshold */
318 CYG_WORD16 rfcnt; /* received frames count */
319 CYG_WORD16 hmask; /* user defined frm addr mask */
320 CYG_WORD16 haddr1; /* user defined frm address 1 */
321 CYG_WORD16 haddr2; /* user defined frm address 2 */
322 CYG_WORD16 haddr3; /* user defined frm address 3 */
323 CYG_WORD16 haddr4; /* user defined frm address 4 */
324 CYG_WORD16 tmp; /* temp */
325 CYG_WORD16 tmp_mb; /* temp */
326 } _PackedType t_HdlcFcc_Pram;
333 typedef _Packed struct
335 CYG_WORD stat_bus; /* Internal use buffer. */
336 CYG_WORD cam_ptr; /* CAM address. */
337 CYG_WORD c_mask; /* CRC constant mask*/
338 CYG_WORD c_pres; /* CRC preset */
339 CYG_WORD crcec; /* CRC error counter */
340 CYG_WORD alec; /* alignment error counter */
341 CYG_WORD disfc; /* discarded frame counter */
342 CYG_WORD16 ret_lim; /* Retry limit threshold. */
343 CYG_WORD16 ret_cnt; /* Retry limit counter. */
344 CYG_WORD16 p_per; /* persistence */
345 CYG_WORD16 boff_cnt; /* back-off counter */
346 CYG_WORD gaddr_h; /* group address filter, high */
347 CYG_WORD gaddr_l; /* group address filter, low */
348 CYG_WORD16 tfcstat; /* out of sequece Tx BD staus. */
349 CYG_WORD16 tfclen; /* out of sequece Tx BD length. */
350 CYG_WORD tfcptr; /* out of sequece Tx BD data pointer. */
351 CYG_WORD16 mflr; /* maximum frame length reg */
352 CYG_WORD16 paddr1_h; /* physical address (MSB) */
353 CYG_WORD16 paddr1_m; /* physical address */
354 CYG_WORD16 paddr1_l; /* physical address (LSB) */
355 CYG_WORD16 ibd_cnt; /* internal BD counter. */
356 CYG_WORD16 ibd_start; /* internal BD start pointer. */
357 CYG_WORD16 ibd_end; /* internal BD end pointer. */
358 CYG_WORD16 tx_len; /* tx frame length counter */
359 CYG_BYTE ibd_base[0x20]; /* internal micro code usage. */
360 CYG_WORD iaddr_h; /* individual address filter, high */
361 CYG_WORD iaddr_l; /* individual address filter, low */
362 CYG_WORD16 minflr; /* minimum frame length reg */
363 CYG_WORD16 taddr_h; /* temp address (MSB) */
364 CYG_WORD16 taddr_m; /* temp address */
365 CYG_WORD16 taddr_l; /* temp address (LSB) */
366 CYG_WORD16 pad_ptr; /* pad_ptr. */
367 CYG_WORD16 cf_type; /* flow control frame type coding. */
368 CYG_WORD16 cf_range; /* flow control frame range. */
369 CYG_WORD16 max_b; /* max buffer descriptor byte count. */
370 CYG_WORD16 maxd1; /* max DMA1 length register. */
371 CYG_WORD16 maxd2; /* max DMA2 length register. */
372 CYG_WORD16 maxd; /* Rx max DMA. */
373 CYG_WORD16 dma_cnt; /* Rx DMA counter. */
376 CYG_WORD octc; /* received octets counter. */
377 CYG_WORD colc; /* estimated number of collisions */
378 CYG_WORD broc; /* received good packets of broadcast address */
379 CYG_WORD mulc; /* received good packets of multicast address */
380 CYG_WORD uspc; /* received packets shorter then 64 octets. */
381 CYG_WORD frgc; /* as uspc + bad packets */
382 CYG_WORD ospc; /* received packets longer then 1518 octets. */
383 CYG_WORD jbrc; /* as ospc + bad packets */
384 CYG_WORD p64c; /* received packets of 64 octets.. */
385 CYG_WORD p65c; /* received packets of 65-128 octets.. */
386 CYG_WORD p128c; /* received packets of 128-255 octets.. */
387 CYG_WORD p256c; /* received packets of 256-511 octets.. */
388 CYG_WORD p512c; /* received packets of 512-1023 octets.. */
389 CYG_WORD p1024c; /* received packets of 1024-1518 octets.. */
390 CYG_WORD cam_buf; /* cam respond internal buffer. */
391 CYG_WORD16 rfthr; /* received frames threshold */
392 CYG_WORD16 rfcnt; /* received frames count */
393 } _PackedType t_EnetFcc_Pram;
396 /*-----------------*/
397 /* FCC Common PRAM */
398 /*-----------------*/
400 typedef _Packed struct
402 CYG_WORD16 riptr; /* Rx internal temporary data pointer. */
403 CYG_WORD16 tiptr; /* Tx internal temporary data pointer. */
404 CYG_WORD16 reserved0; /* Reserved */
405 CYG_WORD16 mrblr; /* Rx buffer length */
406 CYG_WORD rstate; /* Rx internal state */
407 CYG_WORD rbase; /* RX BD base address */
408 CYG_WORD16 rbdstat; /* Rx BD status and control */
409 CYG_WORD16 rbdlen; /* Rx BD data length */
410 CYG_WORD rdptr; /* rx BD data pointer */
411 CYG_WORD tstate; /* Tx internal state */
412 CYG_WORD tbase; /* TX BD base address */
413 CYG_WORD16 tbdstat; /* Tx BD status and control */
414 CYG_WORD16 tbdlen; /* Tx BD data length */
415 CYG_WORD tdptr; /* Tx data pointer */
416 CYG_WORD rbptr; /* rx BD pointer */
417 CYG_WORD tbptr; /* Tx BD pointer */
418 CYG_WORD rcrc; /* Temp receive CRC */
419 CYG_WORD reserved_1[0x1];
420 CYG_WORD tcrc; /* Temp transmit CRC */
421 union /* Protocol-Specific parameter ram */
426 } _PackedType t_Fcc_Pram;
430 /*---------------------------------------------------------------------------*/
431 /* MULTICHANNEL COMMUNICATION CONTROLLER (MCC) */
432 /*---------------------------------------------------------------------------*/
434 /******************************************************************************
435 * Note that each MCC uses multiple logical channels. We first define the *
436 * PRAM for a logical channel (which can be used in either HDLC or Transparent *
437 * mode; wherever there are differences, it is specified), followed by the *
438 * PRAM for an MCC itself. *
439 ******************************************************************************/
441 /*---------------------*/
442 /* MCC Logical Channel */
443 /*---------------------*/
445 typedef _Packed struct
447 CYG_WORD tstate; /* Tx internal state. */
448 CYG_WORD zistate; /* Zero insertion machine state. */
449 CYG_WORD zidata0; /* Zero insertion high CYG_WORD16. */
450 CYG_WORD zidata1; /* Zero insertion low CYG_WORD16. */
451 CYG_WORD16 tbdflags; /* Tx internal BD flags. */
452 CYG_WORD16 tbdcnt; /* Tx internal byte count . */
453 CYG_WORD tbdptr; /* Tx internal data pointer. */
454 CYG_WORD16 intmask; /* Interrupt mask flags. */
455 CYG_WORD16 chamr; /* channel mode register. */
456 CYG_WORD tcrc; /* Transparent: reserved. */
457 /* Hdlc: Temp receive CRC.*/
458 CYG_WORD rstate; /* Rx internal state. */
459 CYG_WORD zdstate; /* Zero deletion machine state. */
460 CYG_WORD zddata0; /* Zero deletion high CYG_WORD16. */
461 CYG_WORD zddata1; /* Zero deletion low CYG_WORD16. */
462 CYG_WORD16 rbdflags; /* Rx internal BD flags. */
463 CYG_WORD16 rbdcnt; /* Rx internal byte count . */
464 CYG_WORD rbdptr; /* Rx internal data pointer. */
465 CYG_WORD16 maxrlen; /* Transparent: Max receive buffer length. */
466 /* Hdlc: Max receive frame length. */
467 CYG_WORD16 sync_maxcnt;/* Transparent: Receive synchronization pattern*/
468 /* Hdlc: Max length counter. */
469 CYG_WORD rcrc; /* Transparent: reserved. */
470 /* Hdlc: Temp receive CRC.*/
471 } _PackedType t_Mch_Pram;
478 typedef _Packed struct
480 CYG_WORD mccbase; /* A pointer to starting address of BD rings. */
481 CYG_WORD16 mccstate; /* Controller state. */
482 CYG_WORD16 mrblr; /* Maximum receive buffer length. */
483 CYG_WORD16 grfthr; /* Global receive frame threshold. */
484 CYG_WORD16 grfcnt; /* Global receive frame counter. */
485 CYG_WORD rinttmp; /* Temp location for receive interrupt table entry. */
486 CYG_WORD data0; /* Temporary location for holding data. */
487 CYG_WORD data1; /* Temporary location for holding data. */
488 CYG_WORD tintbase; /* Transmit interrupt table base address. */
489 CYG_WORD tintptr; /* Transmit interrupt table pointer. */
490 CYG_WORD tinttmp; /* Temp location for receive interrupt table entry. */
491 CYG_WORD16 sctpbase; /* A pointer to the super channel transmit table*/
492 CYG_BYTE res0[0x2]; /* Reserved area */
493 CYG_WORD c_mask32; /* CRC constant. */
494 CYG_WORD16 xtrabase; /* A pointer to the beginning of extra parameters */
495 CYG_WORD16 c_mask16; /* CRC constant. */
496 CYG_WORD rinttmp0; /* Temp location for receive interrupt table entry. */
497 CYG_WORD rinttmp1; /* Temp location for receive interrupt table entry. */
498 CYG_WORD rinttmp2; /* Temp location for receive interrupt table entry. */
499 CYG_WORD rinttmp3; /* Temp location for receive interrupt table entry. */
500 CYG_WORD rintbase0; /* Receive interrupt table base address. */
501 CYG_WORD rintptr0; /* Receive interrupt table pointer. */
502 CYG_WORD rintbase1; /* Receive interrupt table base address. */
503 CYG_WORD rintptr1; /* Receive interrupt table pointer. */
504 CYG_WORD rintbase2; /* Receive interrupt table base address. */
505 CYG_WORD rintptr2; /* Receive interrupt table pointer. */
506 CYG_WORD rintbase3; /* Receive interrupt table base address. */
507 CYG_WORD rintptr3; /* Receive interrupt table pointer. */
509 } _PackedType t_Mcc_Pram;
513 /*---------------------------------------------------------------------------*/
514 /* ATM PARAMETER RAM */
515 /*---------------------------------------------------------------------------*/
518 /*--------------------------------------*/
519 /* Address Compression parameters table */
520 /*--------------------------------------*/
522 _Packed struct AddressCompressionPram
524 volatile CYG_WORD VptBase; /* VP-level addressing table base address */
525 volatile CYG_WORD VctBase; /* VC-level addressing table base address */
526 volatile CYG_WORD Vpt1Base; /* VP1-level addressing table base address */
527 volatile CYG_WORD Vct1Base; /* VC1-level addressing table base address */
528 volatile CYG_WORD16 VpMask; /* VP mask for address compression look-up */
532 /*-------------------------------*/
533 /* External CAM parameters table */
534 /*-------------------------------*/
536 _Packed struct ExtCamPram
538 volatile CYG_WORD ExtCamBase; /* Base address of the external CAM */
539 volatile CYG_BYTE reserved00[4]; /* Reserved */
540 volatile CYG_WORD ExtCam1Base; /* Base address of the external CAM1 */
541 volatile CYG_BYTE reserved01[6]; /* Reserved */
545 /*---------------------------*/
546 /* ATM mode parameters table */
547 /*---------------------------*/
549 typedef _Packed struct AtmPram
551 volatile CYG_BYTE reserved0[64]; /* Reserved */
552 volatile CYG_WORD16 RxCellTmpBase; /* Rx cell temporary base address */
553 volatile CYG_WORD16 TxCellTmpBase; /* Tx cell temporary base address */
554 volatile CYG_WORD16 UdcTmpBase; /* UDC temp base address (in UDC mode only) */
555 volatile CYG_WORD16 IntRctBase; /* Internal RTC base address */
556 volatile CYG_WORD16 IntTctBase; /* Internal TCT base address */
557 volatile CYG_WORD16 IntTcteBase; /* Internal ACT base address */
558 volatile CYG_BYTE reserved1[4]; /* reserved four bytes */
559 volatile CYG_WORD ExtRctBase; /* Extrnal RTC base address */
560 volatile CYG_WORD ExtTctBase; /* Extrnal TCT base address */
561 volatile CYG_WORD ExtTcteBase; /* Extrnal ACT base address */
562 volatile CYG_WORD16 UeadOffset; /* The offset in half-wordunits of the UEAD
563 entry in the UDC extra header. Should be
564 even address. If little-endian format is
565 used, the UeadOffset is of the little-endian
567 volatile CYG_BYTE reserved2[2]; /* Reserved */
568 volatile CYG_WORD16 PmtBase; /* Performance monitoring table base address */
569 volatile CYG_WORD16 ApcParamBase; /* APC Parameters table base address */
570 volatile CYG_WORD16 FbpParamBase; /* Free buffer pool parameters base address */
571 volatile CYG_WORD16 IntQParamBase; /* Interrupt queue parameters table base */
572 volatile CYG_BYTE reserved3[2];
573 volatile CYG_WORD16 UniStatTableBase; /* UNI statistics table base */
574 volatile CYG_WORD BdBaseExt; /* BD ring base address extension */
577 struct AddressCompressionPram AddrCompression;
578 struct ExtCamPram ExtCam;
579 } AddrMapping; /* Address look-up mechanism */
580 volatile CYG_WORD16 VciFiltering; /* VCI filtering enable bits. If bit i is set,
581 the cell with VCI=i will be sent to the
582 raw cell queue. The bits 0-2 and 5 should
584 volatile CYG_WORD16 Gmode; /* Global mode */
585 volatile CYG_WORD16 CommInfo1; /* The information field associated with the */
586 volatile CYG_WORD CommInfo2; /* last host command */
587 volatile CYG_BYTE reserved4[4]; /* Reserved */
588 volatile CYG_WORD CRC32Preset; /* Preset for CRC32 */
589 volatile CYG_WORD CRC32Mask; /* Constant mask for CRC32 */
590 volatile CYG_WORD16 AAL1SnpTableBase; /* AAl1 SNP protection look-up table base */
591 volatile CYG_WORD16 reserved5; /* Reserved */
592 volatile CYG_WORD SrtsBase; /* External SRTS logic base address. For AAL1
593 only. Should be 16 bytes aligned */
594 volatile CYG_WORD16 IdleBase; /* Idle cell base address */
595 volatile CYG_WORD16 IdleSize; /* Idle cell size: 52, 56, 60, 64 */
596 volatile CYG_WORD EmptyCellPayload; /* Empty cell payload (little-indian) */
598 /* ABR specific only */
599 volatile CYG_WORD Trm; /* Upper bound on time between F-RM cells for active source */
600 volatile CYG_WORD16 Nrm; /* Controls the maximum data cells sent for each F-RM cell. */
601 volatile CYG_WORD16 Mrm; /* Controls bandwidth between F-RM, B-RM and user data cell */
602 volatile CYG_WORD16 Tcr; /* Tag cell rate */
603 volatile CYG_WORD16 AbrRxTcte; /* ABR reserved area address (2-CYG_WORD16 aligned)*/
604 volatile CYG_BYTE reserved7[76]; /* Reserved */
605 } _PackedType t_Atm_Pram;
609 /*---------------------------------------------------------------------------*/
610 /* SERIAL MANAGEMENT CHANNEL (SMC) */
611 /*---------------------------------------------------------------------------*/
613 typedef _Packed struct
615 CYG_WORD16 rbase; /* Rx BD Base Address */
616 CYG_WORD16 tbase; /* Tx BD Base Address */
617 CYG_BYTE rfcr; /* Rx function code */
618 CYG_BYTE tfcr; /* Tx function code */
619 CYG_WORD16 mrblr; /* Rx buffer length */
620 CYG_WORD rstate; /* Rx internal state */
621 CYG_WORD rptr; /* Rx internal data pointer */
622 CYG_WORD16 rbptr; /* rb BD Pointer */
623 CYG_WORD16 rcount; /* Rx internal byte count */
624 CYG_WORD rtemp; /* Rx temp */
625 CYG_WORD tstate; /* Tx internal state */
626 CYG_WORD tptr; /* Tx internal data pointer */
627 CYG_WORD16 tbptr; /* Tx BD pointer */
628 CYG_WORD16 tcount; /* Tx byte count */
629 CYG_WORD ttemp; /* Tx temp */
631 /* SMC UART-specific PRAM */
632 CYG_WORD16 max_idl; /* Maximum IDLE Characters */
633 CYG_WORD16 idlc; /* Temporary IDLE Counter */
634 CYG_WORD16 brkln; /* Last Rx Break Length */
635 CYG_WORD16 brkec; /* Rx Break Condition Counter */
636 CYG_WORD16 brkcr; /* Break Count Register (Tx) */
637 CYG_WORD16 r_mask; /* Temporary bit mask */
639 } _PackedType t_Smc_Pram;
643 /*---------------------------------------------------------------------------*/
644 /* IDMA PARAMETER RAM */
645 /*---------------------------------------------------------------------------*/
647 typedef _Packed struct
649 CYG_WORD16 ibase; /* IDMA BD Base Address */
650 CYG_WORD16 dcm; /* DMA channel mode register */
651 CYG_WORD16 ibdptr; /* next bd ptr */
652 CYG_WORD16 DPR_buf; /* ptr to internal 64 byte buffer */
653 CYG_WORD16 BUF_inv; /* The quantity of data in DPR_buf */
654 CYG_WORD16 SS_max; /* Steady State Max. transfer size */
655 CYG_WORD16 DPR_in_ptr; /* write ptr for the internal buffer */
656 CYG_WORD16 sts; /* Source Transfer Size */
657 CYG_WORD16 DPR_out_ptr; /* read ptr for the internal buffer */
658 CYG_WORD16 seob; /* Source end of burst */
659 CYG_WORD16 deob; /* Destination end of burst */
660 CYG_WORD16 dts; /* Destination Transfer Size */
661 CYG_WORD16 RetAdd; /* return address when ERM==1 */
662 CYG_WORD16 Reserved; /* reserved */
663 CYG_WORD BD_cnt; /* Internal byte count */
664 CYG_WORD S_ptr; /* source internal data ptr */
665 CYG_WORD D_ptr; /* destination internal data ptr */
666 CYG_WORD istate; /* Internal state */
668 } _PackedType t_Idma_Pram;
672 /*-------------------------------------------------------------------*/
673 /* INTER-INTEGRATED CIRCUIT (I2C) */
674 /*-------------------------------------------------------------------*/
676 typedef _Packed struct
678 CYG_WORD16 rbase; /* RX BD base address */
679 CYG_WORD16 tbase; /* TX BD base address */
680 CYG_BYTE rfcr; /* Rx function code */
681 CYG_BYTE tfcr; /* Tx function code */
682 CYG_WORD16 mrblr; /* Rx buffer length */
683 CYG_WORD rstate; /* Rx internal state */
684 CYG_WORD rptr; /* Rx internal data pointer */
685 CYG_WORD16 rbptr; /* rb BD Pointer */
686 CYG_WORD16 rcount; /* Rx internal byte count */
687 CYG_WORD rtemp; /* Rx temp */
688 CYG_WORD tstate; /* Tx internal state */
689 CYG_WORD tptr; /* Tx internal data pointer */
690 CYG_WORD16 tbptr; /* Tx BD pointer */
691 CYG_WORD16 tcount; /* Tx byte count */
692 CYG_WORD ttemp; /* Tx temp */
694 } _PackedType t_I2c_Pram;
698 /*---------------------------------------------------------------------------*/
699 /* SERIAL PERIPHERAL INTERFACE (SPI) */
700 /*---------------------------------------------------------------------------*/
702 typedef _Packed struct
704 CYG_WORD16 rbase; /* Rx BD Base Address */
705 CYG_WORD16 tbase; /* Tx BD Base Address */
706 CYG_BYTE rfcr; /* Rx function code */
707 CYG_BYTE tfcr; /* Tx function code */
708 CYG_WORD16 mrblr; /* Rx buffer length */
709 CYG_WORD rstate; /* Rx internal state */
710 CYG_WORD rptr; /* Rx internal data pointer */
711 CYG_WORD16 rbptr; /* Rx BD Pointer */
712 CYG_WORD16 rcount; /* Rx internal byte count */
713 CYG_WORD rtemp; /* Rx temp */
714 CYG_WORD tstate; /* Tx internal state */
715 CYG_WORD tptr; /* Tx internal data pointer */
716 CYG_WORD16 tbptr; /* Tx BD pointer */
717 CYG_WORD16 tcount; /* Tx byte count */
718 CYG_WORD ttemp; /* Tx temp */
719 CYG_BYTE reserved[8];
721 } _PackedType t_Spi_Pram;
725 /*---------------------------------------------------------------------------*/
726 /* RISC TIMER PARAMETER RAM */
727 /*---------------------------------------------------------------------------*/
729 typedef _Packed struct
732 CYG_WORD16 tm_base; /* RISC timer table base adr */
733 CYG_WORD16 tm_ptr; /* RISC timer table pointer */
734 CYG_WORD16 r_tmr; /* RISC timer mode register */
735 CYG_WORD16 r_tmv; /* RISC timer valid register */
736 CYG_WORD tm_cmd; /* RISC timer cmd register */
737 CYG_WORD tm_cnt; /* RISC timer internal cnt */
738 } _PackedType t_timer_pram;
742 /*--------------------------------------------------------------------------*/
743 /* ROM MICROCODE PARAMETER RAM AREA */
744 /*--------------------------------------------------------------------------*/
746 typedef _Packed struct
748 CYG_WORD16 rev_num; /* Ucode Revision Number */
749 CYG_WORD16 d_ptr; /* MISC Dump area pointer */
750 } _PackedType t_ucode_pram;
752 /*--------------------------------------------------------------------------*/
753 /* MAIN DEFINITION OF MPC8260 INTERNAL MEMORY MAP */
754 /*--------------------------------------------------------------------------*/
756 typedef _Packed struct
760 t_Mch_Pram mch_pram[256]; /* MCC logical channels parameter ram */
761 volatile CYG_BYTE reserved0[0x4000]; /* Reserved area */
767 /*for access to the PRAM structs for SCCs, FCCs, and MCCs */
770 t_Scc_Pram scc_pram[4];
771 t_Fcc_Pram fcc_pram[3];
772 t_Mcc_Pram mcc_pram[2];
773 volatile CYG_BYTE reserved1[0x700];
776 /* for access to ATM PRAM structs */
779 volatile CYG_BYTE reserved2[0x400];
780 t_Atm_Pram atm_pram[2];
781 volatile CYG_BYTE reserved3[0xa00];
784 /* for access to the memory locations holding user-defined
785 base addresses of PRAM for SMCs, IDMA, SPI, and I2C. */
788 volatile CYG_BYTE scc1[0x100];
789 volatile CYG_BYTE scc2[0x100];
790 volatile CYG_BYTE scc3[0x100];
791 volatile CYG_BYTE scc4[0x100];
792 volatile CYG_BYTE fcc1[0x100];
793 volatile CYG_BYTE fcc2[0x100];
794 volatile CYG_BYTE fcc3[0x100];
795 volatile CYG_BYTE mcc1[0x80];
796 volatile CYG_BYTE reserved_0[0x7c];
797 volatile CYG_BYTE smc1[0x2];
798 volatile CYG_BYTE idma1[0x2];
799 volatile CYG_BYTE mcc2[0x80];
800 volatile CYG_BYTE reserved_1[0x7c];
801 volatile CYG_BYTE smc2[0x2];
802 volatile CYG_BYTE idma2[0x2];
803 volatile CYG_BYTE reserved_2[0xfc];
804 volatile CYG_BYTE spi[0x2];
805 volatile CYG_BYTE idma3[0x2];
806 volatile CYG_BYTE reserved_3[0xe0];
807 volatile CYG_BYTE timers[0x10];
808 volatile CYG_BYTE Rev_num[0x2];
809 volatile CYG_BYTE D_ptr[0x2];
810 volatile CYG_BYTE reserved_4[0x4];
811 volatile CYG_BYTE rand[0x4];
812 volatile CYG_BYTE i2c[0x2];
813 volatile CYG_BYTE idma4[0x2];
814 volatile CYG_BYTE reserved_5[0x500];
819 volatile CYG_BYTE reserved11[0x2000]; /* Reserved area */
820 volatile CYG_BYTE cpm_ram_dpram_2[0x1000]; /* Internal RAM */
821 volatile CYG_BYTE reserved12[0x4000]; /* Reserved area */
824 volatile CYG_WORD siu_siumcr; /* SIU Module Configuration Register */
825 volatile CYG_WORD siu_sypcr; /* System Protection Control Register */
826 volatile CYG_BYTE reserved13[0x6]; /* Reserved area */
827 volatile CYG_WORD16 siu_swsr; /* Software Service Register */
830 volatile CYG_BYTE reserved14[0x14]; /* Reserved area */
831 volatile CYG_WORD bcr; /* Bus Configuration Register */
832 volatile CYG_BYTE ppc_acr; /* Arbiter Configuration Register */
833 volatile CYG_BYTE reserved15[0x3]; /* Reserved area */
834 volatile CYG_WORD ppc_alrh; /* Arbitration level Register (First clients)*/
835 volatile CYG_WORD ppc_alrl; /* Arbitration Level Register (Next clients) */
836 volatile CYG_BYTE lcl_acr; /* LCL Arbiter Configuration Register */
837 volatile CYG_BYTE reserved16[0x3]; /* Reserved area */
838 volatile CYG_WORD lcl_alrh; /* LCL Arbitration level Register (First clients)*/
839 volatile CYG_WORD lcl_alrl; /* LCL Arbitration Level Register (Next clients) */
840 volatile CYG_WORD tescr1; /* PPC bus transfer error status control register 1 */
841 volatile CYG_WORD tescr2; /* PPC bus transfer error status control register 2 */
842 volatile CYG_WORD ltescr1; /* Local bus transfer error status control register 1 */
843 volatile CYG_WORD ltescr2; /* Local bus transfer error status control register 2 */
844 volatile CYG_WORD pdtea; /* PPC bus DMA Transfer Error Address */
845 volatile CYG_BYTE pdtem; /* PPC bus DMA Transfer Error MSNUM */
846 volatile CYG_BYTE reserved17[0x3]; /* Reserved area */
847 volatile CYG_WORD ldtea; /* PPC bus DMA Transfer Error Address */
848 volatile CYG_BYTE ldtem; /* PPC bus DMA Transfer Error MSNUM */
849 volatile CYG_BYTE reserved18[0xa3]; /* Reserved area */
854 volatile CYG_WORD memc_br; /* Base Register */
855 volatile CYG_WORD memc_or; /* Option Register */
857 volatile CYG_BYTE reserved19[0x8]; /* Reserved area */
858 volatile CYG_WORD memc_mar; /* Memory Address Register */
859 volatile CYG_BYTE reserved20[0x4]; /* Reserved area */
860 volatile CYG_WORD memc_mamr; /* Machine A Mode Register */
861 volatile CYG_WORD memc_mbmr; /* Machine B Mode Register */
862 volatile CYG_WORD memc_mcmr; /* Machine C Mode Register */
863 volatile CYG_WORD memc_mdmr; /* Machine D Mode Register */
864 volatile CYG_BYTE reserved21[0x4]; /* Reserved area */
865 volatile CYG_WORD16 memc_mptpr; /* Memory Periodic Timer Prescaler */
866 volatile CYG_BYTE reserved22[0x2]; /* Reserved area */
867 volatile CYG_WORD memc_mdr; /* Memory Data Register */
868 volatile CYG_BYTE reserved23[0x4]; /* Reserved area */
869 volatile CYG_WORD memc_psdmr; /* PowerPC Bus SDRAM machine Mode Register */
870 volatile CYG_WORD memc_lsdmr; /* Local Bus SDRAM machine Mode Registe */
871 volatile CYG_BYTE memc_purt; /* PowerPC Bus assigned UPM Refresh Timer */
872 volatile CYG_BYTE reserved24[0x3]; /* Reserved area */
873 volatile CYG_BYTE memc_psrt; /* PowerPC BusBus assigned SDRAM Refresh Timer */
874 volatile CYG_BYTE reserved25[0x3]; /* Reserved area */
875 volatile CYG_BYTE memc_lurt; /* Local Bus assigned UPM Refresh Timer */
876 volatile CYG_BYTE reserved26[0x3]; /* Reserved area */
877 volatile CYG_BYTE memc_lsrt; /* Local Bus assigned SDRAM Refresh Timer */
878 volatile CYG_BYTE reserved27[0x3]; /* Reserved area */
879 volatile CYG_WORD memc_immr; /* Internal Memory Map Register */
882 volatile CYG_WORD pcibr0; /* Base address+valid for PCI window 1 */
883 volatile CYG_WORD pcibr1; /* Base address+valid for PCI window 2 */
884 volatile CYG_BYTE reserved28[0x10]; /* Reserved area */
885 volatile CYG_WORD pcimsk0; /* Mask for PCI window 1 */
886 volatile CYG_WORD pcimsk1; /* Mask for PCI window 2 */
887 volatile CYG_BYTE reserved29[0x54]; /* Reserved area */
890 volatile CYG_WORD16 si_timers_tmcntsc; /* Time Counter Status and Control Register */
891 volatile CYG_BYTE reserved30[0x2]; /* Reserved area */
892 volatile CYG_WORD si_timers_tmcnt; /* Time Counter Register */
893 volatile CYG_WORD si_timers_tmcntsec; /* Time Counter Seconds*/
894 volatile CYG_WORD si_timers_tmcntal; /* Time Counter Alarm Register */
895 volatile CYG_BYTE reserved31[0x10]; /* Reserved area */
896 volatile CYG_WORD16 si_timers_piscr; /* Periodic Interrupt Status and Control Reg. */
897 volatile CYG_BYTE reserved32[0x2]; /* Reserved area */
898 volatile CYG_WORD si_timers_pitc; /* Periodic Interrupt Count Register */
899 volatile CYG_WORD si_timers_pitr; /* Periodic Interrupt Timer Register */
900 volatile CYG_BYTE reserved33[0x54]; /* Reserved area */
902 /* test module registers */
903 volatile CYG_WORD tstmhr;
904 volatile CYG_WORD tstmlr;
905 volatile CYG_WORD16 tster;
906 volatile CYG_BYTE reserved34[0x156]; /* Reserved area */
909 volatile CYG_WORD pci_pci; /* PCI Configuration space */
910 volatile CYG_BYTE reserved35[0x7fc]; /* Reserved area */
913 volatile CYG_WORD16 ic_sicr; /* Interrupt Configuration Register */
914 volatile CYG_BYTE reserved36[0x2]; /* Reserved area */
915 volatile CYG_WORD ic_sivec; /* CP Interrupt Vector Register */
916 volatile CYG_WORD ic_sipnr_h; /* Interrupt Pending Register (HIGH) */
917 volatile CYG_WORD ic_sipnr_l; /* Interrupt Pending Register (LOW) */
918 volatile CYG_WORD ic_siprr; /* SIU Interrupt Priority Register */
919 volatile CYG_WORD ic_scprr_h; /* Interrupt Priority Register (HIGH) */
920 volatile CYG_WORD ic_scprr_l; /* Interrupt Priority Register (LOW) */
921 volatile CYG_WORD ic_simr_h; /* Interrupt Mask Register (HIGH) */
922 volatile CYG_WORD ic_simr_l; /* Interrupt Mask Register (LOW) */
923 volatile CYG_WORD ic_siexr; /* External Interrupt Control Register */
924 volatile CYG_BYTE reserved37[0x58]; /* Reserved area */
927 volatile CYG_WORD clocks_sccr; /* System Clock Control Register */
928 volatile CYG_BYTE reserved38[0x4]; /* Reserved area */
929 volatile CYG_WORD clocks_scmr; /* System Clock Mode Register */
930 volatile CYG_BYTE reserved39[0x4]; /* Reserved area */
931 volatile CYG_WORD clocks_rsr; /* Reset Status Register */
932 volatile CYG_WORD clocks_rmr; /* Reset Moode Register */
933 volatile CYG_BYTE reserved40[0x68]; /* Reserved area */
938 volatile CYG_WORD pdir; /* Port A-D Data Direction Register */
939 volatile CYG_WORD ppar; /* Port A-D Pin Assignment Register */
940 volatile CYG_WORD psor; /* Port A-D Special Operation Register */
941 volatile CYG_WORD podr; /* Port A-D Open Drain Register */
942 volatile CYG_WORD pdat; /* Port A-D Data Register */
943 volatile CYG_BYTE reserved41[0xc]; /* Reserved area */
947 volatile CYG_BYTE cpm_timers_tgcr1; /* Timer Global Configuration Register */
948 volatile CYG_BYTE reserved42[0x3]; /* Reserved area */
949 volatile CYG_BYTE cpm_timers_tgcr2; /* Timer Global Configuration Register */
950 volatile CYG_BYTE reserved43[0xb]; /* Reserved area */
951 volatile CYG_WORD16 cpm_timers_tmr1; /* Timer Mode Register */
952 volatile CYG_WORD16 cpm_timers_tmr2; /* Timer Mode Register */
953 volatile CYG_WORD16 cpm_timers_trr1; /* Timer Reference Register */
954 volatile CYG_WORD16 cpm_timers_trr2; /* Timer Reference Register */
955 volatile CYG_WORD16 cpm_timers_tcr1; /* Timer Capture Register */
956 volatile CYG_WORD16 cpm_timers_tcr2; /* Timer Capture Register */
957 volatile CYG_WORD16 cpm_timers_tcn1; /* Timer Counter */
958 volatile CYG_WORD16 cpm_timers_tcn2; /* Timer Counter */
959 volatile CYG_WORD16 cpm_timers_tmr3; /* Timer Mode Register */
960 volatile CYG_WORD16 cpm_timers_tmr4; /* Timer Mode Register */
961 volatile CYG_WORD16 cpm_timers_trr3; /* Timer Reference Register */
962 volatile CYG_WORD16 cpm_timers_trr4; /* Timer Reference Register */
963 volatile CYG_WORD16 cpm_timers_tcr3; /* Timer Capture Register */
964 volatile CYG_WORD16 cpm_timers_tcr4; /* Timer Capture Register */
965 volatile CYG_WORD16 cpm_timers_tcn3; /* Timer Counter */
966 volatile CYG_WORD16 cpm_timers_tcn4; /* Timer Counter */
967 volatile CYG_WORD16 cpm_timers_ter[4]; /* Timer Event Register */
968 volatile CYG_BYTE reserved44[0x260]; /* Reserved area */
971 volatile CYG_BYTE sdma_sdsr; /* SDMA Status Register */
972 volatile CYG_BYTE reserved45[0x3]; /* Reserved area */
973 volatile CYG_BYTE sdma_sdmr; /* SDMA Mask Register */
974 volatile CYG_BYTE reserved46[0x3]; /* Reserved area */
977 volatile CYG_BYTE idma_idsr1; /* IDMA Status Register */
978 volatile CYG_BYTE reserved47[0x3]; /* Reserved area */
979 volatile CYG_BYTE idma_idmr1; /* IDMA Mask Register */
980 volatile CYG_BYTE reserved48[0x3]; /* Reserved area */
981 volatile CYG_BYTE idma_idsr2; /* IDMA Status Register */
982 volatile CYG_BYTE reserved49[0x3]; /* Reserved area */
983 volatile CYG_BYTE idma_idmr2; /* IDMA Mask Register */
984 volatile CYG_BYTE reserved50[0x3]; /* Reserved area */
985 volatile CYG_BYTE idma_idsr3; /* IDMA Status Register */
986 volatile CYG_BYTE reserved51[0x3]; /* Reserved area */
987 volatile CYG_BYTE idma_idmr3; /* IDMA Mask Register */
988 volatile CYG_BYTE reserved52[0x3]; /* Reserved area */
989 volatile CYG_BYTE idma_idsr4; /* IDMA Status Register */
990 volatile CYG_BYTE reserved53[0x3]; /* Reserved area */
991 volatile CYG_BYTE idma_idmr4; /* IDMA Mask Register */
992 volatile CYG_BYTE reserved54[0x2c3]; /* Reserved area */
997 volatile CYG_WORD fcc_gfmr; /* FCC General Mode Register */
998 volatile CYG_WORD fcc_psmr; /* FCC Protocol Specific Mode Register */
999 volatile CYG_WORD16 fcc_todr; /* FCC Transmit On Demand Register */
1000 volatile CYG_BYTE reserved55[0x2]; /* Reserved area */
1001 volatile CYG_WORD16 fcc_dsr; /* FCC Data Sync. Register */
1002 volatile CYG_BYTE reserved56[0x2]; /* Reserved area */
1003 volatile CYG_WORD fcc_fcce; /* FCC Event Register */
1004 volatile CYG_WORD fcc_fccm; /* FCC Mask Register */
1005 volatile CYG_BYTE fcc_fccs; /* FCC Status Register */
1006 volatile CYG_BYTE reserved57[0x3]; /* Reserved area */
1007 volatile CYG_WORD fcc_ftprr; /* FCC Transmit Partial Rate Register */
1009 volatile CYG_BYTE reserved58[0x290]; /* Reserved area */
1011 /* brgs 5 through 8 */
1012 volatile CYG_WORD brgs_brgc5; /* Baud Rate Generator 5 Config Register */
1013 volatile CYG_WORD brgs_brgc6; /* Baud Rate Generator 6 Config Register */
1014 volatile CYG_WORD brgs_brgc7; /* Baud Rate Generator 7 Config Register */
1015 volatile CYG_WORD brgs_brgc8; /* Baud Rate Generator 8 Config Register */
1016 volatile CYG_BYTE reserved59[0x260]; /* Reserved area */
1019 volatile CYG_BYTE i2c_i2mod; /* IC Mode Register */
1020 volatile CYG_BYTE reserved60[0x3]; /* Reserved area */
1021 volatile CYG_BYTE i2c_i2add; /* IC Address Register */
1022 volatile CYG_BYTE reserved61[0x3]; /* Reserved area */
1023 volatile CYG_BYTE i2c_i2brg; /* IC BRG Register */
1024 volatile CYG_BYTE reserved62[0x3]; /* Reserved area */
1025 volatile CYG_BYTE i2c_i2com; /* IC Command Register */
1026 volatile CYG_BYTE reserved63[0x3]; /* Reserved area */
1027 volatile CYG_BYTE i2c_i2cer; /* IC Event Register */
1028 volatile CYG_BYTE reserved64[0x3]; /* Reserved area */
1029 volatile CYG_BYTE i2c_i2cmr; /* IC Mask Register */
1030 volatile CYG_BYTE reserved65[0x14b]; /* Reserved area */
1033 volatile CYG_WORD cpm_cpcr; /* Communication Processor Command Register */
1034 volatile CYG_WORD cpm_rccr; /* RISC Configuration Register */
1035 volatile CYG_WORD cpm_rmdr; /* RISC Microcode Dev. Support Control Reg. */
1036 volatile CYG_WORD16 cpm_rctr1; /* RISC Controller Trap Register */
1037 volatile CYG_WORD16 cpm_rctr2; /* RISC Controller Trap Register */
1038 volatile CYG_WORD16 cpm_rctr3; /* RISC Controller Trap Register */
1039 volatile CYG_WORD16 cpm_rctr4; /* RISC Controller Trap Register */
1040 volatile CYG_BYTE reserved66[0x2]; /* Reserved area */
1041 volatile CYG_WORD16 cpm_rter; /* RISC Timers Event Register */
1042 volatile CYG_BYTE reserved67[0x2]; /* Reserved area */
1043 volatile CYG_WORD16 cpm_rtmr; /* RISC Timers Mask Register */
1044 volatile CYG_WORD16 cpm_rtscr; /* RISC Time-Stamp Timer Control Register */
1045 volatile CYG_WORD16 cpm_rmds; /* RISC Development Support Status Register */
1046 volatile CYG_WORD cpm_rtsr; /* RISC Time-Stamp Register */
1047 volatile CYG_BYTE reserved68[0xc]; /* Reserved area */
1049 /* brgs 1 through 4 */
1050 volatile CYG_WORD brgs_brgc1; /* Baud Rate Generator 5 Config Register */
1051 volatile CYG_WORD brgs_brgc2; /* Baud Rate Generator 2 Config Register */
1052 volatile CYG_WORD brgs_brgc3; /* Baud Rate Generator 3 Config Register */
1053 volatile CYG_WORD brgs_brgc4; /* Baud Rate Generator 4 Config Register */
1056 struct scc_regs_8260
1058 volatile CYG_WORD gsmr_l; /* SCC General Mode Register */
1059 volatile CYG_WORD gsmr_h; /* SCC General Mode Register */
1060 volatile CYG_WORD16 psmr; /* SCC Protocol Specific Mode Register */
1061 volatile CYG_BYTE reserved69[0x2]; /* Reserved area */
1062 volatile CYG_WORD16 todr; /* SCC Transmit-On-Demand Register */
1063 volatile CYG_WORD16 dsr; /* SCC Data Synchronization Register */
1064 volatile CYG_WORD16 scce; /* SCC Event Register */
1065 volatile CYG_BYTE reserved70[0x2]; /* Reserved area */
1066 volatile CYG_WORD16 sccm; /* SCC Mask Register */
1067 volatile CYG_BYTE reserved71; /* Reserved area */
1068 volatile CYG_BYTE sccs; /* SCC Status Register */
1069 volatile CYG_BYTE reserved72[0x8]; /* Reserved area */
1073 struct smc_regs_8260
1075 volatile CYG_BYTE reserved73[0x2]; /* Reserved area */
1076 volatile CYG_WORD16 smc_smcmr; /* SMC Mode Register */
1077 volatile CYG_BYTE reserved74[0x2]; /* Reserved area */
1078 volatile CYG_BYTE smc_smce; /* SMC Event Register */
1079 volatile CYG_BYTE reserved75[0x3]; /* Reserved area */
1080 volatile CYG_BYTE smc_smcm; /* SMC Mask Register */
1081 volatile CYG_BYTE reserved76[0x5]; /* Reserved area */
1085 volatile CYG_WORD16 spi_spmode; /* SPI Mode Register */
1086 volatile CYG_BYTE reserved77[0x4]; /* Reserved area */
1087 volatile CYG_BYTE spi_spie; /* SPI Event Register */
1088 volatile CYG_BYTE reserved78[0x3]; /* Reserved area */
1089 volatile CYG_BYTE spi_spim; /* SPI Mask Register */
1090 volatile CYG_BYTE reserved79[0x2]; /* Reserved area */
1091 volatile CYG_BYTE spi_spcom; /* SPI Command Register */
1092 volatile CYG_BYTE reserved80[0x52]; /* Reserved area */
1096 volatile CYG_BYTE cpm_mux_cmxsi1cr; /* CPM MUX SI Clock Route Register */
1097 volatile CYG_BYTE reserved81; /* Reserved area */
1098 volatile CYG_BYTE cpm_mux_cmxsi2cr; /* CPM MUX SI Clock Route Register */
1099 volatile CYG_BYTE reserved82; /* Reserved area */
1100 volatile CYG_WORD cpm_mux_cmxfcr; /* CPM MUX FCC Clock Route Register */
1101 volatile CYG_WORD cpm_mux_cmxscr; /* CPM MUX SCC Clock Route Register */
1102 volatile CYG_BYTE cpm_mux_cmxsmr; /* CPM MUX SMC Clock Route Register */
1103 volatile CYG_BYTE reserved83; /* Reserved area */
1104 volatile CYG_WORD16 cpm_mux_cmxuar; /* CPM MUX UTOPIA Address Register */
1105 volatile CYG_BYTE reserved84[0x10]; /* Reserved area */
1110 volatile CYG_WORD16 si_si1mr[4]; /* SI TDM Mode Registers */
1111 volatile CYG_BYTE si_si1gmr; /* SI Global Mode Register */
1112 volatile CYG_BYTE reserved85; /* Reserved area */
1113 volatile CYG_BYTE si_si1cmdr; /* SI Command Register */
1114 volatile CYG_BYTE reserved86; /* Reserved area */
1115 volatile CYG_BYTE si_si1str; /* SI Status Register */
1116 volatile CYG_BYTE reserved87; /* Reserved area */
1117 volatile CYG_WORD16 si_si1rsr; /* SI RAM Shadow Address Register */
1118 volatile CYG_WORD16 mcc_mcce; /* MCC Event Register */
1119 volatile CYG_BYTE reserved88[0x2]; /* Reserved area */
1120 volatile CYG_WORD16 mcc_mccm; /* MCC Mask Register */
1121 volatile CYG_BYTE reserved89[0x2]; /* Reserved area */
1122 volatile CYG_BYTE mcc_mccf; /* MCC Configuration Register */
1123 volatile CYG_BYTE reserved90[0x7]; /* Reserved area */
1125 volatile CYG_BYTE reserved91[0x4a0]; /* Reserved area */
1130 CYG_WORD16 si1_ram_si1_tx_ram[0x100]; /* SI Transmit Routing RAM */
1131 volatile CYG_BYTE reserved92[0x200]; /* Reserved area */
1132 CYG_WORD16 si1_ram_si1_rx_ram[0x100]; /* SI Receive Routing RAM */
1133 volatile CYG_BYTE reserved93[0x200]; /* Reserved area */
1135 volatile CYG_BYTE reserved94[0x1000]; /* Reserved area */
1137 } _PackedType t_PQ2IMM;
1143 /***************************************************************************/
1144 /* General Global Definitions */
1145 /***************************************************************************/
1147 #define PAGE1 0 /* SCC1 Index into SCC Param RAM Array */
1148 #define PAGE2 1 /* SCC2 Index into SCC Param RAM Array */
1149 #define PAGE3 2 /* SCC3 Index into SCC Param RAM Array */
1150 #define PAGE4 3 /* SCC4 Index into SCC Param RAM Array */
1152 #define SCC1 0 /* SCC1 Index into SCC Regs Array */
1153 #define SCC2 1 /* SCC2 Index into SCC Regs Array */
1154 #define SCC3 2 /* SCC3 Index into SCC Regs Array */
1155 #define SCC4 3 /* SCC4 Index into SCC Regs Array */
1157 #define SMC1 0 /* SMC1 Index into SMC Regs Array */
1158 #define SMC2 1 /* SMC2 Index into SMC Regs Array */
1160 #define PORT_A 0 /* Parallel port A registers */
1161 #define PORT_B 1 /* Parallel port B registers */
1162 #define PORT_C 2 /* Parallel port C registers */
1163 #define PORT_D 3 /* Parallel port D registers */
1165 /*--------------------------------*/
1166 /* KEEP ALIVE POWER REGISTERS KEY */
1167 /*--------------------------------*/
1169 #define KEEP_ALIVE_KEY 0x55ccaa33
1171 /*------------------------------------------*
1172 * CPM Command Register (CPCR) *
1173 *-------------------------------------------*
1174 * NOTE: This register is cleared by reset. *
1175 * See MPC8260 User's Manual. *
1176 *-------------------------------------------*/
1178 #define CPCR_RST 0x80000000 /* Software Reset Command */
1179 #define CPCR_FLG 0x00010000 /* Command Semaphore Flag */
1181 /*-----------------------------------------------*/
1182 /* Definitions for SCC CPCR Subblock/Page codes. */
1183 /*-----------------------------------------------*/
1185 #define SCC1_PAGE_SUBBLOCK 0x00800000 /* page 0, code = 4 */
1186 #define SCC2_PAGE_SUBBLOCK 0x04A00000 /* page 1, code = 5 */
1187 #define SCC3_PAGE_SUBBLOCK 0x08C00000 /* page 2, code = 6 */
1188 #define SCC4_PAGE_SUBBLOCK 0x0CE00000 /* page 3, code = 7 */
1190 /*-----------------------------------------------*/
1191 /* Definitions for SMC CPCR Subblock/Page codes. */
1192 /*-----------------------------------------------*/
1194 #define SMC1_PAGE_SUBBLOCK 0x1D000000 /* page 7, code = 8 */
1195 #define SMC2_PAGE_SUBBLOCK 0x21200000 /* page 8, code = 9 */
1197 /*-----------------------------*/
1198 /* Opcode definitions for SCCs, opcodes for SMC's are the same
1199 * except not all codes are valid for SMC */
1200 /*-----------------------------*/
1202 #define CPCR_INIT_TX_RX_PARAMS 0x00000000 /* Opcode 0 */
1203 #define CPCR_INIT_RX_PARAMS 0x00000001 /* Opcode 1 */
1204 #define CPCR_INIT_TX_PARAMS 0x00000002 /* Opcode 2 */
1205 #define CPCR_ENTER_HUNT_MODE 0x00000003 /* Opcode 3 */
1206 #define CPCR_STOP_TX 0x00000004 /* Opcode 4 */
1207 #define CPCR_GRACEFUL_STOP_TX 0x00000005 /* Opcode 5 */
1208 #define CPCR_RESTART_TX 0x00000006 /* Opcode 6 */
1209 #define CPCR_CLOSE_RX_BD 0x00000007 /* Opcode 7 */
1210 #define CPCR_SET_GRP_ADDR 0x00000008 /* Opcode 8 */
1211 #define CPCR_RESET_BCS 0x0000000A /* Opcode 10 */
1213 /*-----------------------------------------------------*/
1214 /* General Definitions for SCC CPCR Command Operations */
1215 /*-----------------------------------------------------*/
1217 #define READY_TO_RX_CMD 0x00000000
1219 /*-------------------------*/
1220 /* General SCC Definitions */
1221 /*-------------------------*/
1223 #define DISABLE_TX_RX 0xFFFFFFCF /* Clear the ENT/ENR bits in the GSMR
1224 Disables the transmit & Receive
1227 #define GSMR_L1_ENT 0x00000010 /* ENT bit for the GSMR low register */
1228 #define GSMR_L1_ENR 0x00000020 /* ENR bit for the GSMR low register */
1231 #define ALL_ONES 0xFFFF
1234 #endif // ifndef CYGONCE_HAL_PPC_QUICC2_MPC8260_H