packages/hal/powerpc/ppc60x/v2_0/include/var_cache.h

   1 #ifndef CYGONCE_VAR_CACHE_H
   2 #define CYGONCE_VAR_CACHE_H
   3 //=============================================================================
   4 //
   5 //      var_cache.h
   6 //
   7 //      Variant HAL cache control API
   8 //
   9 //=============================================================================
  10 //####ECOSGPLCOPYRIGHTBEGIN####
  11 // -------------------------------------------
  12 // This file is part of eCos, the Embedded Configurable Operating System.
  13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  14 // Copyright (C) 2002, 2003 Gary Thomas
  15 //
  16 // eCos is free software; you can redistribute it and/or modify it under
  17 // the terms of the GNU General Public License as published by the Free
  18 // Software Foundation; either version 2 or (at your option) any later version.
  19 //
  20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  22 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  23 // for more details.
  24 //
  25 // You should have received a copy of the GNU General Public License along
  26 // with eCos; if not, write to the Free Software Foundation, Inc.,
  27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  28 //
  29 // As a special exception, if other files instantiate templates or use macros
  30 // or inline functions from this file, or you compile this file and link it
  31 // with other works to produce a work based on this file, this file does not
  32 // by itself cause the resulting work to be covered by the GNU General Public
  33 // License. However the source code for this file must still be made available
  34 // in accordance with section (3) of the GNU General Public License.
  35 //
  36 // This exception does not invalidate any other reasons why a work based on
  37 // this file might be covered by the GNU General Public License.
  38 //
  39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  40 // at http://sources.redhat.com/ecos/ecos-license/
  41 // -------------------------------------------
  42 //####ECOSGPLCOPYRIGHTEND####
  43 //=============================================================================
  44 //#####DESCRIPTIONBEGIN####
  45 //
  46 // Author(s):   nickg
  47 // Contributors:nickg, jskov, gthomas
  48 // Date:        2000-04-02
  49 // Purpose:     Variant cache control API
  50 // Description: The macros defined here provide the HAL APIs for handling
  51 //              cache control operations on the PPC60x variant CPUs.
  52 // Usage:       Is included via the architecture cache header:
  53 //              #include <cyg/hal/hal_cache.h>
  54 //              ...
  55 //
  56 //####DESCRIPTIONEND####
  57 //
  58 //=============================================================================
  59
  60 #include <pkgconf/hal.h>
  61 #include <cyg/infra/cyg_type.h>
  62
  63 #include <cyg/hal/ppc_regs.h>
  64 #include <cyg/hal/plf_cache.h>
  65
  66
  67 //-----------------------------------------------------------------------------
  68 // Cache dimensions
  69
  70 // Data cache
  71 #ifndef HAL_DCACHE_SIZE
  72 #define HAL_DCACHE_SIZE                 16384   // Size of data cache in bytes
  73 #define HAL_DCACHE_LINE_SIZE            32      // Size of a data cache line
  74 #define HAL_DCACHE_WAYS                 4       // Associativity of the cache
  75 #endif
  76
  77 // Instruction cache
  78 #ifndef HAL_ICACHE_SIZE
  79 #define HAL_ICACHE_SIZE                 16384   // Size of cache in bytes
  80 #define HAL_ICACHE_LINE_SIZE            32      // Size of a cache line
  81 #define HAL_ICACHE_WAYS                 4       // Associativity of the cache
  82 #endif
  83
  84 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
  85 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
  86
  87 //-----------------------------------------------------------------------------
  88 // Global control of data cache
  89
  90 // Enable the data cache
  91 #define HAL_DCACHE_ENABLE()                     \
  92     CYG_MACRO_START                             \
  93     cyg_int32 _scratch;                         \
  94     asm volatile ("isync;"                      \
  95                   "mfspr %0,%1;"                \
  96                   "or  %0,%0,%2;"               \
  97                   "mtspr %1,%0"                 \
  98                   : "=&r" (_scratch)            \
  99                   : "I" (CYGARC_REG_HID0),      \
 100                     "r" (_HID0_DCE)             \
 101         );                                      \
 102     CYG_MACRO_END
 103
 104 // Disable the data cache
 105 #define HAL_DCACHE_DISABLE()                    \
 106     CYG_MACRO_START                             \
 107     cyg_int32 _scratch;                         \
 108     asm volatile ("isync;"                      \
 109                   "mfspr %0,%1;"                \
 110                   "andc %0,%0,%2;"              \
 111                   "mtspr %1,%0"                 \
 112                   : "=&r" (_scratch)            \
 113                   : "I" (CYGARC_REG_HID0),      \
 114                     "r" (_HID0_DCE)             \
 115         );                                      \
 116     CYG_MACRO_END
 117
 118 // Invalidate the entire cache
 119 #define HAL_DCACHE_INVALIDATE_ALL()             \
 120     CYG_MACRO_START                             \
 121     cyg_int32 _scr1, _scr2;                     \
 122     asm volatile ("isync;"                      \
 123                   "mfspr %0,%2;"                \
 124                   "mr %1,%0;"                   \
 125                   "or %0,%0,%3;"                \
 126                   "mtspr %2,%0;"                \
 127                   "mtspr %2,%1"                 \
 128                   : "=&r" (_scr1),              \
 129                     "=&r" (_scr2)               \
 130                   : "I" (CYGARC_REG_HID0),      \
 131                     "r" (_HID0_DCFI)            \
 132         );                                      \
 133     CYG_MACRO_END
 134
 135 // Synchronize the contents of the cache with memory.
 136 // Modifications to this macro should mirror modifications to the
 137 // identically named one in the mpc8260 variant.
 138 // We step through twice the number of lines in the cache in order
 139 // to ensure that all dirty lines are flushed to main memory.
 140 // (Consider the case where one of the dirty lines is in the
 141 // first 16Kbytes of RAM -- it won't get flushed by loading
 142 // in words from the first 16Kbytes of RAM).
 143 #define HAL_DCACHE_SYNC()                                       \
 144     CYG_MACRO_START                                             \
 145     cyg_int32 i;                                                \
 146     cyg_uint32 *__base = (cyg_uint32 *) (0);                    \
 147     for(i=0;i< (2 * HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE);i++,__base += HAL_DCACHE_LINE_SIZE/4){                                                 \
 148         asm volatile ("lwz %%r0,0(%0);"::"r"(__base):"r0");     \
 149     }                                                           \
 150     CYG_MACRO_END
 151
 152 // Query the state of the data cache
 153 #define HAL_DCACHE_IS_ENABLED(_state_)          \
 154     CYG_MACRO_START                             \
 155     cyg_int32 _scratch;                         \
 156     asm volatile ("isync;"                      \
 157                   "mfspr %0,%1;"                \
 158                   "and %0,%0,%2;"               \
 159                   : "=&r" (_scratch)            \
 160                   : "I" (CYGARC_REG_HID0),      \
 161                     "r" (_HID0_DCE)             \
 162         );                                      \
 163     (_state_) = _scratch != 0;                  \
 164     CYG_MACRO_END
 165
 166 // Set the data cache refill burst size
 167 //#define HAL_DCACHE_BURST_SIZE(_size_)
 168
 169 // Set the data cache write mode
 170 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
 171
 172 //#define HAL_DCACHE_WRITETHRU_MODE       0
 173 //#define HAL_DCACHE_WRITEBACK_MODE       1
 174
 175 // Load the contents of the given address range into the data cache
 176 // and then lock the cache so that it stays there.
 177 //#define HAL_DCACHE_LOCK(_base_, _size_)
 178
 179 // Undo a previous lock operation
 180 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
 181
 182 // Unlock entire cache
 183 //#define HAL_DCACHE_UNLOCK_ALL()
 184
 185 //-----------------------------------------------------------------------------
 186 // Data cache line control
 187
 188 // Allocate cache lines for the given address range without reading its
 189 // contents from memory.
 190 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
 191
 192 // Write dirty cache lines to memory and invalidate the cache entries
 193 // for the given address range.
 194 #define HAL_DCACHE_FLUSH( _base_ , _size_ )                     \
 195     CYG_MACRO_START                                             \
 196     cyg_uint32 __base = (cyg_uint32) (_base_);                  \
 197     cyg_int32 __size = (cyg_int32) (_size_);                    \
 198     while (__size > 0) {                                        \
 199         asm volatile ("dcbf 0,%0;sync;" : : "r" (__base));      \
 200         __base += HAL_DCACHE_LINE_SIZE;                         \
 201         __size -= HAL_DCACHE_LINE_SIZE;                         \
 202     }                                                           \
 203     CYG_MACRO_END
 204
 205 // Invalidate cache lines in the given range without writing to memory.
 206 #define HAL_DCACHE_INVALIDATE( _base_ , _size_ )                \
 207     CYG_MACRO_START                                             \
 208     cyg_uint32 __base = (cyg_uint32) (_base_);                  \
 209     cyg_int32 __size = (cyg_int32) (_size_);                    \
 210     while (__size > 0) {                                        \
 211         asm volatile ("dcbi 0,%0;sync;" : : "r" (__base));      \
 212         __base += HAL_DCACHE_LINE_SIZE;                         \
 213         __size -= HAL_DCACHE_LINE_SIZE;                         \
 214     }                                                           \
 215     CYG_MACRO_END
 216
 217 // Write dirty cache lines to memory for the given address range.
 218 #define HAL_DCACHE_STORE( _base_ , _size_ )                     \
 219     CYG_MACRO_START                                             \
 220     cyg_uint32 __base = (cyg_uint32) (_base_);                  \
 221     cyg_int32 __size = (cyg_int32) (_size_);                    \
 222     while (__size > 0) {                                        \
 223         asm volatile ("dcbst 0,%0;sync;" : : "r" (__base));     \
 224         __base += HAL_DCACHE_LINE_SIZE;                         \
 225         __size -= HAL_DCACHE_LINE_SIZE;                         \
 226     }                                                           \
 227     CYG_MACRO_END
 228
 229 // Preread the given range into the cache with the intention of reading
 230 // from it later.
 231 #define HAL_DCACHE_READ_HINT( _base_ , _size_ )                 \
 232     CYG_MACRO_START                                             \
 233     cyg_uint32 __base = (cyg_uint32) (_base_);                  \
 234     cyg_int32 __size = (cyg_int32) (_size_);                    \
 235     while (__size > 0) {                                        \
 236         asm volatile ("dcbt 0,%0;" : : "r" (__base));           \
 237         __base += HAL_DCACHE_LINE_SIZE;                         \
 238         __size -= HAL_DCACHE_LINE_SIZE;                         \
 239     }                                                           \
 240     CYG_MACRO_END
 241
 242 // Preread the given range into the cache with the intention of writing
 243 // to it later.
 244 #define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )                \
 245     CYG_MACRO_START                                             \
 246     cyg_uint32 __base = (cyg_uint32) (_base_);                  \
 247     cyg_int32 __size = (cyg_int32) (_size_);                    \
 248     while (__size > 0) {                                        \
 249         asm volatile ("dcbtst 0,%0;" : : "r" (__base));         \
 250         __base += HAL_DCACHE_LINE_SIZE;                         \
 251         __size -= HAL_DCACHE_LINE_SIZE;                         \
 252     }                                                           \
 253     CYG_MACRO_END
 254
 255 // Allocate and zero the cache lines associated with the given range.
 256 #define HAL_DCACHE_ZERO( _base_ , _size_ )                      \
 257     CYG_MACRO_START                                             \
 258     cyg_uint32 __base = (cyg_uint32) (_base_);                  \
 259     cyg_int32 __size = (cyg_int32) (_size_);                    \
 260     while (__size > 0) {                                        \
 261         asm volatile ("dcbz 0,%0;" : : "r" (__base));           \
 262         __base += HAL_DCACHE_LINE_SIZE;                         \
 263         __size -= HAL_DCACHE_LINE_SIZE;                         \
 264     }                                                           \
 265     CYG_MACRO_END
 266
 267 //-----------------------------------------------------------------------------
 268 // Global control of Instruction cache
 269
 270 // Enable the instruction cache
 271 #define HAL_ICACHE_ENABLE()                     \
 272     CYG_MACRO_START                             \
 273     cyg_int32 _scratch;                         \
 274     asm volatile ("isync;"                      \
 275                   "mfspr %0,%1;"                \
 276                   "or  %0,%0,%2;"               \
 277                   "mtspr %1,%0"                 \
 278                   : "=&r" (_scratch)            \
 279                   : "I" (CYGARC_REG_HID0),      \
 280                     "r" (_HID0_ICE)             \
 281         );                                      \
 282     CYG_MACRO_END
 283
 284 // Disable the instruction cache
 285 #define HAL_ICACHE_DISABLE()                    \
 286     CYG_MACRO_START                             \
 287     cyg_int32 _scratch;                         \
 288     asm volatile ("isync;"                      \
 289                   "mfspr %0,%1;"                \
 290                   "andc %0,%0,%2;"              \
 291                   "mtspr %1,%0"                 \
 292                   : "=&r" (_scratch)            \
 293                   : "I" (CYGARC_REG_HID0),      \
 294                     "r" (_HID0_ICE)             \
 295         );                                      \
 296     CYG_MACRO_END
 297
 298 // Invalidate the entire cache
 299 #define HAL_ICACHE_INVALIDATE_ALL()             \
 300     CYG_MACRO_START                             \
 301     cyg_int32 _scr1, _scr2;                     \
 302     asm volatile ("isync;"                      \
 303                   "mfspr %0,%2;"                \
 304                   "mr %1,%0;"                   \
 305                   "or %0,%0,%3;"                \
 306                   "mtspr %2,%0;"                \
 307                   "mtspr %2,%1"                 \
 308                   : "=&r" (_scr1),              \
 309                     "=&r" (_scr2)               \
 310                   : "I" (CYGARC_REG_HID0),      \
 311                     "r" (_HID0_ICFI)            \
 312         );                                      \
 313     CYG_MACRO_END
 314
 315 // Synchronize the contents of the cache with memory.
 316 #define HAL_ICACHE_SYNC()                       \
 317   HAL_ICACHE_INVALIDATE_ALL()
 318
 319 // Query the state of the instruction cache
 320 #define HAL_ICACHE_IS_ENABLED(_state_)          \
 321     CYG_MACRO_START                             \
 322     cyg_int32 _scratch;                         \
 323     asm volatile ("isync;"                      \
 324                   "mfspr %0,%1;"                \
 325                   "and %0,%0,%2;"               \
 326                   : "=&r" (_scratch)            \
 327                   : "I" (CYGARC_REG_HID0),      \
 328                     "r" (_HID0_ICE)             \
 329         );                                      \
 330     (_state_) = _scratch != 0;                  \
 331     CYG_MACRO_END
 332
 333 // Set the instruction cache refill burst size
 334 //#define HAL_ICACHE_BURST_SIZE(_size_)
 335
 336 // Load the contents of the given address range into the instruction cache
 337 // and then lock the cache so that it stays there.
 338 //#define HAL_ICACHE_LOCK(_base_, _size_)
 339
 340 // Undo a previous lock operation
 341 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
 342
 343 // Unlock entire cache
 344 //#define HAL_ICACHE_UNLOCK_ALL()
 345
 346 //-----------------------------------------------------------------------------
 347 // Instruction cache line control
 348
 349 // Invalidate cache lines in the given range without writing to memory.
 350 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
 351
 352 //-----------------------------------------------------------------------------
 353 #endif // ifndef CYGONCE_VAR_CACHE_H
 354 // End of var_cache.h