packages/hal/sh/arch/v2_0/include/hal_var_bank.h

   1 #ifndef CYGONCE_HAL_VAR_BANK_H
   2 #define CYGONCE_HAL_VAR_BANK_H
   3 //=============================================================================
   4 //
   5 //      hal_var_bank.h
   6 //
   7 //      Architecture abstractions for variants with banked registers
   8 //
   9 //=============================================================================
  10 //####ECOSGPLCOPYRIGHTBEGIN####
  11 // -------------------------------------------
  12 // This file is part of eCos, the Embedded Configurable Operating System.
  13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  14 // Copyright (C) 2003 Nick Garnett
  15 //
  16 // eCos is free software; you can redistribute it and/or modify it under
  17 // the terms of the GNU General Public License as published by the Free
  18 // Software Foundation; either version 2 or (at your option) any later version.
  19 //
  20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  22 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  23 // for more details.
  24 //
  25 // You should have received a copy of the GNU General Public License along
  26 // with eCos; if not, write to the Free Software Foundation, Inc.,
  27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  28 //
  29 // As a special exception, if other files instantiate templates or use macros
  30 // or inline functions from this file, or you compile this file and link it
  31 // with other works to produce a work based on this file, this file does not
  32 // by itself cause the resulting work to be covered by the GNU General Public
  33 // License. However the source code for this file must still be made available
  34 // in accordance with section (3) of the GNU General Public License.
  35 //
  36 // This exception does not invalidate any other reasons why a work based on
  37 // this file might be covered by the GNU General Public License.
  38 //
  39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  40 // at http://sources.redhat.com/ecos/ecos-license/
  41 // -------------------------------------------
  42 //####ECOSGPLCOPYRIGHTEND####
  43 //=============================================================================
  44 //#####DESCRIPTIONBEGIN####
  45 //
  46 // Author(s):   jskov
  47 // Contributors:jskov, nickg
  48 // Date:        2002-01-11
  49 // Purpose:     Architecture abstractions for variants with banked registers
  50 //
  51 //####DESCRIPTIONEND####
  52 //
  53 //=============================================================================
  54
  55 //-----------------------------------------------------------------------------
  56 // Processor saved states:
  57
  58 typedef struct
  59 {
  60     // These are common to all saved states
  61     cyg_uint32   r[16];                 // Data regs
  62     cyg_uint32   macl;                  // Multiply and accumulate - low
  63     cyg_uint32   mach;                  // Multiply and accumulate - high
  64
  65 #ifdef CYGHWR_HAL_SH_FPU
  66     cyg_uint32  fr[CYGHWR_HAL_SH_FPU_REGS]; // Floating point registers
  67     cyg_uint32  fpul;                   // Floating point comm reg
  68     cyg_uint32  fpscr;                  // Floating point status/control reg
  69 #endif
  70
  71     cyg_uint32   pr;                    // Procedure Reg
  72     cyg_uint32   sr;                    // Status Reg
  73     cyg_uint32   pc;                    // Program Counter
  74
  75     // This marks the limit of state saved during a context switch and
  76     // is used to calculate necessary stack allocation for context switches.
  77     // It would probably be better to have a union instead...
  78     cyg_uint32   context_size[0];
  79
  80     // These are only saved on interrupts
  81     cyg_uint32   vbr;                   // Vector Base Register
  82     cyg_uint32   gbr;                   // Global Base Register
  83
  84     // These are only saved on interrupts
  85     cyg_uint32   event;                 // EXCEVT or INTEVT
  86 } HAL_SavedRegisters;
  87
  88 //-----------------------------------------------------------------------------
  89 // Context Initialization
  90 // Initialize the context of a thread.
  91 // Arguments:
  92 // _sparg_ name of variable containing current sp, will be written with new sp
  93 // _thread_ thread object address, passed as argument to entry point
  94 // _entry_ entry point address.
  95 // _id_ bit pattern used in initializing registers, for debugging.
  96
  97 #ifdef CYGHWR_HAL_SH_FPU
  98 #include <cyg/hal/sh_regs.h>
  99 #define HAL_THREAD_INIT_CONTEXT_FPU( _regs_ )           \
 100 {                                                       \
 101     int _i_;                                            \
 102     (_regs_)->fpul = 0;                                 \
 103     (_regs_)->fpscr = CYG_FPSCR;                        \
 104     for( _i_ = 0; _i_ < CYGHWR_HAL_SH_FPU_REGS; _i_++ ) \
 105         (_regs_)->fr[_i_] = 0;                          \
 106 }
 107 #else
 108 #define HAL_THREAD_INIT_CONTEXT_FPU( _regs_ )
 109 #endif
 110
 111 #define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ )           \
 112     CYG_MACRO_START                                                           \
 113     register CYG_WORD _sp_ = (CYG_WORD)_sparg_;                               \
 114     register HAL_SavedRegisters *_regs_;                                      \
 115     int _i_;                                                                  \
 116     _sp_ = _sp_ & ~(CYGARC_ALIGNMENT-1);                                      \
 117     /* Note that _regs_ below should be aligned if HAL_SavedRegisters */      \
 118     /* stops being aligned to CYGARC_ALIGNMENT                        */      \
 119     _regs_ = (HAL_SavedRegisters *)((_sp_) - sizeof(HAL_SavedRegisters));     \
 120     for( _i_ = 0; _i_ < 16; _i_++ ) (_regs_)->r[_i_] = (_id_)|_i_;            \
 121     (_regs_)->r[15] = (CYG_WORD)(_regs_);      /* SP = top of stack      */   \
 122     (_regs_)->r[04] = (CYG_WORD)(_thread_);    /* R4 = arg1 = thread ptr */   \
 123     (_regs_)->mach = 0;                        /* MACH = 0               */   \
 124     (_regs_)->macl = 0;                        /* MACL = 0               */   \
 125     (_regs_)->pr = (CYG_WORD)(_entry_);        /* PR = entry point       */   \
 126     (_regs_)->sr = 0x70000000;                 /* SR = enable interrupts */   \
 127     (_regs_)->pc = (CYG_WORD)(_entry_);        /* set PC for thread dbg  */   \
 128     HAL_THREAD_INIT_CONTEXT_FPU( _regs_ );     /* Init FPU state         */   \
 129     _sparg_ = (CYG_ADDRESS)_regs_;                                            \
 130     CYG_MACRO_END
 131
 132 //-----------------------------------------------------------------------------
 133 // Thread register state manipulation for GDB support.
 134
 135 // Translate a stack pointer as saved by the thread context macros above into
 136 // a pointer to a HAL_SavedRegisters structure.
 137 #define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ )  \
 138         (_regs_) = (HAL_SavedRegisters *)(_sp_)
 139
 140 #ifdef CYGHWR_HAL_SH_FPU
 141 #define HAL_GET_GDB_REGISTERS_FPU( _regval_, _regs_ )   \
 142 {                                                       \
 143     _regval_[23] = (_regs_)->fpul;                      \
 144     _regval_[24] = (_regs_)->fpscr;                     \
 145                                                         \
 146     for( _i_ = 0; _i_ < 16; _i_++ )                     \
 147         _regval_[25+_i_] = (_regs_)->fr[_i_];           \
 148 }
 149
 150 #define HAL_SET_GDB_REGISTERS_FPU( _regs_, _regval_ )   \
 151 {                                                       \
 152     (_regs_)->fpul = _regval_[23];                      \
 153     (_regs_)->fpscr = _regval_[24];                     \
 154                                                         \
 155     for( _i_ = 0; _i_ < 16; _i_++ )                     \
 156         (_regs_)->fr[_i_] = _regval_[25+_i_];           \
 157 }
 158 #else
 159 #define HAL_GET_GDB_REGISTERS_FPU( _regval_, _regs_ )
 160 #define HAL_SET_GDB_REGISTERS_FPU( _regs_, _regval_ )
 161 #endif
 162
 163 // Copy a set of registers from a HAL_SavedRegisters structure into a
 164 // GDB ordered array.
 165 #define HAL_GET_GDB_REGISTERS( _aregval_, _regs_ )              \
 166     CYG_MACRO_START                                             \
 167     CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_);       \
 168     int _i_;                                                    \
 169                                                                 \
 170     for( _i_ = 0; _i_ < 8; _i_++ )                              \
 171     {                                                           \
 172         _regval_[_i_] = (_regs_)->r[_i_];                       \
 173         _regval_[43+_i_] = (_regs_)->r[_i_];                    \
 174         _regval_[51+_i_] = 0;                                   \
 175     }                                                           \
 176                                                                 \
 177     for( /* _i_ = 8 */ ; _i_ < 16; _i_++ )                      \
 178         _regval_[_i_] = (_regs_)->r[_i_];                       \
 179                                                                 \
 180     _regval_[16] = (_regs_)->pc;                                \
 181     _regval_[17] = (_regs_)->pr;                                \
 182     _regval_[18] = (_regs_)->gbr;                               \
 183     _regval_[19] = (_regs_)->vbr;                               \
 184     _regval_[20] = (_regs_)->mach;                              \
 185     _regval_[21] = (_regs_)->macl;                              \
 186     _regval_[22] = (_regs_)->sr;                                \
 187                                                                 \
 188     HAL_GET_GDB_REGISTERS_FPU( _regval_, _regs_ );              \
 189                                                                 \
 190     CYG_MACRO_END
 191
 192 // Copy a GDB ordered array into a HAL_SavedRegisters structure.
 193 #define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ )             \
 194     CYG_MACRO_START                                             \
 195     CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_);       \
 196     int _i_;                                                    \
 197                                                                 \
 198     for( _i_ = 0; _i_ < 16; _i_++ )                             \
 199         (_regs_)->r[_i_] = _regval_[_i_];                       \
 200                                                                 \
 201     (_regs_)->pc = _regval_[16];                                \
 202     (_regs_)->pr = _regval_[17];                                \
 203     (_regs_)->gbr  = _regval_[18];                              \
 204     (_regs_)->vbr  = _regval_[19];                              \
 205     (_regs_)->mach = _regval_[20];                              \
 206     (_regs_)->macl = _regval_[21];                              \
 207     (_regs_)->sr = _regval_[22];                                \
 208                                                                 \
 209     HAL_SET_GDB_REGISTERS_FPU( _regs_, _regval_ );              \
 210                                                                 \
 211     CYG_MACRO_END
 212
 213 //--------------------------------------------------------------------------
 214 // CPU address space translation macros
 215 #define CYGARC_BUS_ADDRESS(x)       ((CYG_ADDRWORD)(x) & 0x1fffffff)
 216 #define CYGARC_CACHED_ADDRESS(x)    (CYGARC_BUS_ADDRESS(x)|0x80000000)
 217 #define CYGARC_UNCACHED_ADDRESS(x)  (CYGARC_BUS_ADDRESS(x)|0xa0000000)
 218
 219 //-----------------------------------------------------------------------------
 220 #endif // CYGONCE_HAL_VAR_BANK_H
 221 // End of hal_var_bank.h