packages/hal/sh/hs7729pci/v2_0/include/plf_intr.h

   1 #ifndef CYGONCE_HAL_PLF_INTR_H
   2 #define CYGONCE_HAL_PLF_INTR_H
   3
   4 //==========================================================================
   5 //
   6 //      plf_intr.h
   7 //
   8 //      Platform specific Interrupt and clock support
   9 //
  10 //==========================================================================
  11 //####ECOSGPLCOPYRIGHTBEGIN####
  12 // -------------------------------------------
  13 // This file is part of eCos, the Embedded Configurable Operating System.
  14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  15 //
  16 // eCos is free software; you can redistribute it and/or modify it under
  17 // the terms of the GNU General Public License as published by the Free
  18 // Software Foundation; either version 2 or (at your option) any later version.
  19 //
  20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  22 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  23 // for more details.
  24 //
  25 // You should have received a copy of the GNU General Public License along
  26 // with eCos; if not, write to the Free Software Foundation, Inc.,
  27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  28 //
  29 // As a special exception, if other files instantiate templates or use macros
  30 // or inline functions from this file, or you compile this file and link it
  31 // with other works to produce a work based on this file, this file does not
  32 // by itself cause the resulting work to be covered by the GNU General Public
  33 // License. However the source code for this file must still be made available
  34 // in accordance with section (3) of the GNU General Public License.
  35 //
  36 // This exception does not invalidate any other reasons why a work based on
  37 // this file might be covered by the GNU General Public License.
  38 //
  39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  40 // at http://sources.redhat.com/ecos/ecos-license/
  41 // -------------------------------------------
  42 //####ECOSGPLCOPYRIGHTEND####
  43 //==========================================================================
  44 //#####DESCRIPTIONBEGIN####
  45 //
  46 // Author(s):    jskov
  47 // Contributors: jskov
  48 // Date:         2001-05-25
  49 // Purpose:      Define Interrupt support
  50 // Description:  The macros defined here provide the HAL APIs for handling
  51 //               interrupts and the clock for the HS7729PCI board.
  52 // Usage:
  53 //               #include <cyg/hal/plf_intr.h>
  54 //               ...
  55 //
  56 //
  57 //####DESCRIPTIONEND####
  58 //
  59 //==========================================================================
  60
  61 #include <pkgconf/hal.h>
  62
  63 //----------------------------------------------------------------------------
  64 // External interrupts
  65 #define CYGNUM_HAL_INTERRUPT_EXTERNALS_BASE CYGNUM_HAL_INTERRUPT_LVL0
  66 #define CYGNUM_HAL_INTERRUPT_PCI            CYGNUM_HAL_INTERRUPT_LVL0
  67 #define CYGNUM_HAL_INTERRUPT_UIO_IRQ4       CYGNUM_HAL_INTERRUPT_LVL1
  68 #define CYGNUM_HAL_INTERRUPT_SLOT_IRQ1      CYGNUM_HAL_INTERRUPT_LVL2
  69 #define CYGNUM_HAL_INTERRUPT_UIO_IRQ12      CYGNUM_HAL_INTERRUPT_LVL3
  70 #define CYGNUM_HAL_INTERRUPT_PCMCIA_IRQ0    CYGNUM_HAL_INTERRUPT_LVL4
  71 #define CYGNUM_HAL_INTERRUPT_UIO_IRQ5       CYGNUM_HAL_INTERRUPT_LVL5
  72 #define CYGNUM_HAL_INTERRUPT_USB1           CYGNUM_HAL_INTERRUPT_LVL6
  73 #define CYGNUM_HAL_INTERRUPT_UIO_IRQ8       CYGNUM_HAL_INTERRUPT_LVL7
  74 #define CYGNUM_HAL_INTERRUPT_UIO_IRQ1       CYGNUM_HAL_INTERRUPT_LVL8
  75 #define CYGNUM_HAL_INTERRUPT_RESERVED1      CYGNUM_HAL_INTERRUPT_LVL9
  76 #define CYGNUM_HAL_INTERRUPT_PCMCIA_IRQ2    CYGNUM_HAL_INTERRUPT_LVL10
  77 #define CYGNUM_HAL_INTERRUPT_USB2           CYGNUM_HAL_INTERRUPT_LVL11
  78 #define CYGNUM_HAL_INTERRUPT_RESERVED2      CYGNUM_HAL_INTERRUPT_LVL12
  79 #define CYGNUM_HAL_INTERRUPT_SLOT_IRQ5      CYGNUM_HAL_INTERRUPT_LVL13
  80 #define CYGNUM_HAL_INTERRUPT_UIO_IRQ3       CYGNUM_HAL_INTERRUPT_LVL14
  81
  82 // Decoded interrupts - these follow the INTC v3 vectors defined in
  83 // var_intr.h
  84 #define CYGNUM_HAL_INTERRUPT_PCIA           66
  85 #define CYGNUM_HAL_INTERRUPT_PCIB           67
  86 #define CYGNUM_HAL_INTERRUPT_PCIC           68
  87 #define CYGNUM_HAL_INTERRUPT_PCID           69
  88
  89 #define CYGNUM_HAL_ISR_PLF_MAX              CYGNUM_HAL_INTERRUPT_PCID
  90
  91 //----------------------------------------------------------------------------
  92 // Interrupt configuration extention macros
  93 #define CYGPRI_HAL_INTERRUPT_UPDATE_LEVEL_PLF(vec, level)                               \
  94  case CYGNUM_HAL_INTERRUPT_NMI:                                                         \
  95      /* fall through */                                                                 \
  96  case CYGNUM_HAL_INTERRUPT_LVL0 ... CYGNUM_HAL_INTERRUPT_LVL14:                         \
  97      /* Cannot change levels */                                                         \
  98      break;                                                                             \
  99  case CYGNUM_HAL_INTERRUPT_PCIA ... CYGNUM_HAL_INTERRUPT_PCID:                          \
 100   {                                                                                     \
 101       cyg_uint32 msk;                                                                   \
 102       HAL_READ_UINT32(CYGARC_REG_SD0001_INT_ENABLE, msk);                               \
 103       msk &= ~(CYGARC_REG_SD0001_INT_INTA << ((vec) - CYGNUM_HAL_INTERRUPT_PCIA));      \
 104       msk |= CYGARC_REG_SD0001_INT_EN;                                                  \
 105       if ((level))                                                                      \
 106           msk |= CYGARC_REG_SD0001_INT_INTA << ((vec) - CYGNUM_HAL_INTERRUPT_PCIA);     \
 107       HAL_WRITE_UINT32(CYGARC_REG_SD0001_INT_ENABLE, msk);                              \
 108       break;                                                                            \
 109   }
 110
 111 #define CYGPRI_HAL_INTERRUPT_ACKNOWLEDGE_PLF(vec)                                       \
 112   CYG_MACRO_START                                                                       \
 113   if (vec >= CYGNUM_HAL_INTERRUPT_PCIA && vec <= CYGNUM_HAL_INTERRUPT_PCID) {           \
 114       cyg_uint32 sts = CYGARC_REG_SD0001_INT_INTA << (vec - CYGNUM_HAL_INTERRUPT_PCIA); \
 115       HAL_WRITE_UINT32(CYGARC_REG_SD0001_INT_STS1, sts);                                \
 116   }                                                                                     \
 117   CYG_MACRO_END
 118
 119 //----------------------------------------------------------------------------
 120 // Reset.
 121 // Block interrupts and cause an exception. This forces a reset.
 122 #define HAL_PLATFORM_RESET() \
 123     asm volatile ("ldc %0,sr;trapa #0x00;" : : "r" (CYGARC_REG_SR_BL))
 124
 125 #define HAL_PLATFORM_RESET_ENTRY 0x80000000
 126
 127 //--------------------------------------------------------------------------
 128 #endif // ifndef CYGONCE_HAL_PLF_INTR_H
 129 // End of plf_intr.h