1 //=============================================================================
5 // Init code for M1543C super IO controller
7 //=============================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
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18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
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24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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27 // or inline functions from this file, or you compile this file and link it
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30 // License. However the source code for this file must still be made available
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38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //=============================================================================
41 //#####DESCRIPTIONBEGIN####
46 // Description: Init code for M1543C super IO controller
48 //####DESCRIPTIONEND####
50 //=============================================================================
52 #include <pkgconf/hal.h>
53 #include CYGBLD_HAL_PLATFORM_H
55 #include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros
56 #include <cyg/hal/hal_io.h> // IO macros
57 #include <cyg/hal/hal_intr.h> // interrupt vectors
58 #include <cyg/io/pci.h> // PCI macro
61 //-----------------------------------------------------------------------------
63 #define SIO_READ_UINT8(_a_, _d_) \
65 HAL_PCI_IO_READ_UINT8((_a_), (_d_)); \
68 #define SIO_WRITE_UINT8(_a_, _d_) \
70 HAL_PCI_IO_WRITE_UINT8((_a_), (_d_)); \
73 //-----------------------------------------------------------------------------
75 #define SIO_CONFIG 0x000003f0
76 #define SIO_CONFIG_DATA 0x000003f1
78 #define SIO_CONFIG_DEV 0x07
79 #define SIO_CONFIG_POWER 0x22
80 #define SIO_CONFIG_ACTIVATE 0x30
81 #define SIO_CONFIG_ENTER1 0x51
82 #define SIO_CONFIG_ENTER2 0x23
83 #define SIO_CONFIG_BASE_HIGH 0x60
84 #define SIO_CONFIG_BASE_LOW 0x61
85 #define SIO_CONFIG_IRQ 0x70
86 #define SIO_CONFIG_EXIT 0xbb
87 #define SIO_CONFIG_MODE 0xf0
89 #define SIO_CONFIG_DEV_COM1 0x04
90 #define SIO_CONFIG_DEV_COM2 0x05
91 #define SIO_CONFIG_DEV_RTC 0x06
93 #define SIO_CONFIG_MODE_HIGH 0x02
95 #define SIO_CONFIG_ACTIVATE_ENABLE 0x01
97 #define SIO_CONFIG_POWER_COM1 0x10
98 #define SIO_CONFIG_POWER_COM2 0x20
102 cyg_hal_init_superIO(void)
105 // Enable PCI to ISA bridge (magic from Hitachi monitor).
106 cyg_pci_write_config_uint32(CYG_PCI_DEV_MAKE_ID(0, 2<<3), 0x40, 0x8020c77f);
107 cyg_pci_write_config_uint32(CYG_PCI_DEV_MAKE_ID(0, 2<<3), 0x44, 0x00001b9d);
108 cyg_pci_write_config_uint32(CYG_PCI_DEV_MAKE_ID(0, 2<<3), 0x48, 0x00009315);
109 cyg_pci_write_config_uint32(CYG_PCI_DEV_MAKE_ID(0, 2<<3), 0x4c, 0x0000000f);
112 // Enter SuperIO config mode
113 SIO_WRITE_UINT8(SIO_CONFIG, SIO_CONFIG_ENTER1);
114 SIO_WRITE_UINT8(SIO_CONFIG, SIO_CONFIG_ENTER2);
116 // Configure and enable COM1
117 SIO_WRITE_UINT8(SIO_CONFIG, SIO_CONFIG_DEV);
118 SIO_WRITE_UINT8(SIO_CONFIG_DATA, SIO_CONFIG_DEV_COM1);
120 SIO_WRITE_UINT8(SIO_CONFIG, SIO_CONFIG_BASE_HIGH);
121 SIO_WRITE_UINT8(SIO_CONFIG_DATA, 0x03);
122 SIO_WRITE_UINT8(SIO_CONFIG, SIO_CONFIG_BASE_LOW);
123 SIO_WRITE_UINT8(SIO_CONFIG_DATA, 0xf8);
125 // Select IRQ 4 (see chap 8. Interrupt Controller)
126 SIO_WRITE_UINT8(SIO_CONFIG, SIO_CONFIG_IRQ);
127 SIO_WRITE_UINT8(SIO_CONFIG_DATA, 4);
129 SIO_WRITE_UINT8(SIO_CONFIG, SIO_CONFIG_ACTIVATE);
130 SIO_WRITE_UINT8(SIO_CONFIG_DATA, SIO_CONFIG_ACTIVATE_ENABLE);
132 SIO_WRITE_UINT8(SIO_CONFIG, SIO_CONFIG_EXIT);
135 //-----------------------------------------------------------------------------
136 // end of smsc37c93x.c