1 //=============================================================================
5 // CAC (cache) Module register definitions
7 //=============================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
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38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //=============================================================================
41 //#####DESCRIPTIONBEGIN####
47 //####DESCRIPTIONEND####
49 //=============================================================================
51 // Besides the below, cache sizes are defined in the CPU variant module
52 // headers (mod_76xx.h).
54 //--------------------------------------------------------------------------
56 #define CYGARC_REG_CCR 0xfffffe92
58 #define CYGARC_REG_CCR_W3 0xc0 // way affected
59 #define CYGARC_REG_CCR_W2 0x80
60 #define CYGARC_REG_CCR_W1 0x40
61 #define CYGARC_REG_CCR_W0 0x00
62 #define CYGARC_REG_CCR_WB 0x20 // write-back
63 #define CYGARC_REG_CCR_CP 0x10 // cache purge
64 #define CYGARC_REG_CCR_TW 0x08 // two-way mode
65 #define CYGARC_REG_CCR_OD 0x04 // operand replacement disable
66 #define CYGARC_REG_CCR_ID 0x02 // instruction replacement disable
67 #define CYGARC_REG_CCR_CE 0x01 // cache enable
70 //--------------------------------------------------------------------------
71 // Address array access
72 // Address part (base/top/step specified in mod file)
73 #define CYGARC_REG_CACHE_ADDRESS_ADDRESS 0x00000008 // compare address
76 #define CYGARC_REG_CACHE_ADDRESS_TAG_Mask 0x1ffffc00
77 #define CYGARC_REG_CACHE_ADDRESS_U 0x00000002 // updated (contains dirty data)
78 #define CYGARC_REG_CACHE_ADDRESS_V 0x00000001 // valid