packages/hal/sh/sh2/v2_0/include/var_intr.h

   1 #ifndef CYGONCE_VAR_INTR_H
   2 #define CYGONCE_VAR_INTR_H
   3
   4 //==========================================================================
   5 //
   6 //      var_intr.h
   7 //
   8 //      HAL variant interrupt and clock support
   9 //
  10 //==========================================================================
  11 //####ECOSGPLCOPYRIGHTBEGIN####
  12 // -------------------------------------------
  13 // This file is part of eCos, the Embedded Configurable Operating System.
  14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  15 //
  16 // eCos is free software; you can redistribute it and/or modify it under
  17 // the terms of the GNU General Public License as published by the Free
  18 // Software Foundation; either version 2 or (at your option) any later version.
  19 //
  20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  22 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  23 // for more details.
  24 //
  25 // You should have received a copy of the GNU General Public License along
  26 // with eCos; if not, write to the Free Software Foundation, Inc.,
  27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  28 //
  29 // As a special exception, if other files instantiate templates or use macros
  30 // or inline functions from this file, or you compile this file and link it
  31 // with other works to produce a work based on this file, this file does not
  32 // by itself cause the resulting work to be covered by the GNU General Public
  33 // License. However the source code for this file must still be made available
  34 // in accordance with section (3) of the GNU General Public License.
  35 //
  36 // This exception does not invalidate any other reasons why a work based on
  37 // this file might be covered by the GNU General Public License.
  38 //
  39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  40 // at http://sources.redhat.com/ecos/ecos-license/
  41 // -------------------------------------------
  42 //####ECOSGPLCOPYRIGHTEND####
  43 //==========================================================================
  44 //#####DESCRIPTIONBEGIN####
  45 //
  46 // Author(s):    jskov
  47 // Contributors: jskov,
  48 // Date:         1999-04-24
  49 // Purpose:      Define Interrupt support
  50 // Description:  The macros defined here provide the HAL APIs for handling
  51 //               interrupts and the clock.
  52 //
  53 // Usage:
  54 //               #include <cyg/hal/hal_intr.h>
  55 //               ...
  56 //
  57 //
  58 //####DESCRIPTIONEND####
  59 //
  60 //==========================================================================
  61
  62 #include <pkgconf/hal.h>
  63
  64 #include CYGBLD_HAL_CPU_MODULES_H       // INTC module selection
  65
  66 //--------------------------------------------------------------------------
  67 // Optional platform overrides and fallbacks
  68 #include <cyg/hal/plf_intr.h>
  69
  70 #ifndef CYGPRI_HAL_INTERRUPT_ACKNOWLEDGE_PLF
  71 # define CYGPRI_HAL_INTERRUPT_ACKNOWLEDGE_PLF(vec)
  72 #endif
  73
  74 #ifndef CYGPRI_HAL_INTERRUPT_CONFIGURE_PLF
  75 # define CYGPRI_HAL_INTERRUPT_CONFIGURE_PLF(vec, level, up)
  76 #endif
  77
  78 //----------------------------------------------------------------------------
  79 // Additional vectors provided by INTC V1
  80
  81 #if (CYGARC_SH_MOD_INTC == 1)
  82
  83 #ifndef CYGPRI_HAL_INTERRUPT_UPDATE_LEVEL_PLF
  84 # define CYGPRI_HAL_INTERRUPT_UPDATE_LEVEL_PLF(vec, level)                  \
  85     case CYGNUM_HAL_INTERRUPT_NMI:                                          \
  86         /* fall through */                                                  \
  87     case CYGNUM_HAL_INTERRUPT_LVL4 ... CYGNUM_HAL_INTERRUPT_LVL_MAX:        \
  88         /* Cannot change levels */                                          \
  89         break;
  90 #endif
  91
  92 #define CYGNUM_HAL_INTERRUPT_LVL8           9
  93 #define CYGNUM_HAL_INTERRUPT_LVL9          10
  94 #define CYGNUM_HAL_INTERRUPT_LVL10         11
  95 #define CYGNUM_HAL_INTERRUPT_LVL11         12
  96 #define CYGNUM_HAL_INTERRUPT_LVL12         13
  97 #define CYGNUM_HAL_INTERRUPT_LVL13         14
  98 #define CYGNUM_HAL_INTERRUPT_LVL14         15
  99 #define CYGNUM_HAL_INTERRUPT_DMAC0_TE      16
 100 #define CYGNUM_HAL_INTERRUPT_DMAC1_TE      17
 101 #define CYGNUM_HAL_INTERRUPT_WDT_ITI       18
 102 #define CYGNUM_HAL_INTERRUPT_REF_CMI       19
 103 #define CYGNUM_HAL_INTERRUPT_EDMAC_EINT    20
 104 #define CYGNUM_HAL_INTERRUPT_FRT_ICI       21
 105 #define CYGNUM_HAL_INTERRUPT_FRT_OCI       22
 106 #define CYGNUM_HAL_INTERRUPT_FRT_OVI       23
 107 #define CYGNUM_HAL_INTERRUPT_TPU0_TGI0A    24
 108 #define CYGNUM_HAL_INTERRUPT_TPU0_TGI0B    25
 109 #define CYGNUM_HAL_INTERRUPT_TPU0_TGI0C    26
 110 #define CYGNUM_HAL_INTERRUPT_TPU0_TGI0D    27
 111 #define CYGNUM_HAL_INTERRUPT_TPU0_TGI0V    28
 112 #define CYGNUM_HAL_INTERRUPT_TPU1_TGI1A    29
 113 #define CYGNUM_HAL_INTERRUPT_TPU1_TGI1B    30
 114 #define CYGNUM_HAL_INTERRUPT_TPU1_TGI1V    31
 115 #define CYGNUM_HAL_INTERRUPT_TPU1_TGI1U    32
 116 #define CYGNUM_HAL_INTERRUPT_TPU2_TGI2A    33
 117 #define CYGNUM_HAL_INTERRUPT_TPU2_TGI2B    34
 118 #define CYGNUM_HAL_INTERRUPT_TPU2_TGI2V    35
 119 #define CYGNUM_HAL_INTERRUPT_TPU2_TGI2U    36
 120 #define CYGNUM_HAL_INTERRUPT_SCIF1_ERI1    37
 121 #define CYGNUM_HAL_INTERRUPT_SCIF1_RXI1    38
 122 #define CYGNUM_HAL_INTERRUPT_SCIF1_BRI1    39
 123 #define CYGNUM_HAL_INTERRUPT_SCIF1_TXI1    40
 124 #define CYGNUM_HAL_INTERRUPT_SCIF2_ERI2    41
 125 #define CYGNUM_HAL_INTERRUPT_SCIF2_RXI2    42
 126 #define CYGNUM_HAL_INTERRUPT_SCIF2_BRI2    43
 127 #define CYGNUM_HAL_INTERRUPT_SCIF2_TXI2    44
 128 #define CYGNUM_HAL_INTERRUPT_SIO0_RERI0    45
 129 #define CYGNUM_HAL_INTERRUPT_SIO0_TERI0    46
 130 #define CYGNUM_HAL_INTERRUPT_SIO0_RDFI0    47
 131 #define CYGNUM_HAL_INTERRUPT_SIO0_TDEI0    48
 132 #define CYGNUM_HAL_INTERRUPT_SIO1_RERI1    49
 133 #define CYGNUM_HAL_INTERRUPT_SIO1_TERI1    50
 134 #define CYGNUM_HAL_INTERRUPT_SIO1_RDFI1    51
 135 #define CYGNUM_HAL_INTERRUPT_SIO1_TDEI1    52
 136 #define CYGNUM_HAL_INTERRUPT_SIO2_RERI2    53
 137 #define CYGNUM_HAL_INTERRUPT_SIO2_TERI2    54
 138 #define CYGNUM_HAL_INTERRUPT_SIO2_RDFI2    55
 139 #define CYGNUM_HAL_INTERRUPT_SIO2_TDEI2    56
 140
 141 #define CYGNUM_HAL_INTERRUPT_LVL_MAX       CYGNUM_HAL_INTERRUPT_LVL14
 142
 143 #undef  CYGNUM_HAL_ISR_MAX
 144 #ifdef CYGNUM_HAL_ISR_PLF_MAX
 145 # define CYGNUM_HAL_ISR_MAX                CYGNUM_HAL_ISR_PLF_MAX
 146 #else
 147 # define CYGNUM_HAL_ISR_MAX                CYGNUM_HAL_INTERRUPT_SIO2_TDEI2
 148 #endif
 149
 150 // The vector used by the Real time clock
 151 #ifndef CYGNUM_HAL_INTERRUPT_RTC
 152 # define CYGNUM_HAL_INTERRUPT_RTC             CYGNUM_HAL_INTERRUPT_FRT_OCI
 153 #endif
 154
 155 #elif (CYGARC_SH_MOD_INTC == 2)
 156
 157 #ifndef CYGPRI_HAL_INTERRUPT_UPDATE_LEVEL_PLF
 158 # define CYGPRI_HAL_INTERRUPT_UPDATE_LEVEL_PLF(vec, level)                  \
 159     case CYGNUM_HAL_INTERRUPT_NMI:                                          \
 160         /* Cannot change levels */                                          \
 161         break;
 162 #endif
 163
 164 #define CYGNUM_HAL_INTERRUPT_DMAC0_DEI0         9
 165 #define CYGNUM_HAL_INTERRUPT_DMAC1_DEI1        10
 166 #define CYGNUM_HAL_INTERRUPT_DMAC2_DEI2        11
 167 #define CYGNUM_HAL_INTERRUPT_DMAC3_DEI3        12
 168 #define CYGNUM_HAL_INTERRUPT_MTU0_TGI0A        13
 169 #define CYGNUM_HAL_INTERRUPT_MTU0_TGI0B        14
 170 #define CYGNUM_HAL_INTERRUPT_MTU0_TGI0C        15
 171 #define CYGNUM_HAL_INTERRUPT_MTU0_TGI0D        16
 172 #define CYGNUM_HAL_INTERRUPT_MTU0_TGI0V        17
 173 #define CYGNUM_HAL_INTERRUPT_MTU1_TGI1A        18
 174 #define CYGNUM_HAL_INTERRUPT_MTU1_TGI1B        19
 175 #define CYGNUM_HAL_INTERRUPT_MTU1_TGI1V        20
 176 #define CYGNUM_HAL_INTERRUPT_MTU1_TGI1U        21
 177 #define CYGNUM_HAL_INTERRUPT_MTU2_TGI2A        22
 178 #define CYGNUM_HAL_INTERRUPT_MTU2_TGI2B        23
 179 #define CYGNUM_HAL_INTERRUPT_MTU2_TGI2V        24
 180 #define CYGNUM_HAL_INTERRUPT_MTU2_TGI2U        25
 181 #define CYGNUM_HAL_INTERRUPT_MTU3_TGI3A        26
 182 #define CYGNUM_HAL_INTERRUPT_MTU3_TGI3B        27
 183 #define CYGNUM_HAL_INTERRUPT_MTU3_TGI3C        28
 184 #define CYGNUM_HAL_INTERRUPT_MTU3_TGI3D        29
 185 #define CYGNUM_HAL_INTERRUPT_MTU3_TGI3V        30
 186 #define CYGNUM_HAL_INTERRUPT_MTU4_TGI4A        31
 187 #define CYGNUM_HAL_INTERRUPT_MTU4_TGI4B        32
 188 #define CYGNUM_HAL_INTERRUPT_MTU4_TGI4C        33
 189 #define CYGNUM_HAL_INTERRUPT_MTU4_TGI4D        34
 190 #define CYGNUM_HAL_INTERRUPT_MTU4_TGI4V        35
 191 #define CYGNUM_HAL_INTERRUPT_SCI0_ERI0         36
 192 #define CYGNUM_HAL_INTERRUPT_SCI0_RXI0         37
 193 #define CYGNUM_HAL_INTERRUPT_SCI0_TXI0         38
 194 #define CYGNUM_HAL_INTERRUPT_SCI0_TEI0         39
 195 #define CYGNUM_HAL_INTERRUPT_SCI1_ERI1         40
 196 #define CYGNUM_HAL_INTERRUPT_SCI1_RXI1         41
 197 #define CYGNUM_HAL_INTERRUPT_SCI1_TXI1         42
 198 #define CYGNUM_HAL_INTERRUPT_SCI1_TEI1         43
 199 #define CYGNUM_HAL_INTERRUPT_AD_ADI0           44
 200 #define CYGNUM_HAL_INTERRUPT_AD_ADI1           45
 201 #define CYGNUM_HAL_INTERRUPT_DTC_SWDTCE        46
 202 #define CYGNUM_HAL_INTERRUPT_CMT0_CMI0         47
 203 #define CYGNUM_HAL_INTERRUPT_CMT1_CMI1         48
 204 #define CYGNUM_HAL_INTERRUPT_WDT_ITI           49
 205 #define CYGNUM_HAL_INTERRUPT_BSC_CMI           50
 206 #define CYGNUM_HAL_INTERRUPT_IO_OEI            51
 207 #define CYGNUM_HAL_INTERRUPT_VAR_RESERVED      52       // just to catch bad assignments
 208
 209 #undef  CYGNUM_HAL_ISR_MAX
 210 #ifdef CYGNUM_HAL_ISR_PLF_MAX
 211 # define CYGNUM_HAL_ISR_MAX                  CYGNUM_HAL_ISR_PLF_MAX
 212 #else
 213 # define CYGNUM_HAL_ISR_MAX                  CYGNUM_HAL_INTERRUPT_VAR_RESERVED
 214 #endif
 215
 216 //                           eCos vector this entry decodes to , actual HW interrupt vector
 217 #define CYGHWR_HAL_SH_SH2_CUSTOM_INTERRUPT_LAYOUT                         \
 218         exception_vector_int CYGNUM_HAL_INTERRUPT_LVL0         ,  1 ;     \
 219         exception_vector_int CYGNUM_HAL_INTERRUPT_LVL1         ,  2 ;     \
 220         exception_vector_int CYGNUM_HAL_INTERRUPT_LVL2         ,  3 ;     \
 221         exception_vector_int CYGNUM_HAL_INTERRUPT_LVL3         ,  4 ;     \
 222         exception_vector_int CYGNUM_HAL_INTERRUPT_LVL4         ,  5 ;     \
 223         exception_vector_int CYGNUM_HAL_INTERRUPT_LVL5         ,  6 ;     \
 224         exception_vector_int CYGNUM_HAL_INTERRUPT_LVL6         ,  7 ;     \
 225         exception_vector_int CYGNUM_HAL_INTERRUPT_LVL7         ,  8 ;     \
 226                                                                           \
 227         exception_vector_int CYGNUM_HAL_INTERRUPT_DMAC0_DEI0   ,  9  ;    \
 228         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 10  ;    \
 229         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 11  ;    \
 230         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 12  ;    \
 231         exception_vector_int CYGNUM_HAL_INTERRUPT_DMAC1_DEI1   , 13  ;    \
 232         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 14  ;    \
 233         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 15  ;    \
 234         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 16  ;    \
 235         exception_vector_int CYGNUM_HAL_INTERRUPT_DMAC2_DEI2   , 17  ;    \
 236         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 18  ;    \
 237         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 19  ;    \
 238         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 20  ;    \
 239         exception_vector_int CYGNUM_HAL_INTERRUPT_DMAC3_DEI3   , 21  ;    \
 240         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 22  ;    \
 241         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 23  ;    \
 242         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 24  ;    \
 243         exception_vector_int CYGNUM_HAL_INTERRUPT_MTU0_TGI0A   , 25  ;    \
 244         exception_vector_int CYGNUM_HAL_INTERRUPT_MTU0_TGI0B   , 26  ;    \
 245         exception_vector_int CYGNUM_HAL_INTERRUPT_MTU0_TGI0C   , 27  ;    \
 246         exception_vector_int CYGNUM_HAL_INTERRUPT_MTU0_TGI0D   , 28  ;    \
 247         exception_vector_int CYGNUM_HAL_INTERRUPT_MTU0_TGI0V   , 29  ;    \
 248         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 30  ;    \
 249         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 31  ;    \
 250         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 32  ;    \
 251         exception_vector_int CYGNUM_HAL_INTERRUPT_MTU1_TGI1A   , 33  ;    \
 252         exception_vector_int CYGNUM_HAL_INTERRUPT_MTU1_TGI1B   , 34  ;    \
 253         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 35  ;    \
 254         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 36  ;    \
 255         exception_vector_int CYGNUM_HAL_INTERRUPT_MTU1_TGI1V   , 37  ;    \
 256         exception_vector_int CYGNUM_HAL_INTERRUPT_MTU1_TGI1U   , 38  ;    \
 257         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 39  ;    \
 258         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 40  ;    \
 259         exception_vector_int CYGNUM_HAL_INTERRUPT_MTU2_TGI2A   , 41  ;    \
 260         exception_vector_int CYGNUM_HAL_INTERRUPT_MTU2_TGI2B   , 42  ;    \
 261         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 43  ;    \
 262         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 44  ;    \
 263         exception_vector_int CYGNUM_HAL_INTERRUPT_MTU2_TGI2V   , 45  ;    \
 264         exception_vector_int CYGNUM_HAL_INTERRUPT_MTU2_TGI2U   , 46  ;    \
 265         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 47  ;    \
 266         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 48  ;    \
 267         exception_vector_int CYGNUM_HAL_INTERRUPT_MTU3_TGI3A   , 49  ;    \
 268         exception_vector_int CYGNUM_HAL_INTERRUPT_MTU3_TGI3B   , 50  ;    \
 269         exception_vector_int CYGNUM_HAL_INTERRUPT_MTU3_TGI3C   , 51  ;    \
 270         exception_vector_int CYGNUM_HAL_INTERRUPT_MTU3_TGI3D   , 52  ;    \
 271         exception_vector_int CYGNUM_HAL_INTERRUPT_MTU3_TGI3V   , 53  ;    \
 272         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 54  ;    \
 273         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 55  ;    \
 274         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 56  ;    \
 275         exception_vector_int CYGNUM_HAL_INTERRUPT_MTU4_TGI4A   , 57  ;    \
 276         exception_vector_int CYGNUM_HAL_INTERRUPT_MTU4_TGI4B   , 58  ;    \
 277         exception_vector_int CYGNUM_HAL_INTERRUPT_MTU4_TGI4C   , 59  ;    \
 278         exception_vector_int CYGNUM_HAL_INTERRUPT_MTU4_TGI4D   , 60  ;    \
 279         exception_vector_int CYGNUM_HAL_INTERRUPT_MTU4_TGI4V   , 61  ;    \
 280         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 62  ;    \
 281         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 63  ;    \
 282         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 64  ;    \
 283         exception_vector_int CYGNUM_HAL_INTERRUPT_SCI0_ERI0    , 65  ;    \
 284         exception_vector_int CYGNUM_HAL_INTERRUPT_SCI0_RXI0    , 66  ;    \
 285         exception_vector_int CYGNUM_HAL_INTERRUPT_SCI0_TXI0    , 67  ;    \
 286         exception_vector_int CYGNUM_HAL_INTERRUPT_SCI0_TEI0    , 68  ;    \
 287         exception_vector_int CYGNUM_HAL_INTERRUPT_SCI1_ERI1    , 69  ;    \
 288         exception_vector_int CYGNUM_HAL_INTERRUPT_SCI1_RXI1    , 70  ;    \
 289         exception_vector_int CYGNUM_HAL_INTERRUPT_SCI1_TXI1    , 71  ;    \
 290         exception_vector_int CYGNUM_HAL_INTERRUPT_SCI1_TEI1    , 72  ;    \
 291         exception_vector_int CYGNUM_HAL_INTERRUPT_AD_ADI0      , 73  ;    \
 292         exception_vector_int CYGNUM_HAL_INTERRUPT_AD_ADI1      , 74  ;    \
 293         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 75  ;    \
 294         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 76  ;    \
 295         exception_vector_int CYGNUM_HAL_INTERRUPT_DTC_SWDTCE   , 77  ;    \
 296         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 78  ;    \
 297         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 79  ;    \
 298         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 80  ;    \
 299         exception_vector_int CYGNUM_HAL_INTERRUPT_CMT0_CMI0    , 81  ;    \
 300         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 82  ;    \
 301         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 83  ;    \
 302         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 84  ;    \
 303         exception_vector_int CYGNUM_HAL_INTERRUPT_CMT1_CMI1    , 85  ;    \
 304         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 86  ;    \
 305         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 87  ;    \
 306         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 88  ;    \
 307         exception_vector_int CYGNUM_HAL_INTERRUPT_WDT_ITI      , 89  ;    \
 308         exception_vector_int CYGNUM_HAL_INTERRUPT_BSC_CMI      , 90  ;    \
 309         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 91  ;    \
 310         exception_vector_int CYGNUM_HAL_INTERRUPT_VAR_RESERVED , 92  ;    \
 311         exception_vector_int CYGNUM_HAL_INTERRUPT_BSC_CMI      , 93  ;    \
 312         .set    vecno, CYGNUM_HAL_INTERRUPT_VAR_RESERVED             ;    \
 313         .rept   (256-CYGNUM_HAL_INTERRUPT_VAR_RESERVED)              ;    \
 314         exception_vector_int vecno                                   ;    \
 315         .set    vecno, vecno+1                                       ;    \
 316         .endr
 317
 318 // The vector used by the Real time clock
 319 #ifndef CYGNUM_HAL_INTERRUPT_RTC
 320 # define CYGNUM_HAL_INTERRUPT_RTC             CYGNUM_HAL_INTERRUPT_CMT0_CMI0
 321 #endif
 322
 323 #else
 324
 325 # error "No vectors defined for this INTC type"
 326
 327 #endif
 328
 329 //----------------------------------------------------------------------------
 330 // Platform may provide extensions to the interrupt configuration functions
 331 // via these macros. The first macro is put inside the functions's
 332 // switch statements, the last two called as functions.
 333 #ifndef CYGPRI_HAL_INTERRUPT_UPDATE_LEVEL_PLF
 334 # define CYGPRI_HAL_INTERRUPT_UPDATE_LEVEL_PLF(vec, level)
 335 # define CYGPRI_HAL_INTERRUPT_ACKNOWLEDGE_PLF(vec)
 336 # define CYGPRI_HAL_INTERRUPT_CONFIGURE_PLF(vec)
 337 #endif
 338
 339 #ifndef __ASSEMBLER__
 340 //--------------------------------------------------------------------------
 341 // Clock control, using Free-running Timer to match on compare register A
 342
 343 #include <cyg/hal/sh_regs.h>            // register definitions
 344 #include <cyg/hal/hal_io.h>             // io macros
 345 #include <cyg/infra/cyg_ass.h>          // CYG_FAIL
 346
 347 #if defined(CYGARC_SH_MOD_FRT)
 348 #define HAL_CLOCK_VAR_INITIALIZE( _period_ )                                \
 349     CYG_MACRO_START                                                         \
 350     register cyg_uint8 _tier_;                                              \
 351                                                                             \
 352     /* Disable interrupts while programming the timer */                    \
 353     HAL_READ_UINT8(CYGARC_REG_TIER, _tier_);                                \
 354     HAL_WRITE_UINT8(CYGARC_REG_TIER, 0);                                    \
 355                                                                             \
 356     /* Clear counter register */                                            \
 357     HAL_WRITE_UINT8(CYGARC_REG_FRC, 0);                                     \
 358     /* Set compare A register */                                            \
 359     HAL_WRITE_UINT8(CYGARC_REG_TOCR, CYGARC_REG_TOCR_OLVLA);                \
 360     HAL_WRITE_UINT16(CYGARC_REG_OCR, _period_);                             \
 361                                                                             \
 362     /* Enable match A counter clear */                                      \
 363     HAL_WRITE_UINT8(CYGARC_REG_FTCSR, CYGARC_REG_FTCSR_CCLRA);              \
 364     /* Set interrupt prescaling */                                          \
 365     HAL_WRITE_UINT8(CYGARC_REG_TCR,                                         \
 366                      ((8==CYGHWR_HAL_SH_FRT_PRESCALE) ?                     \
 367                           CYGARC_REG_TCR_CLK_8 :                            \
 368                       (32==CYGHWR_HAL_SH_FRT_PRESCALE) ?                    \
 369                           CYGARC_REG_TCR_CLK_32:                            \
 370                       (128==CYGHWR_HAL_SH_FRT_PRESCALE) ?                   \
 371                           CYGARC_REG_TCR_CLK_128:CYGARC_REG_TCR_CLK_EXT));  \
 372                                                                             \
 373                                                                             \
 374     CYG_MACRO_END
 375
 376 // HAL_CLOCK_VAR_INITIALIZE is called from hal_variant_init since the
 377 // FRT is also used by the hal_delay_us code.
 378 #define HAL_CLOCK_INITIALIZE( _period_ )                                    \
 379     CYG_MACRO_START                                                         \
 380     register cyg_uint8 _tier_;                                              \
 381                                                                             \
 382     CYG_ASSERT((cyg_uint16)(_period_) < (cyg_uint16)0xfffe,                 \
 383                "period too large for 16bit FRT");                           \
 384                                                                             \
 385     /* Disable interrupts while programming the timer */                    \
 386     HAL_READ_UINT8(CYGARC_REG_TIER, _tier_);                                \
 387     HAL_WRITE_UINT8(CYGARC_REG_TIER, 0);                                    \
 388                                                                             \
 389     /* Set compare A register */                                            \
 390     HAL_WRITE_UINT8(CYGARC_REG_TOCR, CYGARC_REG_TOCR_OLVLA);                \
 391     HAL_WRITE_UINT16(CYGARC_REG_OCR, _period_);                             \
 392                                                                             \
 393     /* Enable interrupt */                                                  \
 394     _tier_ |= CYGARC_REG_TIER_OCIAE;                                        \
 395     HAL_WRITE_UINT8(CYGARC_REG_TIER, _tier_);                               \
 396                                                                             \
 397     CYG_MACRO_END
 398
 399 #define HAL_CLOCK_RESET( _vector_, _period_ )   \
 400     CYG_MACRO_START                             \
 401     register cyg_uint8 _ftcsr_;                 \
 402                                                 \
 403     /* Clear match flag */                      \
 404     HAL_READ_UINT8(CYGARC_REG_FTCSR, _ftcsr_);  \
 405     _ftcsr_ &= ~CYGARC_REG_FTCSR_OCFA;          \
 406     HAL_WRITE_UINT8(CYGARC_REG_FTCSR, _ftcsr_); \
 407                                                 \
 408     CYG_MACRO_END
 409
 410 #define HAL_CLOCK_READ( _pvalue_ )              \
 411     CYG_MACRO_START                             \
 412     register cyg_uint16 _frc_;                  \
 413                                                 \
 414     HAL_READ_UINT16(CYGARC_REG_FRC, _frc_);     \
 415                                                 \
 416     *(_pvalue_) = _frc_;                        \
 417     CYG_MACRO_END
 418
 419 #elif defined(CYGARC_SH_MOD_CMT)
 420
 421 /* Compare Match Timer 0 is used for the eCos kernel RTC */
 422 #define HAL_CLOCK_VAR_INITIALIZE( _period_ )                                \
 423     CYG_MACRO_START                                                         \
 424     register cyg_uint16 _tmp_;                                              \
 425                                                                             \
 426     /* Disable timer while programming it */                                \
 427     HAL_READ_UINT16(CYGARC_REG_CMSTR, _tmp_);                               \
 428     HAL_WRITE_UINT16(CYGARC_REG_CMSTR, _tmp_ & ~CYGARC_REG_CMSTR_STR0);     \
 429                                                                             \
 430     /* Clear counter register */                                            \
 431     HAL_WRITE_UINT16(CYGARC_REG_CMCNT0, 0);                                 \
 432     /* Set compare 0 register */                                            \
 433     HAL_WRITE_UINT16(CYGARC_REG_CMCOR0, _period_);                          \
 434                                                                             \
 435     /* Set prescaling and disable interrupts */                             \
 436     HAL_WRITE_UINT16(CYGARC_REG_CMCSR0,                                     \
 437                      ((8==CYGHWR_HAL_SH_CMT_PRESCALE) ?                     \
 438                           CYGARC_REG_CMCSR_CLK_8 :                          \
 439                       (32==CYGHWR_HAL_SH_CMT_PRESCALE) ?                    \
 440                           CYGARC_REG_CMCSR_CLK_32:                          \
 441                       (128==CYGHWR_HAL_SH_CMT_PRESCALE) ?                   \
 442                           CYGARC_REG_CMCSR_CLK_128:CYGARC_REG_CMCSR_CLK_512));  \
 443                                                                             \
 444     /* Start timer */                                                       \
 445     HAL_WRITE_UINT16(CYGARC_REG_CMSTR, _tmp_ | CYGARC_REG_CMSTR_STR0);      \
 446                                                                             \
 447     CYG_MACRO_END
 448
 449 // HAL_CLOCK_VAR_INITIALIZE is called from hal_variant_init since the
 450 // CMT0 is also used by the hal_delay_us code.
 451 #define HAL_CLOCK_INITIALIZE( _period_ )                                    \
 452     CYG_MACRO_START                                                         \
 453     register cyg_uint16 _tmp_;                                              \
 454                                                                             \
 455     CYG_ASSERT((cyg_uint16)(_period_) < (cyg_uint16)0xfffe,                 \
 456                "period too large for 16bit CMT");                           \
 457                                                                             \
 458     /* Disable timer while programming it */                                \
 459     HAL_READ_UINT16(CYGARC_REG_CMSTR, _tmp_);                               \
 460     HAL_WRITE_UINT16(CYGARC_REG_CMSTR, _tmp_ & ~CYGARC_REG_CMSTR_STR0);     \
 461                                                                             \
 462     /* Clear counter register */                                            \
 463     HAL_WRITE_UINT16(CYGARC_REG_CMCNT0, 0);                                 \
 464     /* Set compare 0 register */                                            \
 465     HAL_WRITE_UINT16(CYGARC_REG_CMCOR0, _period_);                          \
 466                                                                             \
 467     /* Set prescaling and enable interrupts */                              \
 468     HAL_WRITE_UINT16(CYGARC_REG_CMCSR0, CYGARC_REG_CMCSR_CMIE |             \
 469                      ((8==CYGHWR_HAL_SH_CMT_PRESCALE) ?                     \
 470                           CYGARC_REG_CMCSR_CLK_8 :                          \
 471                       (32==CYGHWR_HAL_SH_CMT_PRESCALE) ?                    \
 472                           CYGARC_REG_CMCSR_CLK_32:                          \
 473                       (128==CYGHWR_HAL_SH_CMT_PRESCALE) ?                   \
 474                           CYGARC_REG_CMCSR_CLK_128:CYGARC_REG_CMCSR_CLK_512));  \
 475                                                                             \
 476     /* Start timer */                                                       \
 477     HAL_WRITE_UINT16(CYGARC_REG_CMSTR, _tmp_ | CYGARC_REG_CMSTR_STR0);      \
 478                                                                             \
 479     CYG_MACRO_END
 480
 481 #define HAL_CLOCK_RESET( _vector_, _period_ )   \
 482     CYG_MACRO_START                             \
 483     register cyg_uint16 _tmp_;                  \
 484                                                 \
 485     /* Clear match flag */                      \
 486     HAL_READ_UINT16(CYGARC_REG_CMCSR0, _tmp_);  \
 487     _tmp_ &= ~CYGARC_REG_CMCSR_CMF;             \
 488     HAL_WRITE_UINT16(CYGARC_REG_CMCSR0, _tmp_); \
 489                                                 \
 490     CYG_MACRO_END
 491
 492 #define HAL_CLOCK_READ( _pvalue_ )              \
 493     CYG_MACRO_START                             \
 494     register cyg_uint16 _tmp_;                  \
 495                                                 \
 496     HAL_READ_UINT16(CYGARC_REG_CMCNT0, _tmp_);  \
 497                                                 \
 498     *(_pvalue_) = _tmp_;                        \
 499     CYG_MACRO_END
 500
 501
 502
 503 #else
 504 # error "No RTC handling defined"
 505 #endif
 506
 507
 508
 509 #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
 510 #define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ(_pvalue_)
 511 #endif
 512
 513
 514 //----------------------------------------------------------------------------
 515 // Reset.
 516 #ifndef HAL_PLATFORM_RESET
 517 #define HAL_PLATFORM_RESET()                                                                    \
 518  CYG_MACRO_START                                                                                \
 519  HAL_WRITE_UINT16(CYGARC_REG_RSTCSR_W, CYGARC_REG_RSTCSR_W_RSTx_MAGIC|CYGARC_REG_RSTCSR_RSTE);  \
 520  HAL_WRITE_UINT16(CYGARC_REG_WTCNT_W, CYGARC_REG_WTCNT_W_MAGIC|0xfe);                           \
 521  HAL_WRITE_UINT16(CYGARC_REG_WTCSR_W, CYGARC_REG_WTCSR_W_MAGIC|CYGARC_REG_WTCSR_TME|CYGARC_REG_WTCSR_WTIT);           \
 522  /* wait for it */                                                                              \
 523  for(;;) ;                                                                                      \
 524  CYG_MACRO_END
 525 #else
 526 #define HAL_PLATFORM_RESET()
 527 #endif
 528
 529 #endif // __ASSEMBLER__
 530
 531 //--------------------------------------------------------------------------
 532 #endif // ifndef CYGONCE_VAR_INTR_H
 533 // End of var_intr.h