1 //=============================================================================
5 // PCIC (PCI controller) Module register definitions
7 //=============================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
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38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //=============================================================================
41 //#####DESCRIPTIONBEGIN####
47 //####DESCRIPTIONEND####
49 //=============================================================================
51 //--------------------------------------------------------------------------
52 // PCI control registers
53 #define CYGARC_REG_PCIC_BASE 0xfe200000
54 #define CYGARC_REG_PCIC_IO_BASE 0xfe240000
55 #define CYGARC_REG_PCIC_IO_BASE_MASK 0x0003ffff
56 #define CYGARC_REG_PCIC_MEM_BASE 0xfd000000
60 #define CYGARC_REG_PCIC_CFG (CYGARC_REG_PCIC_BASE)
62 #define CYGARC_REG_PCIC_CR (CYGARC_REG_PCIC_BASE + 0x100)
63 #define CYGARC_REG_PCIC_LSR0 (CYGARC_REG_PCIC_BASE + 0x104)
64 #define CYGARC_REG_PCIC_LSR1 (CYGARC_REG_PCIC_BASE + 0x108)
65 #define CYGARC_REG_PCIC_LAR0 (CYGARC_REG_PCIC_BASE + 0x10c)
66 #define CYGARC_REG_PCIC_LAR1 (CYGARC_REG_PCIC_BASE + 0x110)
67 #define CYGARC_REG_PCIC_INT (CYGARC_REG_PCIC_BASE + 0x114)
68 #define CYGARC_REG_PCIC_INTM (CYGARC_REG_PCIC_BASE + 0x118)
69 #define CYGARC_REG_PCIC_ALR (CYGARC_REG_PCIC_BASE + 0x11c)
70 #define CYGARC_REG_PCIC_CLR (CYGARC_REG_PCIC_BASE + 0x120)
71 #define CYGARC_REG_PCIC_AINT (CYGARC_REG_PCIC_BASE + 0x130)
72 #define CYGARC_REG_PCIC_AINTM (CYGARC_REG_PCIC_BASE + 0x134)
73 #define CYGARC_REG_PCIC_BMLR (CYGARC_REG_PCIC_BASE + 0x138)
74 #define CYGARC_REG_PCIC_DMABT (CYGARC_REG_PCIC_BASE + 0x140)
75 #define CYGARC_REG_PCIC_DPA0 (CYGARC_REG_PCIC_BASE + 0x180)
76 #define CYGARC_REG_PCIC_DLA0 (CYGARC_REG_PCIC_BASE + 0x184)
77 #define CYGARC_REG_PCIC_DTC0 (CYGARC_REG_PCIC_BASE + 0x188)
78 #define CYGARC_REG_PCIC_DCR0 (CYGARC_REG_PCIC_BASE + 0x18c)
79 #define CYGARC_REG_PCIC_DPA1 (CYGARC_REG_PCIC_BASE + 0x190)
80 #define CYGARC_REG_PCIC_DLA1 (CYGARC_REG_PCIC_BASE + 0x194)
81 #define CYGARC_REG_PCIC_DTC1 (CYGARC_REG_PCIC_BASE + 0x198)
82 #define CYGARC_REG_PCIC_DCR1 (CYGARC_REG_PCIC_BASE + 0x19c)
83 #define CYGARC_REG_PCIC_DPA2 (CYGARC_REG_PCIC_BASE + 0x1a0)
84 #define CYGARC_REG_PCIC_DLA2 (CYGARC_REG_PCIC_BASE + 0x1a4)
85 #define CYGARC_REG_PCIC_DTC2 (CYGARC_REG_PCIC_BASE + 0x1a8)
86 #define CYGARC_REG_PCIC_DCR2 (CYGARC_REG_PCIC_BASE + 0x1ac)
87 #define CYGARC_REG_PCIC_DPA3 (CYGARC_REG_PCIC_BASE + 0x1b0)
88 #define CYGARC_REG_PCIC_DLA3 (CYGARC_REG_PCIC_BASE + 0x1b4)
89 #define CYGARC_REG_PCIC_DTC3 (CYGARC_REG_PCIC_BASE + 0x1b8)
90 #define CYGARC_REG_PCIC_DCR3 (CYGARC_REG_PCIC_BASE + 0x1bc)
91 #define CYGARC_REG_PCIC_PAR (CYGARC_REG_PCIC_BASE + 0x1c0)
92 #define CYGARC_REG_PCIC_MBR (CYGARC_REG_PCIC_BASE + 0x1c4)
93 #define CYGARC_REG_PCIC_IOBR (CYGARC_REG_PCIC_BASE + 0x1c8)
94 #define CYGARC_REG_PCIC_PINT (CYGARC_REG_PCIC_BASE + 0x1cc)
95 #define CYGARC_REG_PCIC_PINTM (CYGARC_REG_PCIC_BASE + 0x1d0)
96 #define CYGARC_REG_PCIC_CLKR (CYGARC_REG_PCIC_BASE + 0x1d4)
97 #define CYGARC_REG_PCIC_BCR1 (CYGARC_REG_PCIC_BASE + 0x1e0)
98 #define CYGARC_REG_PCIC_BCR2 (CYGARC_REG_PCIC_BASE + 0x1e4)
99 #define CYGARC_REG_PCIC_WCR1 (CYGARC_REG_PCIC_BASE + 0x1e8)
100 #define CYGARC_REG_PCIC_WCR2 (CYGARC_REG_PCIC_BASE + 0x1ec)
101 #define CYGARC_REG_PCIC_WCR3 (CYGARC_REG_PCIC_BASE + 0x1f0)
102 #define CYGARC_REG_PCIC_MCR (CYGARC_REG_PCIC_BASE + 0x1f4)
103 #define CYGARC_REG_PCIC_PCTR (CYGARC_REG_PCIC_BASE + 0x200)
104 #define CYGARC_REG_PCIC_PDTR (CYGARC_REG_PCIC_BASE + 0x204)
105 #define CYGARC_REG_PCIC_PDR (CYGARC_REG_PCIC_BASE + 0x220)
108 #define CYGARC_REG_PCIC_CR_MAGIC 0xa5000000
109 #define CYGARC_REG_PCIC_CR_TRDSGL 0x00000200
110 #define CYGARC_REG_PCIC_CR_BYTESWAP 0x00000100
111 #define CYGARC_REG_PCIC_CR_PCIPUP 0x00000080
112 #define CYGARC_REG_PCIC_CR_BMABT 0x00000040
113 #define CYGARC_REG_PCIC_CR_MD10 0x00000020
114 #define CYGARC_REG_PCIC_CR_MD9 0x00000010
115 #define CYGARC_REG_PCIC_CR_SERR 0x00000008
116 #define CYGARC_REG_PCIC_CR_INTA 0x00000004
117 #define CYGARC_REG_PCIC_CR_PCIRST 0x00000002
118 #define CYGARC_REG_PCIC_CR_CFINIT 0x00000001
119 #define CYGARC_REG_PCIC_CR_INIT 0xa5000001
121 #define CYGARC_REG_PCIC_IOBR_MASK 0xfffc0000
123 #define CYGARC_REG_PCIC_PAR_ENABLE 0x80000000
124 #define CYGARC_REG_PCIC_PAR_BUSNO_shift 16
125 #define CYGARC_REG_PCIC_PAR_FUNC_shift 8
128 #define CYGARC_REG_PCIC_INTM_M_LOCKON 0x00008000
129 #define CYGARC_REG_PCIC_INTM_T_TGT_ABORT 0x00004000
130 #define CYGARC_REG_PCIC_INTM_TGT_RETRY 0x00000200
131 #define CYGARC_REG_PCIC_INTM_MST_DIS 0x00000100
132 #define CYGARC_REG_PCIC_INTM_ADRPERR 0x00000080
133 #define CYGARC_REG_PCIC_INTM_SERR_DET 0x00000040
134 #define CYGARC_REG_PCIC_INTM_T_DPERR_WT 0x00000020
135 #define CYGARC_REG_PCIC_INTM_T_PERR_DET 0x00000010
136 #define CYGARC_REG_PCIC_INTM_M_TGT_ABORT 0x00000008
137 #define CYGARC_REG_PCIC_INTM_M_MST_ABORT 0x00000004
138 #define CYGARC_REG_PCIC_INTM_M_DPERR_WT 0x00000002
139 #define CYGARC_REG_PCIC_INTM_M_DPERR_RD 0x00000001
140 #define CYGARC_REG_PCIC_INTM_INIT 0x0000c3ff
142 #define CYGARC_REG_PCIC_AINTM_MST_BRKN 0x00002000
143 #define CYGARC_REG_PCIC_AINTM_TGT_BUSTO 0x00001000
144 #define CYGARC_REG_PCIC_AINTM_MST_BUSTO 0x00000800
145 #define CYGARC_REG_PCIC_AINTM_TGT_ABORT 0x00000008
146 #define CYGARC_REG_PCIC_AINTM_MST_ABORT 0x00000004
147 #define CYGARC_REG_PCIC_AINTM_DPERR_WT 0x00000002
148 #define CYGARC_REG_PCIC_AINTM_DPERR_RD 0x00000001
149 #define CYGARC_REG_PCIC_AINTM_INIT 0x0000380f