1 # ====================================================================
3 # hal_sh_sh4_202_md.cdl
5 # SuperH SH4-202 MicroDev CPU board configuration data
7 # ====================================================================
8 #####ECOSGPLCOPYRIGHTBEGIN####
9 ## -------------------------------------------
10 ## This file is part of eCos, the Embedded Configurable Operating System.
11 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12 ## Copyright (C) 2003 Nick Garnett
14 ## eCos is free software; you can redistribute it and/or modify it under
15 ## the terms of the GNU General Public License as published by the Free
16 ## Software Foundation; either version 2 or (at your option) any later version.
18 ## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
19 ## WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
23 ## You should have received a copy of the GNU General Public License along
24 ## with eCos; if not, write to the Free Software Foundation, Inc.,
25 ## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 ## As a special exception, if other files instantiate templates or use macros
28 ## or inline functions from this file, or you compile this file and link it
29 ## with other works to produce a work based on this file, this file does not
30 ## by itself cause the resulting work to be covered by the GNU General Public
31 ## License. However the source code for this file must still be made available
32 ## in accordance with section (3) of the GNU General Public License.
34 ## This exception does not invalidate any other reasons why a work based on
35 ## this file might be covered by the GNU General Public License.
37 ## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
38 ## at http://sources.redhat.com/ecos/ecos-license/
39 ## -------------------------------------------
40 #####ECOSGPLCOPYRIGHTEND####
41 # ====================================================================
42 ######DESCRIPTIONBEGIN####
45 # Original data: jskov
49 #####DESCRIPTIONEND####
51 # ====================================================================
53 cdl_package CYGPKG_HAL_SH_SH4_202_MD {
54 display "SuperH SH4-202 MicroDev CPU Board"
56 requires CYGPKG_HAL_SH_202
57 requires CYGHWR_HAL_SH_IRQ_USE_IRQLVL
58 requires ! CYGHWR_HAL_SH_BIGENDIAN
59 define_header hal_sh_sh4_202_md.h
62 The SH4-202-MD HAL package provides the support needed to run
63 eCos on a SuperH SH4-202 MicroDev CPU board."
65 compile hal_diag.c plf_misc.c
67 implements CYGINT_HAL_DEBUG_GDB_STUBS
68 implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
69 implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
70 implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
73 puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_sh.h>"
74 puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_sh_sh4_202_md.h>"
76 puts $::cdl_header "#define CYGNUM_HAL_SH_SH4_SCIF_PORTS 1"
77 puts $::cdl_header "#define CYGHWR_HAL_VSR_TABLE 0x88000000"
78 puts $::cdl_header "#define CYGHWR_HAL_VECTOR_TABLE 0x88000100"
80 puts $::cdl_header "#define HAL_PLATFORM_CPU \"SH4-202\""
81 puts $::cdl_header "#define HAL_PLATFORM_BOARD \"MicroDev CPU Board\""
82 puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\""
85 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
86 display "Number of communication channels on the board"
91 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
92 display "Debug serial port"
94 legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
97 The MicroDev board has one serial port."
100 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
101 display "Default console channel."
106 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
107 display "Diagnostic serial port"
109 legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
110 default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
112 The MicroDev board has one serial port which is used as both
113 the diagnostic and console channel."
116 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD {
117 display "Console/GDB serial port baud rate"
119 legal_values 9600 19200 38400 57600 115200
121 define CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD
123 This option controls the default baud rate used for the
124 Console/GDB connection."
127 cdl_component CYGHWR_HAL_SH_PLF_CLOCK_SETTINGS {
128 display "SH on-chip platform clock controls"
130 The various clocks used by the system are derived from
135 cdl_option CYGHWR_HAL_SH_OOC_XTAL {
136 display "SH clock crystal"
138 legal_values 8000000 to 50000000
139 default_value 33000000
142 This option specifies the frequency of the crystal all
143 other clocks are derived from."
146 cdl_option CYGHWR_HAL_SH_OOC_CKIO {
147 display "SH clock CKIO output enable"
150 This selects whether CKIO output is enabled."
153 cdl_option CYGHWR_HAL_SH_OOC_PLL_1 {
154 display "SH clock PLL circuit 1"
157 legal_values { 0 4 6 8 }
159 This selects the multiplication factor provided by
163 cdl_option CYGHWR_HAL_SH_OOC_PLL_2 {
164 display "SH clock PLL circuit 2"
169 This selects the multiplication factor provided by
170 PLL2. If PLL2 is disabled this option should
174 cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_1 {
175 display "SH clock divider 1"
180 This divider option affects all clocks."
183 cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_IFC {
184 display "SH CPU clock divider"
187 legal_values { 1 2 3 4 6 8 }
189 This divider option affects the CPU clock."
192 cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_BFC {
193 display "SH bus clock divider"
196 legal_values { 1 2 3 4 6 8 }
198 This divider option affects the bus clock."
201 cdl_option CYGHWR_HAL_SH_OOC_DIVIDER_PFC {
202 display "SH peripheral clock divider"
205 legal_values { 1 2 3 4 6 8 }
207 This divider option affects the peripheral clock."
210 cdl_option CYGHWR_HAL_SH_OOC_CLOCK_MODE {
211 display "SH clock mode"
214 legal_values { 0 1 2 3 4 5 }
216 This option must mirror the clock mode hardwired on
217 the MD0-MD2 pins of the CPU in order to correctly
218 initialize the FRQCR register."
223 cdl_component CYG_HAL_STARTUP {
224 display "Startup type"
226 legal_values {"RAM" "ROM" }
227 default_value {"RAM"}
229 define -file system.h CYG_HAL_STARTUP
231 When targetting the MicroDev board it is possible to build
232 the system for either RAM bootstrap or ROM bootstrap.
233 RAM bootstrap generally requires that the board
234 is equipped with ROMs containing a suitable ROM monitor or
235 equivalent software that allows GDB to download the eCos
236 application on to the board. The ROM bootstrap typically
237 requires that the eCos application be blown into flash ROM or
238 equivalent technology."
241 cdl_component CYGBLD_GLOBAL_OPTIONS {
242 display "Global build options"
247 Global build options including control over
248 compiler flags, linker flags and choice of toolchain."
251 cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
252 display "Global command prefix"
255 default_value { "sh-elf" }
256 # default_value { "sh-superh-elf" }
258 This option specifies the command prefix used when
259 invoking the build tools."
262 cdl_option CYGBLD_GLOBAL_CFLAGS {
263 display "Global compiler flags"
266 default_value { CYGHWR_HAL_SH_BIGENDIAN ? "-mb -m4 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -ggdb -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" : "-ml -m4 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -ggdb -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
268 This option controls the global compiler flags which
269 are used to compile all packages by
270 default. Individual packages may define
271 options which override these global flags."
274 cdl_option CYGBLD_GLOBAL_LDFLAGS {
275 display "Global linker flags"
278 default_value { CYGHWR_HAL_SH_BIGENDIAN ? "-mb -m4 -ggdb -nostdlib -Wl,--gc-sections -Wl,-static" : "-ml -m4 -ggdb -nostdlib -Wl,--gc-sections -Wl,-static" }
280 This option controls the global linker flags. Individual
281 packages may define options which override these global flags."
284 cdl_option CYGBLD_BUILD_GDB_STUBS {
285 display "Build GDB stub ROM image"
287 requires { CYG_HAL_STARTUP == "ROM" }
288 requires CYGSEM_HAL_ROM_MONITOR
289 requires CYGBLD_BUILD_COMMON_GDB_STUBS
290 requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
291 requires ! CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
292 requires ! CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
293 requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
294 requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
297 This option enables the building of the GDB stubs for the
298 board. The common HAL controls takes care of most of the
299 build process, but the final conversion from ELF image to
300 binary data is handled by the platform CDL, allowing
301 relocation of the data if necessary."
304 <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
305 $(OBJCOPY) -O binary $< $@
310 cdl_component CYGHWR_MEMORY_LAYOUT {
311 display "Memory layout"
314 calculated { CYG_HAL_STARTUP == "RAM" ? "sh_sh4_202_md_ram" : \
315 "sh_sh4_202_md_rom" }
317 cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
318 display "Memory layout linker script fragment"
321 define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
322 calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_sh_sh4_202_md_ram.ldi>" : \
323 "<pkgconf/mlt_sh_sh4_202_md_rom.ldi>" }
326 cdl_option CYGHWR_MEMORY_LAYOUT_H {
327 display "Memory layout header file"
330 define -file system.h CYGHWR_MEMORY_LAYOUT_H
331 calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_sh_sh4_202_md_ram.h>" : \
332 "<pkgconf/mlt_sh_sh4_202_md_rom.h>" }
336 cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
337 display "Work with a ROM monitor"
339 legal_values { "GDB_stubs" }
340 default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
341 requires { CYG_HAL_STARTUP == "RAM" }
342 parent CYGPKG_HAL_ROM_MONITOR
344 Support can be enabled for boot ROMs or ROM monitors which contain
345 GDB stubs. This support changes various eCos semantics such as
346 the encoding of diagnostic output, and the overriding of hardware
350 cdl_option CYGSEM_HAL_ROM_MONITOR {
351 display "Behave as a ROM monitor"
354 parent CYGPKG_HAL_ROM_MONITOR
355 requires { CYG_HAL_STARTUP == "ROM" }
357 Enable this option if this program is to be used as a ROM monitor,
358 i.e. applications will be loaded into RAM on the board, and this
359 ROM monitor may process exceptions or interrupts generated from the
360 application. This enables features such as utilizing a separate
361 interrupt stack when exceptions are generated."
364 cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
365 display "Redboot HAL options"
368 parent CYGPKG_REDBOOT
369 active_if CYGPKG_REDBOOT
371 This option lists the target's requirements for a valid Redboot
374 cdl_option CYGBLD_BUILD_REDBOOT_BIN {
375 display "Build Redboot ROM binary image"
376 active_if CYGBLD_BUILD_REDBOOT
379 description "This option enables the conversion of the Redboot ELF
380 image to a binary image suitable for ROM programming."
383 <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
384 $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
385 $(OBJCOPY) -O srec $< $(@:.bin=.srec)
386 $(OBJCOPY) -O binary $< $@