1 #ifndef CYGONCE_HAL_HAL_ARCH_H
2 #define CYGONCE_HAL_HAL_ARCH_H
4 //==========================================================================
8 // Architecture specific abstractions
10 //==========================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
18 // Software Foundation; either version 2 or (at your option) any later version.
20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 // You should have received a copy of the GNU General Public License along
26 // with eCos; if not, write to the Free Software Foundation, Inc.,
27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
31 // with other works to produce a work based on this file, this file does not
32 // by itself cause the resulting work to be covered by the GNU General Public
33 // License. However the source code for this file must still be made available
34 // in accordance with section (3) of the GNU General Public License.
36 // This exception does not invalidate any other reasons why a work based on
37 // this file might be covered by the GNU General Public License.
39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //==========================================================================
44 //#####DESCRIPTIONBEGIN####
46 // Author(s): nickg,gthomas
47 // Contributors: nickg,jlarmour
49 // Purpose: Define architecture abstractions
50 // Usage: #include <cyg/hal/hal_arch.h>
52 //####DESCRIPTIONEND####
54 //==========================================================================
56 #include <pkgconf/hal.h>
57 #include <cyg/infra/cyg_type.h>
59 #include <cyg/hal/var_arch.h>
61 //--------------------------------------------------------------------------
62 // Processor saved states:
64 #define CYG_HAL_NEC_REG CYG_WORD32
65 #define CYG_HAL_NEC_REG_SIZE 4
69 // These are common to all saved states
70 CYG_HAL_NEC_REG d[32]; /* Data regs */
71 CYG_ADDRWORD pc; /* Program Counter */
72 CYG_ADDRWORD psw; /* Status Reg */
74 // These are only saved for exceptions and interrupts
75 CYG_ADDRWORD cause; /* Exception cause register */
76 CYG_ADDRWORD vector; /* Exception/interrupt number */
80 // Processor state register
82 #define CYGARC_PSW_ID 0x20 // Interrupt disable
83 #define CYGARC_PSW_EP 0x40 // Exception in progress
84 #define CYGARC_PSW_NP 0x80 // NMI in progress
86 //--------------------------------------------------------------------------
87 // Exception handling function.
88 // This function is defined by the kernel according to this prototype. It is
89 // invoked from the HAL to deal with any CPU exceptions that the HAL does
90 // not want to deal with itself. It usually invokes the kernel's exception
91 // delivery mechanism.
93 externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data );
95 //--------------------------------------------------------------------------
96 // Bit manipulation macros
98 externC cyg_uint32 hal_lsbit_index(cyg_uint32 mask);
99 externC cyg_uint32 hal_msbit_index(cyg_uint32 mask);
101 #define HAL_LSBIT_INDEX(index, mask) index = hal_lsbit_index(mask);
103 #define HAL_MSBIT_INDEX(index, mask) index = hal_msbit_index(mask);
105 //--------------------------------------------------------------------------
106 // Context Initialization
108 #define CYG_HAL_NEC_INIT_PSW 0x00000000
110 // Initialize the context of a thread.
112 // _sparg_ name of variable containing current sp, will be written with new sp
113 // _thread_ thread object address, passed as argument to entry point
114 // _entry_ entry point address.
115 // _id_ bit pattern used in initializing registers, for debugging.
116 #define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \
118 register CYG_WORD _sp_ = ((CYG_WORD)_sparg_)-56; \
119 register HAL_SavedRegisters *_regs_; \
121 _sp_ = _sp_ & 0xFFFFFFF0; \
122 _regs_ = (HAL_SavedRegisters *)(((_sp_) - sizeof(HAL_SavedRegisters))&0xFFFFFFF0); \
123 for( _i_ = 0; _i_ < 32; _i_++ ) (_regs_)->d[_i_] = (_id_)|_i_; \
124 (_regs_)->d[03] = (CYG_HAL_NEC_REG)(_sp_); /* SP = top of stack */ \
125 (_regs_)->d[04] = (CYG_HAL_NEC_REG)(_sp_); /* GP = top of stack */ \
126 (_regs_)->d[29] = (CYG_HAL_NEC_REG)(_sp_); /* FP = top of stack */ \
127 (_regs_)->d[06] = (CYG_HAL_NEC_REG)(_thread_); /* R6 = arg1 = thread ptr */ \
128 (_regs_)->d[31] = (CYG_HAL_NEC_REG)(_entry_); /* RA(d[31]) = entry point*/ \
129 (_regs_)->pc = (CYG_WORD)(_entry_); /* PC = entry point */ \
130 (_regs_)->psw = CYG_HAL_NEC_INIT_PSW; \
131 _sparg_ = (CYG_ADDRESS)_regs_; \
134 //--------------------------------------------------------------------------
135 // Context switch macros.
136 // The arguments are pointers to locations where the stack pointer
137 // of the current thread is to be stored, and from where the sp of the
138 // next thread is to be fetched.
140 externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from );
141 externC void hal_thread_load_context( CYG_ADDRESS to )
142 __attribute__ ((noreturn));
144 #define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \
145 hal_thread_switch_context( (CYG_ADDRESS)_tspptr_, \
146 (CYG_ADDRESS)_fspptr_);
148 #define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \
149 hal_thread_load_context( (CYG_ADDRESS)_tspptr_ );
151 //--------------------------------------------------------------------------
152 // Execution reorder barrier.
153 // When optimizing the compiler can reorder code. In multithreaded systems
154 // where the order of actions is vital, this can sometimes cause problems.
155 // This macro may be inserted into places where reordering should not happen.
156 // The "memory" keyword is potentially unnecessary, but it is harmless to
159 #define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" )
161 //--------------------------------------------------------------------------
162 // Breakpoint support
163 // HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to
164 // happen if executed.
165 // HAL_BREAKINST is the value of the breakpoint instruction and
166 // HAL_BREAKINST_SIZE is its size in bytes.
168 #define HAL_BREAKPOINT(_label_) \
169 asm volatile (" .globl _" #_label_ ";" \
174 #define HAL_BREAKINST 0x0585
175 #define HAL_BREAKINST_SIZE 2
177 //--------------------------------------------------------------------------
178 // Thread register state manipulation for GDB support.
180 // Default to a 32 bit register size for GDB register dumps.
181 #ifndef CYG_HAL_GDB_REG
182 #define CYG_HAL_GDB_REG CYG_WORD32
185 // Translate a stack pointer as saved by the thread context macros above into
186 // a pointer to a HAL_SavedRegisters structure.
187 #define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \
188 (_regs_) = (HAL_SavedRegisters *)(_sp_)
191 //--------------------------------------------------------------------------
198 cyg_uint32 r1,r2,r4,r5;
199 cyg_uint32 r20, r21, r22, r23;
200 cyg_uint32 r24, r25, r26, r27, r28;
206 #define CYGARC_JMP_BUF_SIZE (sizeof(hal_jmp_buf_t) / sizeof(cyg_uint32))
208 typedef cyg_uint32 hal_jmp_buf[ CYGARC_JMP_BUF_SIZE ];
210 externC int hal_setjmp(hal_jmp_buf env);
211 externC void hal_longjmp(hal_jmp_buf env, int val);
213 //-------------------------------------------------------------------------
215 // This macro is called in the idle thread loop, and gives the HAL the
216 // chance to insert code. Typical idle thread behaviour might be to halt the
219 externC void hal_idle_thread_action(cyg_uint32 loop_count);
221 #define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_)
223 //--------------------------------------------------------------------------
224 // Hardware specific test exit code. This is defined here simply to make
225 // setting a breakpoint on this function viable.
227 #define CYGHWR_TEST_PROGRAM_EXIT() \
229 static volatile int ctr; \
233 //--------------------------------------------------------------------------
234 // Minimal and sensible stack sizes: the intention is that applications
235 // will use these to provide a stack size in the first instance prior to
236 // proper analysis. Idle thread stack should be this big.
238 // THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES.
239 // THEY ARE HOWEVER ENOUGH TO START PROGRAMMING.
240 // YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES!
242 // This is not a config option because it should not be adjusted except
243 // under "enough rope" sort of disclaimers.
245 // Typical case stack frame size: return link + 4 pushed registers + some locals.
246 #define CYGNUM_HAL_STACK_FRAME_SIZE (48)
248 // Stack needed for a context switch:
249 #define CYGNUM_HAL_STACK_CONTEXT_SIZE (((32+12)*CYG_HAL_NEC_REG_SIZE)+(32*4))
252 // Interrupt + call to ISR, interrupt_end() and the DSR
253 #define CYGNUM_HAL_STACK_INTERRUPT_SIZE (4+2*CYGNUM_HAL_STACK_CONTEXT_SIZE)
255 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
257 // An interrupt stack which is large enough for all possible interrupt
258 // conditions (and only used for that purpose) exists. "User" stacks
259 // can be much smaller
261 #define CYGNUM_HAL_STACK_SIZE_MINIMUM (CYGNUM_HAL_STACK_CONTEXT_SIZE+ \
262 CYGNUM_HAL_STACK_INTERRUPT_SIZE*2+ \
263 CYGNUM_HAL_STACK_FRAME_SIZE*8)
264 #define CYGNUM_HAL_STACK_SIZE_TYPICAL (CYGNUM_HAL_STACK_SIZE_MINIMUM+1024)
266 #else // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
268 // No separate interrupt stack exists. Make sure all threads contain
269 // a stack sufficiently large.
271 #define CYGNUM_HAL_STACK_SIZE_MINIMUM (4096)
272 #define CYGNUM_HAL_STACK_SIZE_TYPICAL (4096)
276 //--------------------------------------------------------------------------
277 // Macros for switching context between two eCos instances (jump from
278 // code in ROM to code in RAM or vice versa).
279 #define CYGARC_HAL_SAVE_GP()
280 #define CYGARC_HAL_RESTORE_GP()
282 //--------------------------------------------------------------------------
283 #endif // CYGONCE_HAL_HAL_ARCH_H