1 //==========================================================================
5 // Interrupt class implementations
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
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38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
44 // Contributors: nickg
46 // Purpose: Interrupt class implementation
47 // Description: This file contains the definitions of the interrupt
50 //####DESCRIPTIONEND####
52 //==========================================================================
54 #include <pkgconf/kernel.h>
56 #include <cyg/kernel/ktypes.h> // base kernel types
57 #include <cyg/infra/cyg_trac.h> // tracing macros
58 #include <cyg/infra/cyg_ass.h> // assertion macros
59 #include <cyg/kernel/instrmnt.h> // instrumentation
61 #include <cyg/kernel/intr.hxx> // our header
63 #include <cyg/kernel/sched.hxx> // scheduler
65 #include <cyg/kernel/sched.inl>
67 // -------------------------------------------------------------------------
70 volatile cyg_int32 Cyg_Interrupt::disable_counter[CYGNUM_KERNEL_CPU_MAX];
72 Cyg_SpinLock Cyg_Interrupt::interrupt_disable_spinlock CYG_INIT_PRIORITY( INTERRUPTS );
74 CYG_INTERRUPT_STATE Cyg_Interrupt::interrupt_disable_state[CYGNUM_KERNEL_CPU_MAX];
76 // -------------------------------------------------------------------------
78 Cyg_Interrupt::Cyg_Interrupt(
79 cyg_vector vec, // Vector to attach to
80 cyg_priority pri, // Queue priority
81 CYG_ADDRWORD d, // Data pointer
82 cyg_ISR *ir, // Interrupt Service Routine
83 cyg_DSR *dr // Deferred Service Routine
86 CYG_REPORT_FUNCTION();
87 CYG_REPORT_FUNCARG5("vector=%d, priority=%d, data=%08x, isr=%08x, "
88 "dsr=%08x", vec, pri, d, ir, dr);
96 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST
103 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN
113 // -------------------------------------------------------------------------
115 Cyg_Interrupt::~Cyg_Interrupt()
117 CYG_REPORT_FUNCTION();
122 // -------------------------------------------------------------------------
123 // DSR handling statics:
125 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE
128 Cyg_Interrupt::dsr_table[CYGNUM_KERNEL_CPU_MAX][CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE];
130 cyg_ucount32 Cyg_Interrupt::dsr_table_head[CYGNUM_KERNEL_CPU_MAX];
132 volatile cyg_ucount32 Cyg_Interrupt::dsr_table_tail[CYGNUM_KERNEL_CPU_MAX];
136 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST
138 Cyg_Interrupt* volatile Cyg_Interrupt::dsr_list[CYGNUM_KERNEL_CPU_MAX];
142 // -------------------------------------------------------------------------
143 // Call any pending DSRs
146 Cyg_Interrupt::call_pending_DSRs_inner(void)
148 // CYG_REPORT_FUNCTION();
150 HAL_SMP_CPU_TYPE cpu = CYG_KERNEL_CPU_THIS();
152 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE
154 while( dsr_table_head[cpu] != dsr_table_tail[cpu] )
156 Cyg_Interrupt *intr = dsr_table[cpu][dsr_table_head[cpu]];
158 dsr_table_head[cpu]++;
159 if( dsr_table_head[cpu] >= CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE )
160 dsr_table_head[cpu] = 0;
162 CYG_INSTRUMENT_INTR(CALL_DSR, intr->vector, 0);
164 CYG_ASSERT( intr->dsr != NULL , "No DSR defined");
166 intr->dsr( intr->vector, 1, (CYG_ADDRWORD)intr->data );
171 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST
173 while( dsr_list[cpu] != NULL )
179 HAL_DISABLE_INTERRUPTS(old_intr);
181 intr = dsr_list[cpu];
182 dsr_list[cpu] = intr->next_dsr;
183 count = intr->dsr_count;
186 HAL_RESTORE_INTERRUPTS(old_intr);
188 CYG_ASSERT( intr->dsr != NULL , "No DSR defined");
190 intr->dsr( intr->vector, count, (CYG_ADDRWORD)intr->data );
199 cyg_interrupt_call_pending_DSRs(void)
201 Cyg_Interrupt::call_pending_DSRs_inner();
205 // Use HAL supported function to run through the DSRs, but executing using
206 // the separate interrupt stack if available. This function calls back
207 // into this module via 'cyg_interrupt_call_pending_DSRs' above, to keep
208 // the whole process as general as possible.
211 Cyg_Interrupt::call_pending_DSRs(void)
213 CYG_ASSERT( Cyg_Scheduler::get_sched_lock() == 1,
214 "DSRs being called with sched_lock not equal to 1");
215 HAL_INTERRUPT_STACK_CALL_PENDING_DSRS();
219 // -------------------------------------------------------------------------
222 Cyg_Interrupt::post_dsr(void)
224 // CYG_REPORT_FUNCTION();
225 HAL_SMP_CPU_TYPE cpu = CYG_KERNEL_CPU_THIS();
227 CYG_INSTRUMENT_INTR(POST_DSR, vector, 0);
231 // We need to disable interrupts during this part to
232 // guard against nested interrupts.
234 HAL_DISABLE_INTERRUPTS(old_intr);
236 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_TABLE
238 dsr_table[cpu][dsr_table_tail[cpu]++] = this;
239 if( dsr_table_tail[cpu] >= CYGNUM_KERNEL_INTERRUPTS_DSRS_TABLE_SIZE )
240 dsr_table_tail[cpu] = 0;
244 #ifdef CYGIMP_KERNEL_INTERRUPTS_DSRS_LIST
246 // Only add the interrupt to the dsr list if this is
247 // the first DSR call.
248 // At present DSRs are pushed onto the list and will be
249 // called in reverse order. We do not define the order
250 // in which DSRs are called, so this is acceptable.
252 if( dsr_count++ == 0 )
254 next_dsr = dsr_list[cpu];
255 dsr_list[cpu] = this;
260 HAL_RESTORE_INTERRUPTS(old_intr);
263 // -------------------------------------------------------------------------
264 // A C callable interface to Cyg_Interrupt::post_dsr() that can be used from
268 cyg_interrupt_post_dsr( CYG_ADDRWORD intr_obj )
270 Cyg_Interrupt* intr = (Cyg_Interrupt*) intr_obj;
274 // -------------------------------------------------------------------------
276 // FIXME: should have better name - Jifl
281 HAL_SavedRegisters *regs
284 // CYG_REPORT_FUNCTION();
286 #ifdef CYGPKG_KERNEL_SMP_SUPPORT
287 Cyg_Scheduler::lock();
290 // Sometimes we have a NULL intr object pointer.
291 cyg_vector vector = (intr!=NULL)?intr->vector:0;
293 CYG_INSTRUMENT_INTR(END, vector, isr_ret);
295 CYG_UNUSED_PARAM( cyg_vector, vector ); // prevent compiler warning
297 #ifndef CYGIMP_KERNEL_INTERRUPTS_CHAIN
299 // Only do this if we are in a non-chained configuration.
300 // If we are chained, then chain_isr below will do the DSR
303 if( isr_ret & Cyg_Interrupt::CALL_DSR && intr != NULL ) intr->post_dsr();
307 #ifdef CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT
309 // If we have GDB support enabled, and there is the possibility
310 // that this thread will be context switched as a result of this
311 // interrupt, then save the pointer to the saved thread context in
312 // the thread object so that GDB can get a meaningful context to
315 Cyg_Scheduler::get_current_thread()->set_saved_context(regs);
319 // Now unlock the scheduler, which may also call DSRs
320 // and cause a thread switch to happen.
322 Cyg_Scheduler::unlock();
324 #ifdef CYGDBG_KERNEL_DEBUG_GDB_THREAD_SUPPORT
326 Cyg_Scheduler::get_current_thread()->set_saved_context(0);
330 CYG_INSTRUMENT_INTR(RESTORE, vector, 0);
333 // -------------------------------------------------------------------------
334 // Interrupt chaining statics.
336 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN
338 Cyg_Interrupt *Cyg_Interrupt::chain_list[CYGNUM_HAL_ISR_TABLE_SIZE];
342 // -------------------------------------------------------------------------
343 // Chaining ISR inserted in HAL vector
345 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN
348 Cyg_Interrupt::chain_isr(cyg_vector vector, CYG_ADDRWORD data)
350 Cyg_Interrupt *p = *(Cyg_Interrupt **)data;
351 register cyg_uint32 isr_ret = 0;
352 register cyg_uint32 isr_chain_ret = 0;
354 CYG_INSTRUMENT_INTR(CHAIN_ISR, vector, 0);
358 if( p->vector == vector )
360 isr_ret = p->isr(vector, p->data);
362 isr_chain_ret |= isr_ret;
364 if( isr_ret & Cyg_Interrupt::CALL_DSR ) p->post_dsr();
366 if( isr_ret & Cyg_Interrupt::HANDLED ) break;
372 #ifdef HAL_DEFAULT_ISR
373 if( (isr_chain_ret & (Cyg_Interrupt::HANDLED|Cyg_Interrupt::CALL_DSR)) == 0 )
375 // If we finished the loop for some reason other than that an
376 // ISR has handled the interrupt, call any default ISR to either
377 // report the spurious interrupt, or do some other HAL level processing
378 // such as GDB interrupt detection etc.
380 HAL_DEFAULT_ISR( vector, 0 );
384 return isr_ret & ~Cyg_Interrupt::CALL_DSR;
389 // -------------------------------------------------------------------------
390 // Attach an ISR to an interrupt vector.
393 Cyg_Interrupt::attach(void)
395 CYG_REPORT_FUNCTION();
397 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
398 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
400 CYG_INSTRUMENT_INTR(ATTACH, vector, 0);
402 HAL_INTERRUPT_SET_LEVEL( vector, priority );
404 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN
406 CYG_ASSERT( next == NULL , "Cyg_Interrupt already on a list");
410 HAL_TRANSLATE_VECTOR( vector, index );
412 if( chain_list[index] == NULL )
415 // First Interrupt on this chain, just assign it and register
416 // the chain_isr with the HAL.
418 chain_list[index] = this;
420 HAL_INTERRUPT_IN_USE( vector, in_use );
421 CYG_ASSERT( 0 == in_use, "Interrupt vector not free.");
422 HAL_INTERRUPT_ATTACH( vector, chain_isr, &chain_list[index], NULL );
426 // There are already interrupts chained, add this one into the
427 // chain in priority order.
429 Cyg_Interrupt **p = &chain_list[index];
433 Cyg_Interrupt *n = *p;
435 if( n->priority < priority ) break;
449 HAL_INTERRUPT_IN_USE( vector, in_use );
450 CYG_ASSERT( 0 == in_use, "Interrupt vector not free.");
452 HAL_INTERRUPT_ATTACH( vector, isr, data, this );
459 // -------------------------------------------------------------------------
460 // Detach the ISR from the vector
463 Cyg_Interrupt::detach(void)
465 CYG_REPORT_FUNCTION();
467 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
468 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
470 CYG_INSTRUMENT_INTR(DETACH, vector, 0);
472 #ifdef CYGIMP_KERNEL_INTERRUPTS_CHAIN
474 // Remove the interrupt object from the vector chain.
478 HAL_TRANSLATE_VECTOR( vector, index );
480 Cyg_Interrupt **p = &chain_list[index];
484 Cyg_Interrupt *n = *p;
495 // If this was the last one, detach the vector.
497 if( chain_list[index] == NULL )
498 HAL_INTERRUPT_DETACH( vector, chain_isr );
502 HAL_INTERRUPT_DETACH( vector, isr );
510 // -------------------------------------------------------------------------
511 // Get the current service routine
514 Cyg_Interrupt::get_vsr(cyg_vector vector, cyg_VSR **vsr)
516 CYG_REPORT_FUNCTION();
517 CYG_REPORT_FUNCARG2("vector = %d, mem to put VSR in is at %08x", vector,
520 CYG_ASSERT( vector >= CYGNUM_HAL_VSR_MIN, "Invalid vector");
521 CYG_ASSERT( vector <= CYGNUM_HAL_VSR_MAX, "Invalid vector");
523 HAL_VSR_GET( vector, vsr );
528 // -------------------------------------------------------------------------
529 // Install a vector service routine
532 Cyg_Interrupt::set_vsr(cyg_vector vector, cyg_VSR *vsr, cyg_VSR **old)
534 CYG_REPORT_FUNCTION();
536 CYG_REPORT_FUNCARG3( "vector = %d, new vsr is at %08x, mem to put "
537 "old VSR in is at %08x", vector, vsr, old);
539 CYG_INSTRUMENT_INTR(SET_VSR, vector, vsr);
541 CYG_ASSERT( vector >= CYGNUM_HAL_VSR_MIN, "Invalid vector");
542 CYG_ASSERT( vector <= CYGNUM_HAL_VSR_MAX, "Invalid vector");
544 CYG_INTERRUPT_STATE old_ints;
546 HAL_DISABLE_INTERRUPTS(old_ints);
548 HAL_VSR_SET( vector, vsr, old );
550 HAL_RESTORE_INTERRUPTS(old_ints);
555 // -------------------------------------------------------------------------
556 // Disable interrupts at the CPU
560 Cyg_Interrupt::disable_interrupts(void)
562 CYG_REPORT_FUNCTION();
564 CYG_INSTRUMENT_INTR(DISABLE, disable_counter[CYG_KERNEL_CPU_THIS()]+1, 0);
566 HAL_SMP_CPU_TYPE cpu_this = CYG_KERNEL_CPU_THIS();
568 // If the disable_counter is zero, disable interrupts and claim the spinlock.
570 if( 0 == disable_counter[cpu_this] )
572 // Claim the spinlock and disable interrupts. We save the original interrupt
573 // enable state to restore later.
574 interrupt_disable_spinlock.spin_intsave(&interrupt_disable_state[cpu_this]);
577 // Now increment our disable counter.
579 disable_counter[cpu_this]++;
585 // -------------------------------------------------------------------------
586 // Re-enable CPU interrupts
589 Cyg_Interrupt::enable_interrupts(void)
591 CYG_REPORT_FUNCTION();
593 CYG_INSTRUMENT_INTR(ENABLE, disable_counter[CYG_KERNEL_CPU_THIS()], 0);
595 HAL_SMP_CPU_TYPE cpu_this = CYG_KERNEL_CPU_THIS();
597 CYG_ASSERT( disable_counter[cpu_this] > 0 , "Disable counter not greater than zero");
599 // If the disable counter goes to zero, then release the spinlock and restore
600 // the previous interrupt state.
602 if( --disable_counter[cpu_this] == 0 )
604 interrupt_disable_spinlock.clear_intsave(interrupt_disable_state[cpu_this]);
610 // -------------------------------------------------------------------------
611 // Mask a specific interrupt in a PIC
614 Cyg_Interrupt::mask_interrupt(cyg_vector vector)
616 CYG_REPORT_FUNCTION();
617 CYG_REPORT_FUNCARG1("vector=%d", vector);
619 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
620 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
622 CYG_INSTRUMENT_INTR(MASK, vector, 0);
624 CYG_INTERRUPT_STATE old_ints;
626 HAL_DISABLE_INTERRUPTS(old_ints);
627 HAL_INTERRUPT_MASK( vector );
628 HAL_RESTORE_INTERRUPTS(old_ints);
633 // -------------------------------------------------------------------------
634 // Mask a specific interrupt in a PIC (but not interrupt safe)
637 Cyg_Interrupt::mask_interrupt_intunsafe(cyg_vector vector)
639 CYG_REPORT_FUNCTION();
640 CYG_REPORT_FUNCARG1("vector=%d", vector);
643 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
644 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
646 CYG_INSTRUMENT_INTR(MASK, vector, 0);
648 HAL_INTERRUPT_MASK( vector );
653 // -------------------------------------------------------------------------
657 Cyg_Interrupt::unmask_interrupt(cyg_vector vector)
659 CYG_REPORT_FUNCTION();
661 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
662 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
664 CYG_INSTRUMENT_INTR(UNMASK, vector, 0);
666 CYG_INTERRUPT_STATE old_ints;
668 HAL_DISABLE_INTERRUPTS(old_ints);
669 HAL_INTERRUPT_UNMASK( vector );
670 HAL_RESTORE_INTERRUPTS(old_ints);
676 // -------------------------------------------------------------------------
677 // Clear PIC mask (but not interrupt safe)
680 Cyg_Interrupt::unmask_interrupt_intunsafe(cyg_vector vector)
682 CYG_REPORT_FUNCTION();
684 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
685 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
687 CYG_INSTRUMENT_INTR(UNMASK, vector, 0);
689 HAL_INTERRUPT_UNMASK( vector );
695 // -------------------------------------------------------------------------
696 // Acknowledge interrupt at PIC
699 Cyg_Interrupt::acknowledge_interrupt(cyg_vector vector)
701 // CYG_REPORT_FUNCTION();
703 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
704 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
706 CYG_INSTRUMENT_INTR(ACK, vector, 0);
708 HAL_INTERRUPT_ACKNOWLEDGE( vector );
711 // -------------------------------------------------------------------------
712 // Change interrupt detection at PIC
715 Cyg_Interrupt::configure_interrupt(
716 cyg_vector vector, // vector to control
717 cyg_bool level, // level or edge triggered
718 cyg_bool up // hi/lo level, rising/falling edge
721 CYG_REPORT_FUNCTION();
722 CYG_REPORT_FUNCARG3("vector = %d, level = %d, up = %d", vector, level,
725 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
726 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
728 CYG_INSTRUMENT_INTR(CONFIGURE, vector, (level<<1)|up);
730 HAL_INTERRUPT_CONFIGURE( vector, level, up );
735 // -------------------------------------------------------------------------
736 // SMP support for setting/getting interrupt CPU
738 #ifdef CYGPKG_KERNEL_SMP_SUPPORT
741 Cyg_Interrupt::set_cpu(
742 cyg_vector vector, // vector to control
743 HAL_SMP_CPU_TYPE cpu // CPU to set
746 CYG_REPORT_FUNCTION();
747 CYG_REPORT_FUNCARG2("vector = %d, cpu = %d", vector, cpu );
749 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
750 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
752 CYG_INSTRUMENT_INTR(SET_CPU, vector, cpu);
754 HAL_INTERRUPT_SET_CPU( vector, cpu );
760 Cyg_Interrupt::get_cpu(
761 cyg_vector vector // vector to control
764 CYG_REPORT_FUNCTION();
765 CYG_REPORT_FUNCARG1("vector = %d", vector);
767 CYG_ASSERT( vector >= CYGNUM_HAL_ISR_MIN, "Invalid vector");
768 CYG_ASSERT( vector <= CYGNUM_HAL_ISR_MAX, "Invalid vector");
770 HAL_SMP_CPU_TYPE cpu = 0;
772 HAL_INTERRUPT_GET_CPU( vector, cpu );
774 CYG_INSTRUMENT_INTR(GET_CPU, vector, cpu);
783 // -------------------------------------------------------------------------