unified MX27, MX25, MX37 trees

[karo-tx-redboot.git] / packages / hal / arm / mx37 / var / v2_0 / include / hal_var_ints.h

diff --git a/packages/hal/arm/mx37/var/v2_0/include/hal_var_ints.h b/packages/hal/arm/mx37/var/v2_0/include/hal_var_ints.h
index 98bbe3b38acb9c21a641cb407a7913e71ac1f7ab..2648ccd31162c4e4b940b39b3d31e06da5dd58f2 100644 (file)
--- a/packages/hal/arm/mx37/var/v2_0/include/hal_var_ints.h
+++ b/packages/hal/arm/mx37/var/v2_0/include/hal_var_ints.h
@@ -74,30 +74,30 @@
 // end up clumped into interrupt signal #11.  Using the symbols
 // below allow for detection of these separately.
 
-#define CYGNUM_HAL_INTERRUPT_GPIO11  (32+11)
-#define CYGNUM_HAL_INTERRUPT_GPIO12  (32+12)
-#define CYGNUM_HAL_INTERRUPT_GPIO13  (32+13)
-#define CYGNUM_HAL_INTERRUPT_GPIO14  (32+14)
-#define CYGNUM_HAL_INTERRUPT_GPIO15  (32+15)
-#define CYGNUM_HAL_INTERRUPT_GPIO16  (32+16)
-#define CYGNUM_HAL_INTERRUPT_GPIO17  (32+17)
-#define CYGNUM_HAL_INTERRUPT_GPIO18  (32+18)
-#define CYGNUM_HAL_INTERRUPT_GPIO19  (32+19)
-#define CYGNUM_HAL_INTERRUPT_GPIO20  (32+20)
-#define CYGNUM_HAL_INTERRUPT_GPIO21  (32+21)
-#define CYGNUM_HAL_INTERRUPT_GPIO22  (32+22)
-#define CYGNUM_HAL_INTERRUPT_GPIO23  (32+23)
-#define CYGNUM_HAL_INTERRUPT_GPIO24  (32+24)
-#define CYGNUM_HAL_INTERRUPT_GPIO25  (32+25)
-#define CYGNUM_HAL_INTERRUPT_GPIO26  (32+26)
-#define CYGNUM_HAL_INTERRUPT_GPIO27  (32+27)
+#define CYGNUM_HAL_INTERRUPT_GPIO11  (32 + 11)
+#define CYGNUM_HAL_INTERRUPT_GPIO12  (32 + 12)
+#define CYGNUM_HAL_INTERRUPT_GPIO13  (32 + 13)
+#define CYGNUM_HAL_INTERRUPT_GPIO14  (32 + 14)
+#define CYGNUM_HAL_INTERRUPT_GPIO15  (32 + 15)
+#define CYGNUM_HAL_INTERRUPT_GPIO16  (32 + 16)
+#define CYGNUM_HAL_INTERRUPT_GPIO17  (32 + 17)
+#define CYGNUM_HAL_INTERRUPT_GPIO18  (32 + 18)
+#define CYGNUM_HAL_INTERRUPT_GPIO19  (32 + 19)
+#define CYGNUM_HAL_INTERRUPT_GPIO20  (32 + 20)
+#define CYGNUM_HAL_INTERRUPT_GPIO21  (32 + 21)
+#define CYGNUM_HAL_INTERRUPT_GPIO22  (32 + 22)
+#define CYGNUM_HAL_INTERRUPT_GPIO23  (32 + 23)
+#define CYGNUM_HAL_INTERRUPT_GPIO24  (32 + 24)
+#define CYGNUM_HAL_INTERRUPT_GPIO25  (32 + 25)
+#define CYGNUM_HAL_INTERRUPT_GPIO26  (32 + 26)
+#define CYGNUM_HAL_INTERRUPT_GPIO27  (32 + 27)
 
 #define CYGNUM_HAL_INTERRUPT_NONE    -1
 
 #define CYGNUM_HAL_ISR_MIN            0
-#define CYGNUM_HAL_ISR_MAX           (27+32)
+#define CYGNUM_HAL_ISR_MAX           (27 + 32)
 
-#define CYGNUM_HAL_ISR_COUNT         (CYGNUM_HAL_ISR_MAX+1)
+#define CYGNUM_HAL_ISR_COUNT         (CYGNUM_HAL_ISR_MAX + 1)
 
 // The vector used by the Real time clock
 #define CYGNUM_HAL_INTERRUPT_RTC     CYGNUM_HAL_INTERRUPT_TIMER0
@@ -108,18 +108,25 @@
 // method for reading clock interrupt latency
 #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
 externC void hal_clock_latency(cyg_uint32 *);
-# define HAL_CLOCK_LATENCY( _pvalue_ ) \
-         hal_clock_latency( (cyg_uint32 *)(_pvalue_) )
+#define HAL_CLOCK_LATENCY(_pvalue_) \
+                hal_clock_latency((cyg_uint32 *)(_pvalue_))
 #endif
 
 //----------------------------------------------------------------------------
 // Reset.
-#define HAL_PLATFORM_RESET()                                        \
-        CYG_MACRO_START                                             \
-                *(volatile unsigned short *)WDOG_BASE_ADDR |= 0x4;  \
-                /* hang here forever if reset fails */              \
-                while (1){}                                         \
-        CYG_MACRO_END
+#define HAL_PLATFORM_RESET()                                   \
+       CYG_MACRO_START                                                         \
+               cyg_uint32 srsr;                                                \
+               cyg_uint16 wcr;                                                 \
+               /* clear all reset flags */                             \
+               HAL_READ_UINT32(SRC_SRSR_REG, srsr);    \
+               HAL_WRITE_UINT32(SRC_SRSR_REG, srsr);   \
+               HAL_READ_UINT16(WDOG_WCR_REG, wcr);             \
+               wcr &= ~(1 << 4);                                               \
+               HAL_WRITE_UINT16(WDOG_WCR_REG, wcr);    \
+               /* hang here forever if reset fails */  \
+               while (1) {}                                                    \
+       CYG_MACRO_END
 
 // Fallback (never really used)
 #define HAL_PLATFORM_RESET_ENTRY 0x00000000