+# ifdef CYGSEM_KERNEL_INTERRUPTS_DSRS_LIST_FIFO
+
+ cyg_uint32 old_intr;
+ HAL_DISABLE_INTERRUPTS(old_intr);
+ Cyg_Interrupt* intr = dsr_list[cpu];
+ CYG_ASSERT(intr != 0, "No DSRs are pended");
+ dsr_list[cpu] = 0;
+ dsr_list_tail[cpu] = 0;
+ while(true)
+ {
+ cyg_count32 count = intr->dsr_count;
+ Cyg_Interrupt* next = intr->next_dsr;
+ intr->dsr_count = 0;
+ intr->next_dsr = 0;
+ HAL_RESTORE_INTERRUPTS(old_intr);
+
+ CYG_ASSERT(intr->dsr != 0, "No DSR defined");
+ CYG_ASSERT(count > 0, "DSR posted but post count is zero");
+ intr->dsr(intr->vector, count, (CYG_ADDRWORD)intr->data);
+
+ if (!next)
+ break;
+
+ intr = next;
+ HAL_DISABLE_INTERRUPTS(old_intr);
+ }
+
+# else // ! defined CYGSEM_KERNEL_INTERRUPTS_DSRS_LIST_FIFO
+