2 * Freescale i.MX28 Boot PMIC init
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/imx-regs.h>
17 #ifdef CONFIG_SYS_MXS_VDD5V_ONLY
18 #define DCDC4P2_DROPOUT_CONFIG POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
19 POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2
21 #define DCDC4P2_DROPOUT_CONFIG POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
22 POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL
24 #ifdef CONFIG_SYS_SPL_VDDD_VAL
25 #define VDDD_VAL CONFIG_SYS_SPL_VDDD_VAL
29 #ifdef CONFIG_SYS_SPL_VDDIO_VAL
30 #define VDDIO_VAL CONFIG_SYS_SPL_VDDIO_VAL
32 #define VDDIO_VAL 3300
34 #ifdef CONFIG_SYS_SPL_VDDA_VAL
35 #define VDDA_VAL CONFIG_SYS_SPL_VDDA_VAL
39 #ifdef CONFIG_SYS_SPL_VDDMEM_VAL
40 #define VDDMEM_VAL CONFIG_SYS_SPL_VDDMEM_VAL
42 #define VDDMEM_VAL 1700
45 #ifdef CONFIG_SYS_SPL_VDDD_BO_VAL
46 #define VDDD_BO_VAL CONFIG_SYS_SPL_VDDD_BO_VAL
48 #define VDDD_BO_VAL 150
50 #ifdef CONFIG_SYS_SPL_VDDIO_BO_VAL
51 #define VDDIO_BO_VAL CONFIG_SYS_SPL_VDDIO_BO_VAL
53 #define VDDIO_BO_VAL 150
55 #ifdef CONFIG_SYS_SPL_VDDA_BO_VAL
56 #define VDDA_BO_VAL CONFIG_SYS_SPL_VDDA_BO_VAL
58 #define VDDA_BO_VAL 175
60 #ifdef CONFIG_SYS_SPL_VDDMEM_BO_VAL
61 #define VDDMEM_BO_VAL CONFIG_SYS_SPL_VDDMEM_BO_VAL
63 #define VDDMEM_BO_VAL 25
66 #ifdef CONFIG_SYS_SPL_BATT_BO_LEVEL
67 #if CONFIG_SYS_SPL_BATT_BO_LEVEL < 2400 || CONFIG_SYS_SPL_BATT_BO_LEVEL > 3640
68 #error CONFIG_SYS_SPL_BATT_BO_LEVEL out of range
70 #define BATT_BO_VAL (((CONFIG_SYS_SPL_BATT_BO_LEVEL) - 2400) / 40)
72 /* Brownout default at 3V */
73 #define BATT_BO_VAL ((3000 - 2400) / 40)
76 #ifdef CONFIG_SYS_SPL_FIXED_BATT_SUPPLY
77 static const int fixed_batt_supply = 1;
79 static const int fixed_batt_supply;
82 static struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
85 * mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL
87 * This function switches the CPU core clock from PLL to 24MHz XTAL
88 * oscilator. This is necessary if the PLL is being reconfigured to
89 * prevent crash of the CPU core.
91 static void mxs_power_clock2xtal(void)
93 struct mxs_clkctrl_regs *clkctrl_regs =
94 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
96 debug("SPL: Switching CPU clock to 24MHz XTAL\n");
98 /* Set XTAL as CPU reference clock */
99 writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
100 &clkctrl_regs->hw_clkctrl_clkseq_set);
104 * mxs_power_clock2pll() - Switch CPU core clock source to PLL
106 * This function switches the CPU core clock from 24MHz XTAL oscilator
107 * to PLL. This can only be called once the PLL has re-locked and once
108 * the PLL is stable after reconfiguration.
110 static void mxs_power_clock2pll(void)
112 struct mxs_clkctrl_regs *clkctrl_regs =
113 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
115 debug("SPL: Switching CPU core clock source to PLL\n");
118 * TODO: Are we really? It looks like we turn on PLL0, but we then
119 * set the CLKCTRL_CLKSEQ_BYPASS_CPU bit of the (which was already
120 * set by mxs_power_clock2xtal()). Clearing this bit here seems to
121 * introduce some instability (causing the CPU core to hang). Maybe
122 * we aren't giving PLL0 enough time to stabilise?
124 writel(CLKCTRL_PLL0CTRL0_POWER,
125 &clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
129 * TODO: Should the PLL0 FORCE_LOCK bit be set here followed be a
130 * wait on the PLL0 LOCK bit?
132 writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
133 &clkctrl_regs->hw_clkctrl_clkseq_clr);
136 static int mxs_power_wait_rtc_stat(u32 mask)
138 int timeout = 5000; /* 3 ms according to i.MX28 Ref. Manual */
140 struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
142 while ((val = readl(&rtc_regs->hw_rtc_stat)) & mask) {
147 return !!(readl(&rtc_regs->hw_rtc_stat) & mask);
151 * mxs_power_set_auto_restart() - Set the auto-restart bit
153 * This function ungates the RTC block and sets the AUTO_RESTART
154 * bit to work around a design bug on MX28EVK Rev. A .
156 static int mxs_power_set_auto_restart(int on)
158 struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
160 debug("SPL: Setting auto-restart bit\n");
162 if (mxs_power_wait_rtc_stat(RTC_STAT_STALE_REGS_PERSISTENT0))
165 /* Do nothing if flag already set */
166 if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
169 if ((!(readl(&rtc_regs->hw_rtc_persistent0) &
170 RTC_PERSISTENT0_AUTO_RESTART) ^ !on) == 0)
173 if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
176 clrsetbits_le32(&rtc_regs->hw_rtc_persistent0,
177 !on * RTC_PERSISTENT0_AUTO_RESTART,
178 !!on * RTC_PERSISTENT0_AUTO_RESTART);
179 if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
186 * mxs_power_set_linreg() - Set linear regulators 25mV below DC-DC converter
188 * This function configures the VDDIO, VDDA and VDDD linear regulators output
189 * to be 25mV below the VDDIO, VDDA and VDDD output from the DC-DC switching
190 * converter. This is the recommended setting for the case where we use both
191 * linear regulators and DC-DC converter to power the VDDIO rail.
193 static void mxs_power_set_linreg(void)
195 /* Set linear regulator 25mV below switching converter */
196 debug("SPL: Setting VDDD 25mV below DC-DC converters\n");
197 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
198 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
199 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
201 debug("SPL: Setting VDDA 25mV below DC-DC converters\n");
202 clrsetbits_le32(&power_regs->hw_power_vddactrl,
203 POWER_VDDACTRL_LINREG_OFFSET_MASK,
204 POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
206 debug("SPL: Setting VDDIO 25mV below DC-DC converters\n");
207 clrsetbits_le32(&power_regs->hw_power_vddioctrl,
208 POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
209 POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
213 * mxs_get_batt_volt() - Measure battery input voltage
215 * This function retrieves the battery input voltage and returns it.
217 static int mxs_get_batt_volt(void)
219 uint32_t volt = readl(&power_regs->hw_power_battmonitor);
221 volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
222 volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
225 debug("SPL: Battery Voltage = %dmV\n", volt);
230 * mxs_is_batt_ready() - Test if the battery provides enough voltage to boot
232 * This function checks if the battery input voltage is higher than 3.6V and
233 * therefore allows the system to successfully boot using this power source.
235 static int mxs_is_batt_ready(void)
237 return (mxs_get_batt_volt() >= 3600);
241 * mxs_is_batt_good() - Test if battery is operational at all
243 * This function starts recharging the battery and tests if the input current
244 * provided by the 5V input recharging the battery is also sufficient to power
245 * the DC-DC converter.
247 static int mxs_is_batt_good(void)
249 uint32_t volt = mxs_get_batt_volt();
251 if ((volt >= 2400) && (volt <= 4300)) {
252 debug("SPL: Battery is good\n");
256 clrsetbits_le32(&power_regs->hw_power_5vctrl,
257 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
258 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
259 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
260 &power_regs->hw_power_5vctrl_clr);
262 clrsetbits_le32(&power_regs->hw_power_charge,
263 POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
264 POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
266 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
267 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
268 &power_regs->hw_power_5vctrl_clr);
272 volt = mxs_get_batt_volt();
275 debug("SPL: Battery Voltage too high\n");
280 debug("SPL: Battery is good\n");
284 writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
285 &power_regs->hw_power_charge_clr);
286 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
294 debug("SPL: Battery Voltage too low\n");
299 * mxs_power_setup_5v_detect() - Start the 5V input detection comparator
301 * This function enables the 5V detection comparator and sets the 5V valid
302 * threshold to 4.4V . We use 4.4V threshold here to make sure that even
303 * under high load, the voltage drop on the 5V input won't be so critical
304 * to cause undervolt on the 4P2 linear regulator supplying the DC-DC
305 * converter and thus making the system crash.
307 static void mxs_power_setup_5v_detect(void)
309 /* Start 5V detection */
310 debug("SPL: Starting 5V input detection comparator\n");
311 clrsetbits_le32(&power_regs->hw_power_5vctrl,
312 POWER_5VCTRL_VBUSVALID_TRSH_MASK,
313 POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
314 POWER_5VCTRL_PWRUP_VBUS_CMPS);
318 * mxs_src_power_init() - Preconfigure the power block
320 * This function configures reasonable values for the DC-DC control loop
321 * and battery monitor.
323 static void mxs_src_power_init(void)
325 debug("SPL: Pre-Configuring power block\n");
327 /* Improve efficieny and reduce transient ripple */
328 writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
329 POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
331 clrsetbits_le32(&power_regs->hw_power_dclimits,
332 POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
333 0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
335 if (!fixed_batt_supply) {
336 /* FIXME: This requires the LRADC to be set up! */
337 setbits_le32(&power_regs->hw_power_battmonitor,
338 POWER_BATTMONITOR_EN_BATADJ);
340 clrbits_le32(&power_regs->hw_power_battmonitor,
341 POWER_BATTMONITOR_EN_BATADJ);
344 /* Increase the RCSCALE level for quick DCDC response to dynamic load */
345 clrsetbits_le32(&power_regs->hw_power_loopctrl,
346 POWER_LOOPCTRL_EN_RCSCALE_MASK,
347 POWER_LOOPCTRL_RCSCALE_THRESH |
348 POWER_LOOPCTRL_EN_RCSCALE_8X);
350 clrsetbits_le32(&power_regs->hw_power_minpwr,
351 POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
353 if (!fixed_batt_supply) {
354 /* 5V to battery handoff ... FIXME */
355 writel(POWER_5VCTRL_DCDC_XFER,
356 &power_regs->hw_power_5vctrl_set);
358 writel(POWER_5VCTRL_DCDC_XFER,
359 &power_regs->hw_power_5vctrl_clr);
364 * mxs_power_init_4p2_params() - Configure the parameters of the 4P2 regulator
366 * This function configures the necessary parameters for the 4P2 linear
367 * regulator to supply the DC-DC converter from 5V input.
369 static void mxs_power_init_4p2_params(void)
371 debug("SPL: Configuring common 4P2 regulator params\n");
373 /* Setup 4P2 parameters */
374 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
375 POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
376 POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET));
378 clrsetbits_le32(&power_regs->hw_power_5vctrl,
379 POWER_5VCTRL_HEADROOM_ADJ_MASK,
380 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
382 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
383 POWER_DCDC4P2_DROPOUT_CTRL_MASK,
384 DCDC4P2_DROPOUT_CONFIG);
386 clrsetbits_le32(&power_regs->hw_power_5vctrl,
387 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
388 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
392 * mxs_enable_4p2_dcdc_input() - Enable or disable the DCDC input from 4P2
393 * @xfer: Select if the input shall be enabled or disabled
395 * This function enables or disables the 4P2 input into the DC-DC converter.
397 static void mxs_enable_4p2_dcdc_input(int xfer)
399 uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
400 uint32_t prev_5v_brnout, prev_5v_droop;
402 debug("SPL: %s 4P2 DC-DC Input\n", xfer ? "Enabling" : "Disabling");
404 if (xfer && (readl(&power_regs->hw_power_5vctrl) &
405 POWER_5VCTRL_ENABLE_DCDC)) {
409 prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
410 POWER_5VCTRL_PWDN_5VBRNOUT;
411 prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
412 POWER_CTRL_ENIRQ_VDD5V_DROOP;
414 writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_clr);
415 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
416 &power_regs->hw_power_reset);
418 writel(POWER_CTRL_ENIRQ_VDD5V_DROOP, &power_regs->hw_power_ctrl_clr);
421 * Recording orignal values that will be modified temporarlily
422 * to handle a chip bug. See chip errata for CQ ENGR00115837
424 tmp = readl(&power_regs->hw_power_5vctrl);
425 vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
426 vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
428 pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
431 * Disable mechanisms that get erroneously tripped by when setting
432 * the DCDC4P2 EN_DCDC
434 writel(POWER_5VCTRL_VBUSVALID_5VDETECT |
435 POWER_5VCTRL_VBUSVALID_TRSH_MASK,
436 &power_regs->hw_power_5vctrl);
438 writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
441 writel(POWER_5VCTRL_DCDC_XFER,
442 &power_regs->hw_power_5vctrl);
444 writel(POWER_5VCTRL_DCDC_XFER,
445 &power_regs->hw_power_5vctrl_clr);
447 writel(POWER_5VCTRL_ENABLE_DCDC,
448 &power_regs->hw_power_5vctrl_set);
450 writel(POWER_DCDC4P2_ENABLE_DCDC,
451 &power_regs->hw_power_dcdc4p2);
456 clrsetbits_le32(&power_regs->hw_power_5vctrl,
457 POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
460 writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
463 writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_clr);
465 while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
466 writel(POWER_CTRL_VBUS_VALID_IRQ,
467 &power_regs->hw_power_ctrl_clr);
469 if (prev_5v_brnout) {
470 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
471 &power_regs->hw_power_5vctrl_set);
472 writel(POWER_RESET_UNLOCK_KEY,
473 &power_regs->hw_power_reset);
475 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
476 &power_regs->hw_power_5vctrl_clr);
477 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
478 &power_regs->hw_power_reset);
481 while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
482 writel(POWER_CTRL_VDD5V_DROOP_IRQ,
483 &power_regs->hw_power_ctrl_clr);
486 writel(POWER_CTRL_ENIRQ_VDD5V_DROOP,
487 &power_regs->hw_power_ctrl_set);
489 writel(POWER_CTRL_ENIRQ_VDD5V_DROOP,
490 &power_regs->hw_power_ctrl_clr);
494 * mxs_power_init_4p2_regulator() - Start the 4P2 regulator
496 * This function enables the 4P2 regulator and switches the DC-DC converter
497 * to use the 4P2 input.
499 static void mxs_power_init_4p2_regulator(void)
503 debug("SPL: Enabling 4P2 regulator\n");
505 setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
507 writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
509 writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
510 &power_regs->hw_power_5vctrl_clr);
511 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
513 /* Power up the 4p2 rail and logic/control */
514 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
515 &power_regs->hw_power_5vctrl_clr);
518 * Start charging up the 4p2 capacitor. We ramp of this charge
519 * gradually to avoid large inrush current from the 5V cable which can
520 * cause transients/problems
522 debug("SPL: Charging 4P2 capacitor\n");
523 mxs_enable_4p2_dcdc_input(0);
525 if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
527 * If we arrived here, we were unable to recover from mx23 chip
528 * errata 5837. 4P2 is disabled and sufficient battery power is
529 * not present. Exiting to not enable DCDC power during 5V
532 clrbits_le32(&power_regs->hw_power_dcdc4p2,
533 POWER_DCDC4P2_ENABLE_DCDC);
534 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
535 &power_regs->hw_power_5vctrl_set);
537 debug("SPL: Unable to recover from mx23 errata 5837\n");
542 * Here we set the 4p2 brownout level to something very close to 4.2V.
543 * We then check the brownout status. If the brownout status is false,
544 * the voltage is already close to the target voltage of 4.2V so we
545 * can go ahead and set the 4P2 current limit to our max target limit.
546 * If the brownout status is true, we need to ramp up the current limit
547 * so that we don't cause large inrush current issues. We step up the
548 * current limit until the brownout status is false or until we've
549 * reached our maximum defined 4p2 current limit.
551 debug("SPL: Setting 4P2 brownout level\n");
552 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
553 POWER_DCDC4P2_BO_MASK,
554 22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
556 if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
557 writel(0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET,
558 &power_regs->hw_power_5vctrl_set);
560 tmp = (readl(&power_regs->hw_power_5vctrl) &
561 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
562 POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
564 if (!(readl(&power_regs->hw_power_sts) &
565 POWER_STS_DCDC_4P2_BO)) {
566 tmp = readl(&power_regs->hw_power_5vctrl);
567 tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
569 writel(tmp, &power_regs->hw_power_5vctrl);
573 tmp2 = readl(&power_regs->hw_power_5vctrl);
574 tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
576 POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
577 writel(tmp2, &power_regs->hw_power_5vctrl);
583 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
584 writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
588 * mxs_power_init_dcdc_4p2_source() - Switch DC-DC converter to 4P2 source
590 * This function configures the DC-DC converter to be supplied from the 4P2
593 static void mxs_power_init_dcdc_4p2_source(void)
595 debug("SPL: Switching DC-DC converters to 4P2\n");
597 if (!(readl(&power_regs->hw_power_dcdc4p2) &
598 POWER_DCDC4P2_ENABLE_DCDC)) {
599 debug("SPL: Already switched - aborting\n");
603 mxs_enable_4p2_dcdc_input(1);
605 if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
606 clrbits_le32(&power_regs->hw_power_dcdc4p2,
607 POWER_DCDC4P2_ENABLE_DCDC);
608 writel(POWER_5VCTRL_ENABLE_DCDC,
609 &power_regs->hw_power_5vctrl_clr);
610 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
611 &power_regs->hw_power_5vctrl_set);
616 * mxs_power_enable_4p2() - Power up the 4P2 regulator
618 * This function drives the process of powering up the 4P2 linear regulator
619 * and switching the DC-DC converter input over to the 4P2 linear regulator.
621 static void mxs_power_enable_4p2(void)
623 uint32_t vdddctrl, vddactrl, vddioctrl;
626 debug("SPL: Powering up 4P2 regulator\n");
628 vdddctrl = readl(&power_regs->hw_power_vdddctrl);
629 vddactrl = readl(&power_regs->hw_power_vddactrl);
630 vddioctrl = readl(&power_regs->hw_power_vddioctrl);
632 setbits_le32(&power_regs->hw_power_vdddctrl,
633 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
634 POWER_VDDDCTRL_PWDN_BRNOUT);
636 setbits_le32(&power_regs->hw_power_vddactrl,
637 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
638 POWER_VDDACTRL_PWDN_BRNOUT);
640 setbits_le32(&power_regs->hw_power_vddioctrl,
641 POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
643 mxs_power_init_4p2_params();
644 mxs_power_init_4p2_regulator();
646 /* Shutdown battery (none present) */
647 if (!mxs_is_batt_ready()) {
648 clrbits_le32(&power_regs->hw_power_dcdc4p2,
649 POWER_DCDC4P2_BO_MASK);
650 writel(POWER_CTRL_DCDC4P2_BO_IRQ,
651 &power_regs->hw_power_ctrl_clr);
652 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
653 &power_regs->hw_power_ctrl_clr);
656 mxs_power_init_dcdc_4p2_source();
658 writel(vdddctrl, &power_regs->hw_power_vdddctrl);
660 writel(vddactrl, &power_regs->hw_power_vddactrl);
662 writel(vddioctrl, &power_regs->hw_power_vddioctrl);
665 * Check if FET is enabled on either powerout and if so,
669 tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
670 POWER_VDDDCTRL_DISABLE_FET);
671 tmp |= !(readl(&power_regs->hw_power_vddactrl) &
672 POWER_VDDACTRL_DISABLE_FET);
673 tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
674 POWER_VDDIOCTRL_DISABLE_FET);
676 writel(POWER_CHARGE_ENABLE_LOAD,
677 &power_regs->hw_power_charge_clr);
679 debug("SPL: 4P2 regulator powered-up\n");
683 * mxs_boot_valid_5v() - Boot from 5V supply
685 * This function configures the power block to boot from valid 5V input.
686 * This is called only if the 5V is reliable and can properly supply the
687 * CPU. This function proceeds to configure the 4P2 converter to be supplied
690 static void mxs_boot_valid_5v(void)
692 debug("SPL: Booting from 5V supply\n");
695 * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
696 * disconnect event. FIXME
698 writel(POWER_5VCTRL_VBUSVALID_5VDETECT,
699 &power_regs->hw_power_5vctrl_set);
701 /* Configure polarity to check for 5V disconnection. */
702 writel(POWER_CTRL_POLARITY_VBUSVALID |
703 POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
704 &power_regs->hw_power_ctrl_clr);
706 writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
707 &power_regs->hw_power_ctrl_clr);
709 mxs_power_enable_4p2();
713 * mxs_powerdown() - Shut down the system
715 * This function powers down the CPU completely.
717 static void mxs_powerdown(void)
719 debug("Powering Down\n");
721 writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
722 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
723 &power_regs->hw_power_reset);
727 * mxs_batt_boot() - Configure the power block to boot from battery input
729 * This function configures the power block to boot from the battery voltage
732 static void mxs_batt_boot(void)
734 debug("SPL: Configuring power block to boot from battery\n");
736 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
737 &power_regs->hw_power_5vctrl_clr);
738 writel(POWER_5VCTRL_ENABLE_DCDC,
739 &power_regs->hw_power_5vctrl_clr);
741 clrbits_le32(&power_regs->hw_power_dcdc4p2,
742 POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2);
743 writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr);
745 /* 5V to battery handoff. */
746 writel(POWER_5VCTRL_DCDC_XFER, &power_regs->hw_power_5vctrl_set);
748 writel(POWER_5VCTRL_DCDC_XFER, &power_regs->hw_power_5vctrl_clr);
750 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
752 clrsetbits_le32(&power_regs->hw_power_minpwr,
753 POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
755 mxs_power_set_linreg();
757 clrbits_le32(&power_regs->hw_power_vdddctrl,
758 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
760 clrbits_le32(&power_regs->hw_power_vddactrl,
761 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG);
763 clrbits_le32(&power_regs->hw_power_vddioctrl,
764 POWER_VDDIOCTRL_DISABLE_FET);
766 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
767 &power_regs->hw_power_5vctrl_set);
769 writel(POWER_5VCTRL_ENABLE_DCDC, &power_regs->hw_power_5vctrl_set);
771 clrsetbits_le32(&power_regs->hw_power_5vctrl,
772 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
773 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
775 mxs_power_enable_4p2();
779 * mxs_handle_5v_conflict() - Test if the 5V input is reliable
781 * This function tests if the 5V input can reliably supply the system. If it
782 * can, then proceed to configuring the system to boot from 5V source, otherwise
783 * try booting from battery supply. If we can not boot from battery supply
784 * either, shut down the system.
786 static void mxs_handle_5v_conflict(void)
790 debug("SPL: Resolving 5V conflict\n");
792 setbits_le32(&power_regs->hw_power_vddioctrl,
793 POWER_VDDIOCTRL_BO_OFFSET_MASK);
796 tmp = readl(&power_regs->hw_power_sts);
798 if (tmp & POWER_STS_VDDIO_BO) {
800 * If VDDIO has a brownout, then the VDD5V_GT_VDDIO
803 debug("SPL: VDDIO has a brownout\n");
808 if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
809 debug("SPL: POWER_STS_VDD5V_GT_VDDIO is set\n");
813 debug("SPL: POWER_STS_VDD5V_GT_VDDIO is not set\n");
819 * TODO: I can't see this being reached. We'll either
820 * powerdown or boot from a stable 5V supply.
822 if (tmp & POWER_STS_PSWITCH_MASK) {
823 debug("SPL: POWER_STS_PSWITCH_MASK is set\n");
831 * mxs_5v_boot() - Configure the power block to boot from 5V input
833 * This function handles configuration of the power block when supplied by
836 static void mxs_5v_boot(void)
838 debug("SPL: Configuring power block to boot from 5V input\n");
841 * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
842 * but their implementation always returns 1 so we omit it here.
844 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
845 debug("SPL: 5V VDD good\n");
851 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
852 debug("SPL: 5V VDD good (after delay)\n");
857 debug("SPL: 5V VDD not good\n");
858 mxs_handle_5v_conflict();
861 static void mxs_fixed_batt_boot(void)
863 writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
865 writel(POWER_5VCTRL_ENABLE_DCDC |
866 POWER_5VCTRL_ILIMIT_EQ_ZERO |
867 POWER_5VCTRL_PWDN_5VBRNOUT |
868 POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
869 &power_regs->hw_power_5vctrl_set);
871 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
873 clrbits_le32(&power_regs->hw_power_vdddctrl,
874 POWER_VDDDCTRL_DISABLE_FET |
875 POWER_VDDDCTRL_ENABLE_LINREG |
876 POWER_VDDDCTRL_DISABLE_STEPPING);
878 clrbits_le32(&power_regs->hw_power_vddactrl,
879 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
880 POWER_VDDACTRL_DISABLE_STEPPING);
882 clrbits_le32(&power_regs->hw_power_vddioctrl,
883 POWER_VDDIOCTRL_DISABLE_FET |
884 POWER_VDDIOCTRL_DISABLE_STEPPING);
886 /* Stop 5V detection */
887 writel(POWER_5VCTRL_PWRUP_VBUS_CMPS,
888 &power_regs->hw_power_5vctrl_clr);
892 * mxs_init_batt_bo() - Configure battery brownout threshold
894 * This function configures the battery input brownout threshold. The value
895 * at which the battery brownout happens is configured to 3.0V in the code.
897 static void mxs_init_batt_bo(void)
899 debug("SPL: Initialising battery brown-out level to 3.0V\n");
902 clrsetbits_le32(&power_regs->hw_power_battmonitor,
903 POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
904 BATT_BO_VAL << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
906 writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
907 writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
911 * mxs_switch_vddd_to_dcdc_source() - Switch VDDD rail to DC-DC converter
913 * This function turns off the VDDD linear regulator and therefore makes
914 * the VDDD rail be supplied only by the DC-DC converter.
916 static void mxs_switch_vddd_to_dcdc_source(void)
918 debug("SPL: Switching VDDD to DC-DC converters\n");
920 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
921 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
922 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
924 clrbits_le32(&power_regs->hw_power_vdddctrl,
925 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
926 POWER_VDDDCTRL_DISABLE_STEPPING);
930 * mxs_power_configure_power_source() - Configure power block source
932 * This function is the core of the power configuration logic. The function
933 * selects the power block input source and configures the whole power block
934 * accordingly. After the configuration is complete and the system is stable
935 * again, the function switches the CPU clock source back to PLL. Finally,
936 * the function switches the voltage rails to DC-DC converter.
938 static void mxs_power_configure_power_source(void)
940 struct mxs_lradc_regs *lradc_regs =
941 (struct mxs_lradc_regs *)MXS_LRADC_BASE;
943 debug("SPL: Configuring power source\n");
945 mxs_src_power_init();
947 if (!fixed_batt_supply) {
948 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
949 if (mxs_is_batt_ready()) {
950 /* 5V source detected, good battery detected. */
953 if (!mxs_is_batt_good()) {
954 /* 5V source detected, bad battery detected. */
955 writel(LRADC_CONVERSION_AUTOMATIC,
956 &lradc_regs->hw_lradc_conversion_clr);
957 clrbits_le32(&power_regs->hw_power_battmonitor,
958 POWER_BATTMONITOR_BATT_VAL_MASK);
963 /* 5V not detected, booting from battery. */
967 mxs_fixed_batt_boot();
971 * TODO: Do not switch CPU clock to PLL if we are VDD5V is sourced
974 mxs_power_clock2pll();
978 mxs_switch_vddd_to_dcdc_source();
980 #ifdef CONFIG_SOC_MX23
981 /* Fire up the VDDMEM LinReg now that we're all set. */
982 debug("SPL: Enabling mx23 VDDMEM linear regulator\n");
983 writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
984 &power_regs->hw_power_vddmemctrl);
989 * mxs_enable_output_rail_protection() - Enable power rail protection
991 * This function enables overload protection on the power rails. This is
992 * triggered if the power rails' voltage drops rapidly due to overload and
993 * in such case, the supply to the powerrail is cut-off, protecting the
994 * CPU from damage. Note that under such condition, the system will likely
995 * crash or misbehave.
997 static void mxs_enable_output_rail_protection(void)
999 debug("SPL: Enabling output rail protection\n");
1001 writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
1002 POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
1004 setbits_le32(&power_regs->hw_power_vdddctrl,
1005 POWER_VDDDCTRL_PWDN_BRNOUT);
1007 setbits_le32(&power_regs->hw_power_vddactrl,
1008 POWER_VDDACTRL_PWDN_BRNOUT);
1010 setbits_le32(&power_regs->hw_power_vddioctrl,
1011 POWER_VDDIOCTRL_PWDN_BRNOUT);
1015 * mxs_get_vddio_power_source_off() - Get VDDIO rail power source
1017 * This function tests if the VDDIO rail is supplied by linear regulator
1018 * or by the DC-DC converter. Returns 1 if powered by linear regulator,
1019 * returns 0 if powered by the DC-DC converter.
1021 static int mxs_get_vddio_power_source_off(void)
1025 if ((readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) &&
1026 !(readl(&power_regs->hw_power_5vctrl) &
1027 POWER_5VCTRL_ILIMIT_EQ_ZERO)) {
1029 tmp = readl(&power_regs->hw_power_vddioctrl);
1030 if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
1031 if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
1032 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
1037 if (!(readl(&power_regs->hw_power_5vctrl) &
1038 POWER_5VCTRL_ENABLE_DCDC)) {
1039 if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
1040 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
1050 * mxs_get_vddd_power_source_off() - Get VDDD rail power source
1052 * This function tests if the VDDD rail is supplied by linear regulator
1053 * or by the DC-DC converter. Returns 1 if powered by linear regulator,
1054 * returns 0 if powered by the DC-DC converter.
1056 static int mxs_get_vddd_power_source_off(void)
1060 tmp = readl(&power_regs->hw_power_vdddctrl);
1061 if (tmp & POWER_VDDDCTRL_DISABLE_FET) {
1062 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
1063 POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
1068 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
1069 if (!(readl(&power_regs->hw_power_5vctrl) &
1070 POWER_5VCTRL_ENABLE_DCDC)) {
1075 if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) {
1076 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
1077 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) {
1085 static int mxs_get_vdda_power_source_off(void)
1089 tmp = readl(&power_regs->hw_power_vddactrl);
1090 if (tmp & POWER_VDDACTRL_DISABLE_FET) {
1091 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
1092 POWER_VDDACTRL_LINREG_OFFSET_0STEPS) {
1097 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
1098 if (!(readl(&power_regs->hw_power_5vctrl) &
1099 POWER_5VCTRL_ENABLE_DCDC)) {
1104 if (!(tmp & POWER_VDDACTRL_ENABLE_LINREG)) {
1105 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
1106 POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW) {
1114 struct mxs_vddx_cfg {
1118 uint16_t highest_mV;
1119 int (*powered_by_linreg)(void);
1123 uint32_t bo_offset_mask;
1124 uint32_t bo_offset_offset;
1129 #define POWER_REG(n) &((struct mxs_power_regs *)MXS_POWER_BASE)->n
1131 static const struct mxs_vddx_cfg mxs_vddio_cfg = {
1132 .reg = POWER_REG(hw_power_vddioctrl),
1133 #if defined(CONFIG_SOC_MX23)
1140 .powered_by_linreg = mxs_get_vddio_power_source_off,
1141 .trg_mask = POWER_VDDIOCTRL_TRG_MASK,
1142 .bo_irq = POWER_CTRL_VDDIO_BO_IRQ,
1143 .bo_enirq = POWER_CTRL_ENIRQ_VDDIO_BO,
1144 .bo_offset_mask = POWER_VDDIOCTRL_BO_OFFSET_MASK,
1145 .bo_offset_offset = POWER_VDDIOCTRL_BO_OFFSET_OFFSET,
1150 static const struct mxs_vddx_cfg mxs_vddd_cfg = {
1151 .reg = POWER_REG(hw_power_vdddctrl),
1155 .powered_by_linreg = mxs_get_vddd_power_source_off,
1156 .trg_mask = POWER_VDDDCTRL_TRG_MASK,
1157 .bo_irq = POWER_CTRL_VDDD_BO_IRQ,
1158 .bo_enirq = POWER_CTRL_ENIRQ_VDDD_BO,
1159 .bo_offset_mask = POWER_VDDDCTRL_BO_OFFSET_MASK,
1160 .bo_offset_offset = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
1165 static const struct mxs_vddx_cfg mxs_vdda_cfg = {
1166 .reg = POWER_REG(hw_power_vddactrl),
1170 .powered_by_linreg = mxs_get_vdda_power_source_off,
1171 .trg_mask = POWER_VDDACTRL_TRG_MASK,
1172 .bo_irq = POWER_CTRL_VDDA_BO_IRQ,
1173 .bo_enirq = POWER_CTRL_ENIRQ_VDDA_BO,
1174 .bo_offset_mask = POWER_VDDACTRL_BO_OFFSET_MASK,
1175 .bo_offset_offset = POWER_VDDACTRL_BO_OFFSET_OFFSET,
1180 #ifdef CONFIG_SOC_MX23
1181 static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
1182 .reg = POWER_REG(hw_power_vddmemctrl),
1186 .powered_by_linreg = NULL,
1187 .trg_mask = POWER_VDDMEMCTRL_TRG_MASK,
1190 .bo_offset_mask = 0,
1191 .bo_offset_offset = 0,
1196 * mxs_power_set_vddx() - Configure voltage on DC-DC converter rail
1197 * @cfg: Configuration data of the DC-DC converter rail
1198 * @new_target: New target voltage of the DC-DC converter rail
1199 * @new_brownout: New brownout trigger voltage
1201 * This function configures the output voltage on the DC-DC converter rail.
1202 * The rail is selected by the @cfg argument. The new voltage target is
1203 * selected by the @new_target and the voltage is specified in mV. The
1204 * new brownout value is selected by the @new_brownout argument and the
1205 * value is also in mV.
1207 static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
1208 uint32_t new_target, uint32_t bo_offset)
1210 uint32_t cur_target, diff, bo_int = 0;
1211 int powered_by_linreg = 0;
1214 if (new_target < cfg->lowest_mV) {
1215 new_target = cfg->lowest_mV;
1217 if (new_target > cfg->highest_mV) {
1218 new_target = cfg->highest_mV;
1221 if (new_target - bo_offset < cfg->bo_min_mV) {
1222 bo_offset = new_target - cfg->bo_min_mV;
1223 } else if (new_target - bo_offset > cfg->bo_max_mV) {
1224 bo_offset = new_target - cfg->bo_max_mV;
1227 bo_offset = DIV_ROUND_CLOSEST(bo_offset, cfg->step_mV);
1229 cur_target = readl(cfg->reg);
1230 cur_target &= cfg->trg_mask;
1231 cur_target *= cfg->step_mV;
1232 cur_target += cfg->lowest_mV;
1234 adjust_up = new_target > cur_target;
1235 if (cfg->powered_by_linreg)
1236 powered_by_linreg = cfg->powered_by_linreg();
1238 if (adjust_up && cfg->bo_irq) {
1239 if (powered_by_linreg) {
1240 bo_int = readl(&power_regs->hw_power_ctrl);
1241 writel(cfg->bo_enirq, &power_regs->hw_power_ctrl_clr);
1243 setbits_le32(cfg->reg, cfg->bo_offset_mask);
1247 if (abs(new_target - cur_target) > 100) {
1249 diff = cur_target + 100;
1251 diff = cur_target - 100;
1256 diff -= cfg->lowest_mV;
1257 diff /= cfg->step_mV;
1259 clrsetbits_le32(cfg->reg, cfg->trg_mask, diff);
1261 if (powered_by_linreg ||
1262 (readl(&power_regs->hw_power_sts) &
1263 POWER_STS_VDD5V_GT_VDDIO)) {
1266 while (!(readl(&power_regs->hw_power_sts) &
1272 cur_target = readl(cfg->reg);
1273 cur_target &= cfg->trg_mask;
1274 cur_target *= cfg->step_mV;
1275 cur_target += cfg->lowest_mV;
1276 } while (new_target > cur_target);
1279 if (adjust_up && powered_by_linreg) {
1280 writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
1281 if (bo_int & cfg->bo_enirq)
1282 writel(cfg->bo_enirq,
1283 &power_regs->hw_power_ctrl_set);
1286 clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
1287 bo_offset << cfg->bo_offset_offset);
1292 * mxs_setup_batt_detect() - Start the battery voltage measurement logic
1294 * This function starts and configures the LRADC block. This allows the
1295 * power initialization code to measure battery voltage and based on this
1296 * knowledge, decide whether to boot at all, boot from battery or boot
1299 static void mxs_setup_batt_detect(void)
1301 debug("SPL: Starting battery voltage measurement logic\n");
1304 mxs_lradc_enable_batt_measurement();
1309 * mxs_ungate_power() - Ungate the POWER block
1311 * This function ungates clock to the power block. In case the power block
1312 * was still gated at this point, it will not be possible to configure the
1313 * block and therefore the power initialization would fail. This function
1314 * is only needed on i.MX233, on i.MX28 the power block is always ungated.
1316 static void mxs_ungate_power(void)
1318 #ifdef CONFIG_SOC_MX23
1319 writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr);
1323 #ifdef CONFIG_CONFIG_MACH_MX28EVK
1324 #define auto_restart 1
1326 #define auto_restart 0
1330 * mxs_power_init() - The power block init main function
1332 * This function calls all the power block initialization functions in
1333 * proper sequence to start the power block.
1335 #define VDDX_VAL(v) (v) / 1000, (v) / 100 % 10
1337 void mxs_power_init(void)
1339 debug("SPL: Initialising Power Block\n");
1343 mxs_power_clock2xtal();
1344 if (mxs_power_set_auto_restart(auto_restart)) {
1345 serial_puts("Inconsistent value in RTC_PERSISTENT0 register; power-on-reset required\n");
1347 mxs_power_set_linreg();
1349 if (!fixed_batt_supply) {
1350 mxs_power_setup_5v_detect();
1351 mxs_setup_batt_detect();
1354 mxs_power_configure_power_source();
1355 mxs_enable_output_rail_protection();
1357 debug("SPL: Setting VDDIO to %uV%u (brownout @ %uv%02u)\n",
1358 VDDX_VAL(VDDIO_VAL), VDDX_VAL(VDDIO_VAL - VDDIO_BO_VAL));
1359 mxs_power_set_vddx(&mxs_vddio_cfg, VDDIO_VAL, VDDIO_BO_VAL);
1360 debug("SPL: Setting VDDD to %uV%u (brownout @ %uv%02u)\n",
1361 VDDX_VAL(VDDD_VAL), VDDX_VAL(VDDD_VAL - VDDD_BO_VAL));
1362 mxs_power_set_vddx(&mxs_vddd_cfg, VDDD_VAL, VDDD_BO_VAL);
1363 debug("SPL: Setting VDDA to %uV%u (brownout @ %uv%02u)\n",
1364 VDDX_VAL(VDDA_VAL), VDDX_VAL(VDDA_VAL - VDDA_BO_VAL));
1365 mxs_power_set_vddx(&mxs_vdda_cfg, VDDA_VAL, VDDA_BO_VAL);
1366 #ifdef CONFIG_SOC_MX23
1367 debug("SPL: Setting VDDMEM to %uV%u (brownout @ %uv%02u)\n",
1368 VDDX_VAL(VDDMEM_VAL), VDDX_VAL(VDDMEM_VAL - VDDMEM_BO_VAL));
1369 mxs_power_set_vddx(&mxs_vddmem_cfg, VDDMEM_VAL, VDDMEM_BO_VAL);
1371 clrbits_le32(&power_regs->hw_power_vddmemctrl,
1372 POWER_VDDMEMCTRL_ENABLE_LINREG);
1374 writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
1375 POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
1376 POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
1377 POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
1378 if (!fixed_batt_supply)
1379 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
1380 &power_regs->hw_power_5vctrl_set);
1383 #ifdef CONFIG_SPL_MXS_PSWITCH_WAIT
1385 * mxs_power_wait_pswitch() - Wait for power switch to be pressed
1387 * This function waits until the power-switch was pressed to start booting
1390 void mxs_power_wait_pswitch(void)
1392 debug("SPL: Waiting for power switch input\n");
1393 while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))