2 * Freescale i.MX28 Boot PMIC init
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/imx-regs.h>
17 #ifdef CONFIG_SYS_SPL_VDDD_VAL
18 #define VDDD_VAL CONFIG_SYS_SPL_VDDD_VAL
22 #ifdef CONFIG_SYS_SPL_VDDIO_VAL
23 #define VDDIO_VAL CONFIG_SYS_SPL_VDDIO_VAL
25 #define VDDIO_VAL 3300
27 #ifdef CONFIG_SYS_SPL_VDDA_VAL
28 #define VDDA_VAL CONFIG_SYS_SPL_VDDA_VAL
32 #ifdef CONFIG_SYS_SPL_VDDMEM_VAL
33 #define VDDMEM_VAL CONFIG_SYS_SPL_VDDMEM_VAL
35 #define VDDMEM_VAL 1700
38 #ifdef CONFIG_SYS_SPL_VDDD_BO_VAL
39 #define VDDD_BO_VAL CONFIG_SYS_SPL_VDDD_BO_VAL
41 #define VDDD_BO_VAL 150
43 #ifdef CONFIG_SYS_SPL_VDDIO_BO_VAL
44 #define VDDIO_BO_VAL CONFIG_SYS_SPL_VDDIO_BO_VAL
46 #define VDDIO_BO_VAL 150
48 #ifdef CONFIG_SYS_SPL_VDDA_BO_VAL
49 #define VDDA_BO_VAL CONFIG_SYS_SPL_VDDA_BO_VAL
51 #define VDDA_BO_VAL 175
53 #ifdef CONFIG_SYS_SPL_VDDMEM_BO_VAL
54 #define VDDMEM_BO_VAL CONFIG_SYS_SPL_VDDMEM_BO_VAL
56 #define VDDMEM_BO_VAL 25
59 #ifdef CONFIG_SYS_SPL_BATT_BO_LEVEL
60 #if CONFIG_SYS_SPL_BATT_BO_LEVEL < 2400 || CONFIG_SYS_SPL_BATT_BO_LEVEL > 3640
61 #error CONFIG_SYS_SPL_BATT_BO_LEVEL out of range
63 #define BATT_BO_VAL (((CONFIG_SYS_SPL_BATT_BO_LEVEL) - 2400) / 40)
65 /* Brownout default at 3V */
66 #define BATT_BO_VAL ((3000 - 2400) / 40)
69 #ifdef CONFIG_SYS_SPL_FIXED_BATT_SUPPLY
70 static const int fixed_batt_supply = 1;
72 static const int fixed_batt_supply;
75 static struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
78 * mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL
80 * This function switches the CPU core clock from PLL to 24MHz XTAL
81 * oscilator. This is necessary if the PLL is being reconfigured to
82 * prevent crash of the CPU core.
84 static void mxs_power_clock2xtal(void)
86 struct mxs_clkctrl_regs *clkctrl_regs =
87 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
89 debug("SPL: Switching CPU clock to 24MHz XTAL\n");
91 /* Set XTAL as CPU reference clock */
92 writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
93 &clkctrl_regs->hw_clkctrl_clkseq_set);
97 * mxs_power_clock2pll() - Switch CPU core clock source to PLL
99 * This function switches the CPU core clock from 24MHz XTAL oscilator
100 * to PLL. This can only be called once the PLL has re-locked and once
101 * the PLL is stable after reconfiguration.
103 static void mxs_power_clock2pll(void)
105 struct mxs_clkctrl_regs *clkctrl_regs =
106 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
108 debug("SPL: Switching CPU core clock source to PLL\n");
111 * TODO: Are we really? It looks like we turn on PLL0, but we then
112 * set the CLKCTRL_CLKSEQ_BYPASS_CPU bit of the (which was already
113 * set by mxs_power_clock2xtal()). Clearing this bit here seems to
114 * introduce some instability (causing the CPU core to hang). Maybe
115 * we aren't giving PLL0 enough time to stabilise?
117 setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
118 CLKCTRL_PLL0CTRL0_POWER);
122 * TODO: Should the PLL0 FORCE_LOCK bit be set here followed be a
123 * wait on the PLL0 LOCK bit?
125 setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
126 CLKCTRL_CLKSEQ_BYPASS_CPU);
129 static int mxs_power_wait_rtc_stat(u32 mask)
131 int timeout = 5000; /* 3 ms according to i.MX28 Ref. Manual */
133 struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
135 while ((val = readl(&rtc_regs->hw_rtc_stat)) & mask) {
140 return !!(readl(&rtc_regs->hw_rtc_stat) & mask);
144 * mxs_power_set_auto_restart() - Set the auto-restart bit
146 * This function ungates the RTC block and sets the AUTO_RESTART
147 * bit to work around a design bug on MX28EVK Rev. A .
149 static int mxs_power_set_auto_restart(int on)
151 struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
153 debug("SPL: Setting auto-restart bit\n");
155 if (mxs_power_wait_rtc_stat(RTC_STAT_STALE_REGS_PERSISTENT0))
158 /* Do nothing if flag already set */
159 if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
162 if ((!(readl(&rtc_regs->hw_rtc_persistent0) &
163 RTC_PERSISTENT0_AUTO_RESTART) ^ !on) == 0)
166 if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
169 clrsetbits_le32(&rtc_regs->hw_rtc_persistent0,
170 !on * RTC_PERSISTENT0_AUTO_RESTART,
171 !!on * RTC_PERSISTENT0_AUTO_RESTART);
172 if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
179 * mxs_power_set_linreg() - Set linear regulators 25mV below DC-DC converter
181 * This function configures the VDDIO, VDDA and VDDD linear regulators output
182 * to be 25mV below the VDDIO, VDDA and VDDD output from the DC-DC switching
183 * converter. This is the recommended setting for the case where we use both
184 * linear regulators and DC-DC converter to power the VDDIO rail.
186 static void mxs_power_set_linreg(void)
188 /* Set linear regulator 25mV below switching converter */
189 debug("SPL: Setting VDDD 25mV below DC-DC converters\n");
190 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
191 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
192 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
194 debug("SPL: Setting VDDA 25mV below DC-DC converters\n");
195 clrsetbits_le32(&power_regs->hw_power_vddactrl,
196 POWER_VDDACTRL_LINREG_OFFSET_MASK,
197 POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
199 debug("SPL: Setting VDDIO 25mV below DC-DC converters\n");
200 clrsetbits_le32(&power_regs->hw_power_vddioctrl,
201 POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
202 POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
206 * mxs_get_batt_volt() - Measure battery input voltage
208 * This function retrieves the battery input voltage and returns it.
210 static int mxs_get_batt_volt(void)
212 uint32_t volt = readl(&power_regs->hw_power_battmonitor);
214 volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
215 volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
218 debug("SPL: Battery Voltage = %dmV\n", volt);
223 * mxs_is_batt_ready() - Test if the battery provides enough voltage to boot
225 * This function checks if the battery input voltage is higher than 3.6V and
226 * therefore allows the system to successfully boot using this power source.
228 static int mxs_is_batt_ready(void)
230 return (mxs_get_batt_volt() >= 3600);
234 * mxs_is_batt_good() - Test if battery is operational at all
236 * This function starts recharging the battery and tests if the input current
237 * provided by the 5V input recharging the battery is also sufficient to power
238 * the DC-DC converter.
240 static int mxs_is_batt_good(void)
242 uint32_t volt = mxs_get_batt_volt();
244 if ((volt >= 2400) && (volt <= 4300)) {
245 debug("SPL: Battery is good\n");
249 clrsetbits_le32(&power_regs->hw_power_5vctrl,
250 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
251 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
252 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
253 &power_regs->hw_power_5vctrl_clr);
255 clrsetbits_le32(&power_regs->hw_power_charge,
256 POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
257 POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
259 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
260 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
261 &power_regs->hw_power_5vctrl_clr);
265 volt = mxs_get_batt_volt();
268 debug("SPL: Battery Voltage too high\n");
273 debug("SPL: Battery is good\n");
277 writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
278 &power_regs->hw_power_charge_clr);
279 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
287 debug("SPL: Battery Voltage too low\n");
292 * mxs_power_setup_5v_detect() - Start the 5V input detection comparator
294 * This function enables the 5V detection comparator and sets the 5V valid
295 * threshold to 4.4V . We use 4.4V threshold here to make sure that even
296 * under high load, the voltage drop on the 5V input won't be so critical
297 * to cause undervolt on the 4P2 linear regulator supplying the DC-DC
298 * converter and thus making the system crash.
300 static void mxs_power_setup_5v_detect(void)
302 /* Start 5V detection */
303 debug("SPL: Starting 5V input detection comparator\n");
304 clrsetbits_le32(&power_regs->hw_power_5vctrl,
305 POWER_5VCTRL_VBUSVALID_TRSH_MASK,
306 POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
307 POWER_5VCTRL_PWRUP_VBUS_CMPS);
311 * mxs_src_power_init() - Preconfigure the power block
313 * This function configures reasonable values for the DC-DC control loop
314 * and battery monitor.
316 static void mxs_src_power_init(void)
318 debug("SPL: Pre-Configuring power block\n");
320 /* Improve efficieny and reduce transient ripple */
321 writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
322 POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
324 clrsetbits_le32(&power_regs->hw_power_dclimits,
325 POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
326 0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
328 if (!fixed_batt_supply) {
329 /* FIXME: This requires the LRADC to be set up! */
330 setbits_le32(&power_regs->hw_power_battmonitor,
331 POWER_BATTMONITOR_EN_BATADJ);
333 clrbits_le32(&power_regs->hw_power_battmonitor,
334 POWER_BATTMONITOR_EN_BATADJ);
337 /* Increase the RCSCALE level for quick DCDC response to dynamic load */
338 clrsetbits_le32(&power_regs->hw_power_loopctrl,
339 POWER_LOOPCTRL_EN_RCSCALE_MASK,
340 POWER_LOOPCTRL_RCSCALE_THRESH |
341 POWER_LOOPCTRL_EN_RCSCALE_8X);
343 clrsetbits_le32(&power_regs->hw_power_minpwr,
344 POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
346 if (!fixed_batt_supply) {
347 /* 5V to battery handoff ... FIXME */
348 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
350 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
355 * mxs_power_init_4p2_params() - Configure the parameters of the 4P2 regulator
357 * This function configures the necessary parameters for the 4P2 linear
358 * regulator to supply the DC-DC converter from 5V input.
360 static void mxs_power_init_4p2_params(void)
362 debug("SPL: Configuring common 4P2 regulator params\n");
364 /* Setup 4P2 parameters */
365 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
366 POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
367 POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET));
369 clrsetbits_le32(&power_regs->hw_power_5vctrl,
370 POWER_5VCTRL_HEADROOM_ADJ_MASK,
371 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
373 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
374 POWER_DCDC4P2_DROPOUT_CTRL_MASK,
375 POWER_DCDC4P2_DROPOUT_CTRL_100MV |
376 POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL);
378 clrsetbits_le32(&power_regs->hw_power_5vctrl,
379 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
380 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
384 * mxs_enable_4p2_dcdc_input() - Enable or disable the DCDC input from 4P2
385 * @xfer: Select if the input shall be enabled or disabled
387 * This function enables or disables the 4P2 input into the DC-DC converter.
389 static void mxs_enable_4p2_dcdc_input(int xfer)
391 uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
392 uint32_t prev_5v_brnout, prev_5v_droop;
394 debug("SPL: %s 4P2 DC-DC Input\n", xfer ? "Enabling" : "Disabling");
396 prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
397 POWER_5VCTRL_PWDN_5VBRNOUT;
398 prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
399 POWER_CTRL_ENIRQ_VDD5V_DROOP;
401 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
402 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
403 &power_regs->hw_power_reset);
405 clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
407 if (xfer && (readl(&power_regs->hw_power_5vctrl) &
408 POWER_5VCTRL_ENABLE_DCDC)) {
413 * Recording orignal values that will be modified temporarlily
414 * to handle a chip bug. See chip errata for CQ ENGR00115837
416 tmp = readl(&power_regs->hw_power_5vctrl);
417 vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
418 vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
420 pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
423 * Disable mechanisms that get erroneously tripped by when setting
424 * the DCDC4P2 EN_DCDC
426 clrbits_le32(&power_regs->hw_power_5vctrl,
427 POWER_5VCTRL_VBUSVALID_5VDETECT |
428 POWER_5VCTRL_VBUSVALID_TRSH_MASK);
430 writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
433 setbits_le32(&power_regs->hw_power_5vctrl,
434 POWER_5VCTRL_DCDC_XFER);
436 clrbits_le32(&power_regs->hw_power_5vctrl,
437 POWER_5VCTRL_DCDC_XFER);
439 setbits_le32(&power_regs->hw_power_5vctrl,
440 POWER_5VCTRL_ENABLE_DCDC);
442 setbits_le32(&power_regs->hw_power_dcdc4p2,
443 POWER_DCDC4P2_ENABLE_DCDC);
448 clrsetbits_le32(&power_regs->hw_power_5vctrl,
449 POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
452 writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
455 clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
457 while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
458 writel(POWER_CTRL_VBUS_VALID_IRQ,
459 &power_regs->hw_power_ctrl_clr);
461 if (prev_5v_brnout) {
462 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
463 &power_regs->hw_power_5vctrl_set);
464 writel(POWER_RESET_UNLOCK_KEY,
465 &power_regs->hw_power_reset);
467 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
468 &power_regs->hw_power_5vctrl_clr);
469 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
470 &power_regs->hw_power_reset);
473 while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
474 writel(POWER_CTRL_VDD5V_DROOP_IRQ,
475 &power_regs->hw_power_ctrl_clr);
478 clrbits_le32(&power_regs->hw_power_ctrl,
479 POWER_CTRL_ENIRQ_VDD5V_DROOP);
481 setbits_le32(&power_regs->hw_power_ctrl,
482 POWER_CTRL_ENIRQ_VDD5V_DROOP);
486 * mxs_power_init_4p2_regulator() - Start the 4P2 regulator
488 * This function enables the 4P2 regulator and switches the DC-DC converter
489 * to use the 4P2 input.
491 static void mxs_power_init_4p2_regulator(void)
495 debug("SPL: Enabling 4P2 regulator\n");
497 setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
499 writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
501 writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
502 &power_regs->hw_power_5vctrl_clr);
503 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
505 /* Power up the 4p2 rail and logic/control */
506 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
507 &power_regs->hw_power_5vctrl_clr);
510 * Start charging up the 4p2 capacitor. We ramp of this charge
511 * gradually to avoid large inrush current from the 5V cable which can
512 * cause transients/problems
514 debug("SPL: Charging 4P2 capacitor\n");
515 mxs_enable_4p2_dcdc_input(0);
517 if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
519 * If we arrived here, we were unable to recover from mx23 chip
520 * errata 5837. 4P2 is disabled and sufficient battery power is
521 * not present. Exiting to not enable DCDC power during 5V
524 clrbits_le32(&power_regs->hw_power_dcdc4p2,
525 POWER_DCDC4P2_ENABLE_DCDC);
526 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
527 &power_regs->hw_power_5vctrl_set);
529 debug("SPL: Unable to recover from mx23 errata 5837\n");
534 * Here we set the 4p2 brownout level to something very close to 4.2V.
535 * We then check the brownout status. If the brownout status is false,
536 * the voltage is already close to the target voltage of 4.2V so we
537 * can go ahead and set the 4P2 current limit to our max target limit.
538 * If the brownout status is true, we need to ramp up the current limit
539 * so that we don't cause large inrush current issues. We step up the
540 * current limit until the brownout status is false or until we've
541 * reached our maximum defined 4p2 current limit.
543 debug("SPL: Setting 4P2 brownout level\n");
544 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
545 POWER_DCDC4P2_BO_MASK,
546 22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
548 if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
549 setbits_le32(&power_regs->hw_power_5vctrl,
550 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
552 tmp = (readl(&power_regs->hw_power_5vctrl) &
553 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
554 POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
556 if (!(readl(&power_regs->hw_power_sts) &
557 POWER_STS_DCDC_4P2_BO)) {
558 tmp = readl(&power_regs->hw_power_5vctrl);
559 tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
561 writel(tmp, &power_regs->hw_power_5vctrl);
565 tmp2 = readl(&power_regs->hw_power_5vctrl);
566 tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
568 POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
569 writel(tmp2, &power_regs->hw_power_5vctrl);
575 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
576 writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
580 * mxs_power_init_dcdc_4p2_source() - Switch DC-DC converter to 4P2 source
582 * This function configures the DC-DC converter to be supplied from the 4P2
585 static void mxs_power_init_dcdc_4p2_source(void)
587 debug("SPL: Switching DC-DC converters to 4P2\n");
589 if (!(readl(&power_regs->hw_power_dcdc4p2) &
590 POWER_DCDC4P2_ENABLE_DCDC)) {
591 debug("SPL: Already switched - aborting\n");
595 mxs_enable_4p2_dcdc_input(1);
597 if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
598 clrbits_le32(&power_regs->hw_power_dcdc4p2,
599 POWER_DCDC4P2_ENABLE_DCDC);
600 writel(POWER_5VCTRL_ENABLE_DCDC,
601 &power_regs->hw_power_5vctrl_clr);
602 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
603 &power_regs->hw_power_5vctrl_set);
608 * mxs_power_enable_4p2() - Power up the 4P2 regulator
610 * This function drives the process of powering up the 4P2 linear regulator
611 * and switching the DC-DC converter input over to the 4P2 linear regulator.
613 static void mxs_power_enable_4p2(void)
615 uint32_t vdddctrl, vddactrl, vddioctrl;
618 debug("SPL: Powering up 4P2 regulator\n");
620 vdddctrl = readl(&power_regs->hw_power_vdddctrl);
621 vddactrl = readl(&power_regs->hw_power_vddactrl);
622 vddioctrl = readl(&power_regs->hw_power_vddioctrl);
624 setbits_le32(&power_regs->hw_power_vdddctrl,
625 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
626 POWER_VDDDCTRL_PWDN_BRNOUT);
628 setbits_le32(&power_regs->hw_power_vddactrl,
629 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
630 POWER_VDDACTRL_PWDN_BRNOUT);
632 setbits_le32(&power_regs->hw_power_vddioctrl,
633 POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
635 mxs_power_init_4p2_params();
636 mxs_power_init_4p2_regulator();
638 /* Shutdown battery (none present) */
639 if (!mxs_is_batt_ready()) {
640 clrbits_le32(&power_regs->hw_power_dcdc4p2,
641 POWER_DCDC4P2_BO_MASK);
642 writel(POWER_CTRL_DCDC4P2_BO_IRQ,
643 &power_regs->hw_power_ctrl_clr);
644 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
645 &power_regs->hw_power_ctrl_clr);
648 mxs_power_init_dcdc_4p2_source();
650 writel(vdddctrl, &power_regs->hw_power_vdddctrl);
652 writel(vddactrl, &power_regs->hw_power_vddactrl);
654 writel(vddioctrl, &power_regs->hw_power_vddioctrl);
657 * Check if FET is enabled on either powerout and if so,
661 tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
662 POWER_VDDDCTRL_DISABLE_FET);
663 tmp |= !(readl(&power_regs->hw_power_vddactrl) &
664 POWER_VDDACTRL_DISABLE_FET);
665 tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
666 POWER_VDDIOCTRL_DISABLE_FET);
668 writel(POWER_CHARGE_ENABLE_LOAD,
669 &power_regs->hw_power_charge_clr);
671 debug("SPL: 4P2 regulator powered-up\n");
675 * mxs_boot_valid_5v() - Boot from 5V supply
677 * This function configures the power block to boot from valid 5V input.
678 * This is called only if the 5V is reliable and can properly supply the
679 * CPU. This function proceeds to configure the 4P2 converter to be supplied
682 static void mxs_boot_valid_5v(void)
684 debug("SPL: Booting from 5V supply\n");
687 * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
688 * disconnect event. FIXME
690 writel(POWER_5VCTRL_VBUSVALID_5VDETECT,
691 &power_regs->hw_power_5vctrl_set);
693 /* Configure polarity to check for 5V disconnection. */
694 writel(POWER_CTRL_POLARITY_VBUSVALID |
695 POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
696 &power_regs->hw_power_ctrl_clr);
698 writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
699 &power_regs->hw_power_ctrl_clr);
701 mxs_power_enable_4p2();
705 * mxs_powerdown() - Shut down the system
707 * This function powers down the CPU completely.
709 static void mxs_powerdown(void)
711 debug("Powering Down\n");
713 writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
714 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
715 &power_regs->hw_power_reset);
719 * mxs_batt_boot() - Configure the power block to boot from battery input
721 * This function configures the power block to boot from the battery voltage
724 static void mxs_batt_boot(void)
726 debug("SPL: Configuring power block to boot from battery\n");
728 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
729 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
731 clrbits_le32(&power_regs->hw_power_dcdc4p2,
732 POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2);
733 writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr);
735 /* 5V to battery handoff. */
736 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
738 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
740 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
742 clrsetbits_le32(&power_regs->hw_power_minpwr,
743 POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
745 mxs_power_set_linreg();
747 clrbits_le32(&power_regs->hw_power_vdddctrl,
748 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
750 clrbits_le32(&power_regs->hw_power_vddactrl,
751 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG);
753 clrbits_le32(&power_regs->hw_power_vddioctrl,
754 POWER_VDDIOCTRL_DISABLE_FET);
756 setbits_le32(&power_regs->hw_power_5vctrl,
757 POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
759 setbits_le32(&power_regs->hw_power_5vctrl,
760 POWER_5VCTRL_ENABLE_DCDC);
762 clrsetbits_le32(&power_regs->hw_power_5vctrl,
763 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
764 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
766 mxs_power_enable_4p2();
770 * mxs_handle_5v_conflict() - Test if the 5V input is reliable
772 * This function tests if the 5V input can reliably supply the system. If it
773 * can, then proceed to configuring the system to boot from 5V source, otherwise
774 * try booting from battery supply. If we can not boot from battery supply
775 * either, shut down the system.
777 static void mxs_handle_5v_conflict(void)
781 debug("SPL: Resolving 5V conflict\n");
783 setbits_le32(&power_regs->hw_power_vddioctrl,
784 POWER_VDDIOCTRL_BO_OFFSET_MASK);
787 tmp = readl(&power_regs->hw_power_sts);
789 if (tmp & POWER_STS_VDDIO_BO) {
791 * If VDDIO has a brownout, then the VDD5V_GT_VDDIO
794 debug("SPL: VDDIO has a brownout\n");
799 if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
800 debug("SPL: POWER_STS_VDD5V_GT_VDDIO is set\n");
804 debug("SPL: POWER_STS_VDD5V_GT_VDDIO is not set\n");
810 * TODO: I can't see this being reached. We'll either
811 * powerdown or boot from a stable 5V supply.
813 if (tmp & POWER_STS_PSWITCH_MASK) {
814 debug("SPL: POWER_STS_PSWITCH_MASK is set\n");
822 * mxs_5v_boot() - Configure the power block to boot from 5V input
824 * This function handles configuration of the power block when supplied by
827 static void mxs_5v_boot(void)
829 debug("SPL: Configuring power block to boot from 5V input\n");
832 * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
833 * but their implementation always returns 1 so we omit it here.
835 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
836 debug("SPL: 5V VDD good\n");
842 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
843 debug("SPL: 5V VDD good (after delay)\n");
848 debug("SPL: 5V VDD not good\n");
849 mxs_handle_5v_conflict();
852 static void mxs_fixed_batt_boot(void)
854 writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
856 setbits_le32(&power_regs->hw_power_5vctrl,
857 POWER_5VCTRL_ENABLE_DCDC |
858 POWER_5VCTRL_ILIMIT_EQ_ZERO |
859 POWER_5VCTRL_PWDN_5VBRNOUT |
860 POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
862 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
864 clrbits_le32(&power_regs->hw_power_vdddctrl,
865 POWER_VDDDCTRL_DISABLE_FET |
866 POWER_VDDDCTRL_ENABLE_LINREG |
867 POWER_VDDDCTRL_DISABLE_STEPPING);
869 clrbits_le32(&power_regs->hw_power_vddactrl,
870 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
871 POWER_VDDACTRL_DISABLE_STEPPING);
873 clrbits_le32(&power_regs->hw_power_vddioctrl,
874 POWER_VDDIOCTRL_DISABLE_FET |
875 POWER_VDDIOCTRL_DISABLE_STEPPING);
877 /* Stop 5V detection */
878 writel(POWER_5VCTRL_PWRUP_VBUS_CMPS,
879 &power_regs->hw_power_5vctrl_clr);
883 * mxs_init_batt_bo() - Configure battery brownout threshold
885 * This function configures the battery input brownout threshold. The value
886 * at which the battery brownout happens is configured to 3.0V in the code.
888 static void mxs_init_batt_bo(void)
890 debug("SPL: Initialising battery brown-out level to 3.0V\n");
893 clrsetbits_le32(&power_regs->hw_power_battmonitor,
894 POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
895 BATT_BO_VAL << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
897 writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
898 writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
902 * mxs_switch_vddd_to_dcdc_source() - Switch VDDD rail to DC-DC converter
904 * This function turns off the VDDD linear regulator and therefore makes
905 * the VDDD rail be supplied only by the DC-DC converter.
907 static void mxs_switch_vddd_to_dcdc_source(void)
909 debug("SPL: Switching VDDD to DC-DC converters\n");
911 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
912 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
913 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
915 clrbits_le32(&power_regs->hw_power_vdddctrl,
916 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
917 POWER_VDDDCTRL_DISABLE_STEPPING);
921 * mxs_power_configure_power_source() - Configure power block source
923 * This function is the core of the power configuration logic. The function
924 * selects the power block input source and configures the whole power block
925 * accordingly. After the configuration is complete and the system is stable
926 * again, the function switches the CPU clock source back to PLL. Finally,
927 * the function switches the voltage rails to DC-DC converter.
929 static void mxs_power_configure_power_source(void)
931 struct mxs_lradc_regs *lradc_regs =
932 (struct mxs_lradc_regs *)MXS_LRADC_BASE;
934 debug("SPL: Configuring power source\n");
936 mxs_src_power_init();
938 if (!fixed_batt_supply) {
939 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
940 if (mxs_is_batt_ready()) {
941 /* 5V source detected, good battery detected. */
944 if (!mxs_is_batt_good()) {
945 /* 5V source detected, bad battery detected. */
946 writel(LRADC_CONVERSION_AUTOMATIC,
947 &lradc_regs->hw_lradc_conversion_clr);
948 clrbits_le32(&power_regs->hw_power_battmonitor,
949 POWER_BATTMONITOR_BATT_VAL_MASK);
954 /* 5V not detected, booting from battery. */
958 mxs_fixed_batt_boot();
962 * TODO: Do not switch CPU clock to PLL if we are VDD5V is sourced
965 mxs_power_clock2pll();
969 mxs_switch_vddd_to_dcdc_source();
971 #ifdef CONFIG_SOC_MX23
972 /* Fire up the VDDMEM LinReg now that we're all set. */
973 debug("SPL: Enabling mx23 VDDMEM linear regulator\n");
974 writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
975 &power_regs->hw_power_vddmemctrl);
980 * mxs_enable_output_rail_protection() - Enable power rail protection
982 * This function enables overload protection on the power rails. This is
983 * triggered if the power rails' voltage drops rapidly due to overload and
984 * in such case, the supply to the powerrail is cut-off, protecting the
985 * CPU from damage. Note that under such condition, the system will likely
986 * crash or misbehave.
988 static void mxs_enable_output_rail_protection(void)
990 debug("SPL: Enabling output rail protection\n");
992 writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
993 POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
995 setbits_le32(&power_regs->hw_power_vdddctrl,
996 POWER_VDDDCTRL_PWDN_BRNOUT);
998 setbits_le32(&power_regs->hw_power_vddactrl,
999 POWER_VDDACTRL_PWDN_BRNOUT);
1001 setbits_le32(&power_regs->hw_power_vddioctrl,
1002 POWER_VDDIOCTRL_PWDN_BRNOUT);
1006 * mxs_get_vddio_power_source_off() - Get VDDIO rail power source
1008 * This function tests if the VDDIO rail is supplied by linear regulator
1009 * or by the DC-DC converter. Returns 1 if powered by linear regulator,
1010 * returns 0 if powered by the DC-DC converter.
1012 static int mxs_get_vddio_power_source_off(void)
1016 if ((readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) &&
1017 !(readl(&power_regs->hw_power_5vctrl) &
1018 POWER_5VCTRL_ILIMIT_EQ_ZERO)) {
1020 tmp = readl(&power_regs->hw_power_vddioctrl);
1021 if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
1022 if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
1023 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
1028 if (!(readl(&power_regs->hw_power_5vctrl) &
1029 POWER_5VCTRL_ENABLE_DCDC)) {
1030 if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
1031 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
1041 * mxs_get_vddd_power_source_off() - Get VDDD rail power source
1043 * This function tests if the VDDD rail is supplied by linear regulator
1044 * or by the DC-DC converter. Returns 1 if powered by linear regulator,
1045 * returns 0 if powered by the DC-DC converter.
1047 static int mxs_get_vddd_power_source_off(void)
1051 tmp = readl(&power_regs->hw_power_vdddctrl);
1052 if (tmp & POWER_VDDDCTRL_DISABLE_FET) {
1053 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
1054 POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
1059 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
1060 if (!(readl(&power_regs->hw_power_5vctrl) &
1061 POWER_5VCTRL_ENABLE_DCDC)) {
1066 if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) {
1067 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
1068 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) {
1076 static int mxs_get_vdda_power_source_off(void)
1080 tmp = readl(&power_regs->hw_power_vddactrl);
1081 if (tmp & POWER_VDDACTRL_DISABLE_FET) {
1082 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
1083 POWER_VDDACTRL_LINREG_OFFSET_0STEPS) {
1088 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
1089 if (!(readl(&power_regs->hw_power_5vctrl) &
1090 POWER_5VCTRL_ENABLE_DCDC)) {
1095 if (!(tmp & POWER_VDDACTRL_ENABLE_LINREG)) {
1096 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
1097 POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW) {
1105 struct mxs_vddx_cfg {
1109 uint16_t highest_mV;
1110 int (*powered_by_linreg)(void);
1114 uint32_t bo_offset_mask;
1115 uint32_t bo_offset_offset;
1120 #define POWER_REG(n) &((struct mxs_power_regs *)MXS_POWER_BASE)->n
1122 static const struct mxs_vddx_cfg mxs_vddio_cfg = {
1123 .reg = POWER_REG(hw_power_vddioctrl),
1124 #if defined(CONFIG_SOC_MX23)
1131 .powered_by_linreg = mxs_get_vddio_power_source_off,
1132 .trg_mask = POWER_VDDIOCTRL_TRG_MASK,
1133 .bo_irq = POWER_CTRL_VDDIO_BO_IRQ,
1134 .bo_enirq = POWER_CTRL_ENIRQ_VDDIO_BO,
1135 .bo_offset_mask = POWER_VDDIOCTRL_BO_OFFSET_MASK,
1136 .bo_offset_offset = POWER_VDDIOCTRL_BO_OFFSET_OFFSET,
1141 static const struct mxs_vddx_cfg mxs_vddd_cfg = {
1142 .reg = POWER_REG(hw_power_vdddctrl),
1146 .powered_by_linreg = mxs_get_vddd_power_source_off,
1147 .trg_mask = POWER_VDDDCTRL_TRG_MASK,
1148 .bo_irq = POWER_CTRL_VDDD_BO_IRQ,
1149 .bo_enirq = POWER_CTRL_ENIRQ_VDDD_BO,
1150 .bo_offset_mask = POWER_VDDDCTRL_BO_OFFSET_MASK,
1151 .bo_offset_offset = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
1156 static const struct mxs_vddx_cfg mxs_vdda_cfg = {
1157 .reg = POWER_REG(hw_power_vddactrl),
1161 .powered_by_linreg = mxs_get_vdda_power_source_off,
1162 .trg_mask = POWER_VDDACTRL_TRG_MASK,
1163 .bo_irq = POWER_CTRL_VDDA_BO_IRQ,
1164 .bo_enirq = POWER_CTRL_ENIRQ_VDDA_BO,
1165 .bo_offset_mask = POWER_VDDACTRL_BO_OFFSET_MASK,
1166 .bo_offset_offset = POWER_VDDACTRL_BO_OFFSET_OFFSET,
1171 #ifdef CONFIG_SOC_MX23
1172 static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
1173 .reg = POWER_REG(hw_power_vddmemctrl),
1177 .powered_by_linreg = NULL,
1178 .trg_mask = POWER_VDDMEMCTRL_TRG_MASK,
1181 .bo_offset_mask = 0,
1182 .bo_offset_offset = 0,
1187 * mxs_power_set_vddx() - Configure voltage on DC-DC converter rail
1188 * @cfg: Configuration data of the DC-DC converter rail
1189 * @new_target: New target voltage of the DC-DC converter rail
1190 * @new_brownout: New brownout trigger voltage
1192 * This function configures the output voltage on the DC-DC converter rail.
1193 * The rail is selected by the @cfg argument. The new voltage target is
1194 * selected by the @new_target and the voltage is specified in mV. The
1195 * new brownout value is selected by the @new_brownout argument and the
1196 * value is also in mV.
1198 static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
1199 uint32_t new_target, uint32_t bo_offset)
1201 uint32_t cur_target, diff, bo_int = 0;
1202 int powered_by_linreg = 0;
1205 if (new_target < cfg->lowest_mV) {
1206 new_target = cfg->lowest_mV;
1208 if (new_target > cfg->highest_mV) {
1209 new_target = cfg->highest_mV;
1212 if (new_target - bo_offset < cfg->bo_min_mV) {
1213 bo_offset = new_target - cfg->bo_min_mV;
1214 } else if (new_target - bo_offset > cfg->bo_max_mV) {
1215 bo_offset = new_target - cfg->bo_max_mV;
1218 bo_offset = DIV_ROUND_CLOSEST(bo_offset, cfg->step_mV);
1220 cur_target = readl(cfg->reg);
1221 cur_target &= cfg->trg_mask;
1222 cur_target *= cfg->step_mV;
1223 cur_target += cfg->lowest_mV;
1225 adjust_up = new_target > cur_target;
1226 if (cfg->powered_by_linreg)
1227 powered_by_linreg = cfg->powered_by_linreg();
1229 if (adjust_up && cfg->bo_irq) {
1230 if (powered_by_linreg) {
1231 bo_int = readl(&power_regs->hw_power_ctrl);
1232 writel(cfg->bo_enirq, &power_regs->hw_power_ctrl_clr);
1234 setbits_le32(cfg->reg, cfg->bo_offset_mask);
1238 if (abs(new_target - cur_target) > 100) {
1240 diff = cur_target + 100;
1242 diff = cur_target - 100;
1247 diff -= cfg->lowest_mV;
1248 diff /= cfg->step_mV;
1250 clrsetbits_le32(cfg->reg, cfg->trg_mask, diff);
1252 if (powered_by_linreg ||
1253 (readl(&power_regs->hw_power_sts) &
1254 POWER_STS_VDD5V_GT_VDDIO)) {
1257 while (!(readl(&power_regs->hw_power_sts) &
1263 cur_target = readl(cfg->reg);
1264 cur_target &= cfg->trg_mask;
1265 cur_target *= cfg->step_mV;
1266 cur_target += cfg->lowest_mV;
1267 } while (new_target > cur_target);
1270 if (adjust_up && powered_by_linreg) {
1271 writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
1272 if (bo_int & cfg->bo_enirq)
1273 writel(cfg->bo_enirq,
1274 &power_regs->hw_power_ctrl_set);
1277 clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
1278 bo_offset << cfg->bo_offset_offset);
1283 * mxs_setup_batt_detect() - Start the battery voltage measurement logic
1285 * This function starts and configures the LRADC block. This allows the
1286 * power initialization code to measure battery voltage and based on this
1287 * knowledge, decide whether to boot at all, boot from battery or boot
1290 static void mxs_setup_batt_detect(void)
1292 debug("SPL: Starting battery voltage measurement logic\n");
1295 mxs_lradc_enable_batt_measurement();
1300 * mxs_ungate_power() - Ungate the POWER block
1302 * This function ungates clock to the power block. In case the power block
1303 * was still gated at this point, it will not be possible to configure the
1304 * block and therefore the power initialization would fail. This function
1305 * is only needed on i.MX233, on i.MX28 the power block is always ungated.
1307 static void mxs_ungate_power(void)
1309 #ifdef CONFIG_SOC_MX23
1310 writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr);
1314 #ifdef CONFIG_CONFIG_MACH_MX28EVK
1315 #define auto_restart 1
1317 #define auto_restart 0
1321 * mxs_power_init() - The power block init main function
1323 * This function calls all the power block initialization functions in
1324 * proper sequence to start the power block.
1326 #define VDDX_VAL(v) (v) / 1000, (v) / 100 % 10
1328 void mxs_power_init(void)
1330 debug("SPL: Initialising Power Block\n");
1334 mxs_power_clock2xtal();
1335 if (mxs_power_set_auto_restart(auto_restart)) {
1336 serial_puts("Inconsistent value in RTC_PERSISTENT0 register; power-on-reset required\n");
1338 mxs_power_set_linreg();
1340 if (!fixed_batt_supply) {
1341 mxs_power_setup_5v_detect();
1342 mxs_setup_batt_detect();
1345 mxs_power_configure_power_source();
1346 mxs_enable_output_rail_protection();
1348 debug("SPL: Setting VDDIO to %uV%u (brownout @ %uv%02u)\n",
1349 VDDX_VAL(VDDIO_VAL), VDDX_VAL(VDDIO_VAL - VDDIO_BO_VAL));
1350 mxs_power_set_vddx(&mxs_vddio_cfg, VDDIO_VAL, VDDIO_BO_VAL);
1351 debug("SPL: Setting VDDD to %uV%u (brownout @ %uv%02u)\n",
1352 VDDX_VAL(VDDD_VAL), VDDX_VAL(VDDD_VAL - VDDD_BO_VAL));
1353 mxs_power_set_vddx(&mxs_vddd_cfg, VDDD_VAL, VDDD_BO_VAL);
1354 debug("SPL: Setting VDDA to %uV%u (brownout @ %uv%02u)\n",
1355 VDDX_VAL(VDDA_VAL), VDDX_VAL(VDDA_VAL - VDDA_BO_VAL));
1356 mxs_power_set_vddx(&mxs_vdda_cfg, VDDA_VAL, VDDA_BO_VAL);
1357 #ifdef CONFIG_SOC_MX23
1358 debug("SPL: Setting VDDMEM to %uV%u (brownout @ %uv%02u)\n",
1359 VDDX_VAL(VDDMEM_VAL), VDDX_VAL(VDDMEM_VAL - VDDMEM_BO_VAL));
1360 mxs_power_set_vddx(&mxs_vddmem_cfg, VDDMEM_VAL, VDDMEM_BO_VAL);
1362 clrbits_le32(&power_regs->hw_power_vddmemctrl,
1363 POWER_VDDMEMCTRL_ENABLE_LINREG);
1365 writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
1366 POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
1367 POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
1368 POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
1369 if (!fixed_batt_supply)
1370 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
1371 &power_regs->hw_power_5vctrl_set);
1374 #ifdef CONFIG_SPL_MXS_PSWITCH_WAIT
1376 * mxs_power_wait_pswitch() - Wait for power switch to be pressed
1378 * This function waits until the power-switch was pressed to start booting
1381 void mxs_power_wait_pswitch(void)
1383 debug("SPL: Waiting for power switch input\n");
1384 while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))