arch/arm/cpu/armv7/mx5/soc.c

   1 /*
   2  * (C) Copyright 2007
   3  * Sascha Hauer, Pengutronix
   4  *
   5  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <asm/arch/imx-regs.h>
  28 #include <asm/arch/clock.h>
  29 #include <asm/arch/sys_proto.h>
  30
  31 #include <asm/errno.h>
  32 #include <asm/io.h>
  33
  34 #ifdef CONFIG_FSL_ESDHC
  35 #include <fsl_esdhc.h>
  36 #endif
  37
  38 #if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
  39 #error "CPU_TYPE not defined"
  40 #endif
  41
  42 u32 get_cpu_rev(void)
  43 {
  44 #ifdef CONFIG_MX51
  45         int system_rev = 0x51000;
  46 #else
  47         int system_rev = 0x53000;
  48 #endif
  49         int reg = __raw_readl(ROM_SI_REV);
  50
  51 #if defined(CONFIG_MX51)
  52         switch (reg) {
  53         case 0x02:
  54                 system_rev |= CHIP_REV_1_1;
  55                 break;
  56         case 0x10:
  57                 if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0)
  58                         system_rev |= CHIP_REV_2_5;
  59                 else
  60                         system_rev |= CHIP_REV_2_0;
  61                 break;
  62         case 0x20:
  63                 system_rev |= CHIP_REV_3_0;
  64                 break;
  65         default:
  66                 system_rev |= CHIP_REV_1_0;
  67                 break;
  68         }
  69 #else
  70         if (reg < 0x20)
  71                 system_rev |= CHIP_REV_1_0;
  72         else
  73                 system_rev |= reg;
  74 #endif
  75         return system_rev;
  76 }
  77
  78 static char *get_reset_cause(void)
  79 {
  80         u32 cause;
  81         struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  82
  83         cause = readl(&src_regs->srsr);
  84         writel(cause, &src_regs->srsr);
  85
  86         switch (cause) {
  87         case 0x00001:
  88                 return "POR";
  89         case 0x00004:
  90                 return "CSU";
  91         case 0x00008:
  92                 return "IPP USER";
  93         case 0x00010:
  94                 return "WDOG";
  95         case 0x00020:
  96                 return "JTAG HIGH-Z";
  97         case 0x00040:
  98                 return "JTAG SW";
  99         case 0x10000:
 100                 return "WARM BOOT";
 101         default:
 102                 return "unknown reset";
 103         }
 104 }
 105
 106 #if defined(CONFIG_DISPLAY_CPUINFO)
 107 int print_cpuinfo(void)
 108 {
 109         u32 cpurev;
 110
 111         cpurev = get_cpu_rev();
 112         printf("CPU:   Freescale i.MX%x family rev%d.%d at %d MHz\n",
 113                 (cpurev & 0xFF000) >> 12,
 114                 (cpurev & 0x000F0) >> 4,
 115                 (cpurev & 0x0000F) >> 0,
 116                 mxc_get_clock(MXC_ARM_CLK) / 1000000);
 117         printf("Reset cause: %s\n", get_reset_cause());
 118         return 0;
 119 }
 120 #endif
 121
 122 int cpu_eth_init(bd_t *bis)
 123 {
 124         int rc = -ENODEV;
 125
 126 #if defined(CONFIG_FEC_MXC)
 127         rc = fecmxc_initialize(bis);
 128 #endif
 129
 130         return rc;
 131 }
 132
 133 #if defined(CONFIG_FEC_MXC)
 134 void imx_get_mac_from_fuse(unsigned char *mac)
 135 {
 136         int i;
 137         struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
 138         struct fuse_bank *bank = &iim->bank[1];
 139         struct fuse_bank1_regs *fuse =
 140                         (struct fuse_bank1_regs *)bank->fuse_regs;
 141
 142         for (i = 0; i < 6; i++)
 143                 mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
 144 }
 145 #endif
 146
 147 /*
 148  * Initializes on-chip MMC controllers.
 149  * to override, implement board_mmc_init()
 150  */
 151 int cpu_mmc_init(bd_t *bis)
 152 {
 153 #ifdef CONFIG_FSL_ESDHC
 154         return fsl_esdhc_mmc_init(bis);
 155 #else
 156         return 0;
 157 #endif
 158 }
 159
 160 void set_chipselect_size(int const cs_size)
 161 {
 162         unsigned int reg;
 163         struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 164         reg = readl(&iomuxc_regs->gpr1);
 165
 166         switch (cs_size) {
 167         case CS0_128:
 168                 reg &= ~0x7;    /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
 169                 reg |= 0x5;
 170                 break;
 171         case CS0_64M_CS1_64M:
 172                 reg &= ~0x3F;   /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
 173                 reg |= 0x1B;
 174                 break;
 175         case CS0_64M_CS1_32M_CS2_32M:
 176                 reg &= ~0x1FF;  /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
 177                 reg |= 0x4B;
 178                 break;
 179         case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
 180                 reg &= ~0xFFF;  /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
 181                 reg |= 0x249;
 182                 break;
 183         default:
 184                 printf("Unknown chip select size: %d\n", cs_size);
 185                 break;
 186         }
 187
 188         writel(reg, &iomuxc_regs->gpr1);
 189 }
 190
 191 void reset_cpu(ulong addr)
 192 {
 193         __raw_writew(4, WDOG1_BASE_ADDR);
 194 }