2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/errno.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
17 PLL_ARM, /* PLL1: ARM PLL */
18 PLL_528, /* PLL2: System Bus PLL*/
19 PLL_USBOTG, /* PLL3: OTG USB PLL */
20 PLL_AUDIO, /* PLL4: Audio PLL */
21 PLL_VIDEO, /* PLL5: Video PLL */
22 PLL_ENET, /* PLL6: ENET PLL */
23 PLL_USB2, /* PLL7: USB2 PLL */
24 PLL_MLB, /* PLL8: MLB PLL */
27 struct mxc_ccm_reg *const imx_ccm = (void *)CCM_BASE_ADDR;
28 struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
30 int clk_enable(struct clk *clk)
36 if (clk->usecount == 0) {
37 debug("%s: Enabling %s clock\n", __func__, clk->name);
38 ret = clk->enable(clk);
43 assert(clk->usecount > 0);
47 void clk_disable(struct clk *clk)
52 assert(clk->usecount > 0);
53 if (!(--clk->usecount)) {
55 debug("%s: Disabling %s clock\n", __func__, clk->name);
61 int clk_get_usecount(struct clk *clk)
69 u32 clk_get_rate(struct clk *clk)
77 struct clk *clk_get_parent(struct clk *clk)
85 int clk_set_rate(struct clk *clk, unsigned long rate)
87 if (clk && clk->set_rate)
88 clk->set_rate(clk, rate);
92 long clk_round_rate(struct clk *clk, unsigned long rate)
94 if (clk == NULL || !clk->round_rate)
97 return clk->round_rate(clk, rate);
100 int clk_set_parent(struct clk *clk, struct clk *parent)
102 debug("Setting parent of clk %p to %p (%p)\n", clk, parent,
103 clk ? clk->parent : NULL);
105 if (!clk || clk == parent)
108 if (clk->set_parent) {
111 ret = clk->set_parent(clk, parent);
115 clk->parent = parent;
119 #ifdef CONFIG_MXC_OCOTP
120 void enable_ocotp_clk(unsigned char enable)
124 reg = __raw_readl(&imx_ccm->CCGR2);
126 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
128 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
129 __raw_writel(reg, &imx_ccm->CCGR2);
133 #ifdef CONFIG_NAND_MXS
134 void setup_gpmi_io_clk(u32 cfg)
136 /* Disable clocks per ERR007177 from MX6 errata */
137 clrbits_le32(&imx_ccm->CCGR4,
138 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
139 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
140 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
141 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
142 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
144 clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
146 clrsetbits_le32(&imx_ccm->cs2cdr,
147 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
148 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
149 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
152 setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
153 setbits_le32(&imx_ccm->CCGR4,
154 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
155 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
156 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
157 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
158 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
162 void enable_usboh3_clk(unsigned char enable)
166 reg = __raw_readl(&imx_ccm->CCGR6);
168 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
170 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
171 __raw_writel(reg, &imx_ccm->CCGR6);
175 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_SOC_MX6SX)
176 void enable_enet_clk(unsigned char enable)
178 u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
181 setbits_le32(&imx_ccm->CCGR1, mask);
183 clrbits_le32(&imx_ccm->CCGR1, mask);
187 #ifdef CONFIG_MXC_UART
188 void enable_uart_clk(unsigned char enable)
190 u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
193 setbits_le32(&imx_ccm->CCGR5, mask);
195 clrbits_le32(&imx_ccm->CCGR5, mask);
200 /* spi_num can be from 0 - 4 */
201 int enable_cspi_clock(unsigned char enable, unsigned spi_num)
208 mask = MXC_CCM_CCGR_CG_MASK << (spi_num * 2);
210 setbits_le32(&imx_ccm->CCGR1, mask);
212 clrbits_le32(&imx_ccm->CCGR1, mask);
219 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
226 mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
228 setbits_le32(&imx_ccm->CCGR6, mask);
230 clrbits_le32(&imx_ccm->CCGR6, mask);
236 #ifdef CONFIG_SYS_I2C_MXC
237 /* i2c_num can be from 0 - 2 */
238 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
246 mask = MXC_CCM_CCGR_CG_MASK
247 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
248 reg = __raw_readl(&imx_ccm->CCGR2);
253 __raw_writel(reg, &imx_ccm->CCGR2);
258 /* spi_num can be from 0 - SPI_MAX_NUM */
259 int enable_spi_clk(unsigned char enable, unsigned spi_num)
264 if (spi_num > SPI_MAX_NUM)
267 mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
268 reg = __raw_readl(&imx_ccm->CCGR1);
273 __raw_writel(reg, &imx_ccm->CCGR1);
276 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
282 div = __raw_readl(&anatop->pll_arm);
283 if (div & BM_ANADIG_PLL_ARM_BYPASS)
284 /* Assume the bypass clock is always derived from OSC */
286 div &= BM_ANADIG_PLL_ARM_DIV_SELECT;
288 return infreq * div / 2;
290 div = __raw_readl(&anatop->pll_528);
291 if (div & BM_ANADIG_PLL_528_BYPASS)
293 div &= BM_ANADIG_PLL_528_DIV_SELECT;
295 return infreq * (20 + div * 2);
297 div = __raw_readl(&anatop->usb1_pll_480_ctrl);
298 if (div & BM_ANADIG_USB_PLL_480_CTRL_BYPASS)
300 div &= BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT;
302 return infreq * (20 + div * 2);
304 div = __raw_readl(&anatop->pll_audio);
305 if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
307 div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
311 div = __raw_readl(&anatop->pll_video);
312 if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
314 div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
318 div = __raw_readl(&anatop->pll_enet);
319 if (div & BM_ANADIG_PLL_ENET_BYPASS)
321 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
323 return 25000000 * (div + (div >> 1) + 1);
325 div = __raw_readl(&anatop->usb2_pll_480_ctrl);
326 if (div & BM_ANADIG_USB_PLL_480_CTRL_BYPASS)
328 div &= BM_ANADIG_USB_PLL_480_CTRL_DIV_SELECT;
330 return infreq * (20 + div * 2);
332 div = __raw_readl(&anatop->pll_mlb);
333 if (div & BM_ANADIG_PLL_MLB_BYPASS)
335 /* unknown external clock provided on MLB_CLK pin */
340 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
344 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
349 /* No PFD3 on PLL2 */
352 div = __raw_readl(&anatop->pfd_528);
353 freq = (u64)decode_pll(PLL_528, MXC_HCLK);
356 div = __raw_readl(&anatop->pfd_480);
357 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
360 /* No PFD on other PLL */
364 return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
365 ANATOP_PFD_FRAC_SHIFT(pfd_num));
368 static u32 get_mcu_main_clk(void)
372 reg = __raw_readl(&imx_ccm->cacrr);
373 reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
374 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
375 freq = decode_pll(PLL_ARM, MXC_HCLK);
377 return freq / (reg + 1);
380 u32 get_periph_clk(void)
384 reg = __raw_readl(&imx_ccm->cbcdr);
385 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
386 reg = __raw_readl(&imx_ccm->cbcmr);
387 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
388 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
392 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
400 reg = __raw_readl(&imx_ccm->cbcmr);
401 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
402 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
406 freq = decode_pll(PLL_528, MXC_HCLK);
409 freq = mxc_get_pll_pfd(PLL_528, 2);
412 freq = mxc_get_pll_pfd(PLL_528, 0);
415 /* static / 2 divider */
416 freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
424 static u32 get_ipg_clk(void)
428 reg = __raw_readl(&imx_ccm->cbcdr);
429 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
430 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
432 return get_ahb_clk() / (ipg_podf + 1);
435 static u32 get_ipg_per_clk(void)
437 u32 reg, perclk_podf;
439 reg = __raw_readl(&imx_ccm->cscmr1);
440 #if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
441 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
442 return MXC_HCLK; /* OSC 24Mhz */
444 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
446 return get_ipg_clk() / (perclk_podf + 1);
449 static u32 get_uart_clk(void)
452 u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
453 reg = __raw_readl(&imx_ccm->cscdr1);
454 #if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
455 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
458 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
459 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
461 return freq / (uart_podf + 1);
464 static u32 get_cspi_clk(void)
468 reg = __raw_readl(&imx_ccm->cscdr2);
469 reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
470 cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
472 return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
475 static u32 get_axi_clk(void)
477 u32 root_freq, axi_podf;
478 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
480 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
481 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
483 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
484 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
485 root_freq = mxc_get_pll_pfd(PLL_528, 2);
487 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
489 root_freq = get_periph_clk();
491 return root_freq / (axi_podf + 1);
494 static u32 get_emi_slow_clk(void)
496 u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
498 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
499 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
500 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
501 emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
502 emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
504 switch (emi_clk_sel) {
506 root_freq = get_axi_clk();
509 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
512 root_freq = mxc_get_pll_pfd(PLL_528, 2);
515 root_freq = mxc_get_pll_pfd(PLL_528, 0);
519 return root_freq / (emi_slow_podf + 1);
522 static u32 get_nfc_clk(void)
524 u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
525 u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
526 u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
527 int nfc_clk_sel = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >>
528 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
531 switch (nfc_clk_sel) {
533 root_freq = mxc_get_pll_pfd(PLL_528, 0);
536 root_freq = decode_pll(PLL_528, MXC_HCLK);
539 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
542 root_freq = mxc_get_pll_pfd(PLL_528, 2);
546 return root_freq / (pred + 1) / (podf + 1);
549 #define CS2CDR_ENFC_MASK (MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | \
550 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | \
551 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK)
553 static int set_nfc_clk(u32 ref, u32 freq_khz)
555 u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
562 u32 freq = freq_khz * 1000;
564 for (nfc_clk_sel = 0; nfc_clk_sel < 4; nfc_clk_sel++) {
568 if (ref < 4 && ref != nfc_clk_sel)
571 switch (nfc_clk_sel) {
573 root_freq = mxc_get_pll_pfd(PLL_528, 0);
576 root_freq = decode_pll(PLL_528, MXC_HCLK);
579 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
582 root_freq = mxc_get_pll_pfd(PLL_528, 2);
585 if (root_freq < freq)
588 podf = min(DIV_ROUND_UP(root_freq, freq), 1U << 6);
589 pred = min(DIV_ROUND_UP(root_freq / podf, freq), 8U);
590 act_freq = root_freq / pred / podf;
591 err = (freq - act_freq) * 100 / freq;
592 debug("root=%d[%u] freq=%u pred=%u podf=%u act=%u err=%d\n",
593 nfc_clk_sel, root_freq, freq, pred, podf, act_freq, err);
597 nfc_val = (podf - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
598 nfc_val |= (pred - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
599 nfc_val |= nfc_clk_sel << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
606 if (nfc_val == ~0 || min_err > 10)
609 if ((cs2cdr & CS2CDR_ENFC_MASK) != nfc_val) {
610 debug("changing cs2cdr from %08x to %08x\n", cs2cdr,
611 (cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val);
612 __raw_writel((cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val,
615 debug("Leaving cs2cdr unchanged [%08x]\n", cs2cdr);
620 #if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
621 static u32 get_mmdc_ch0_clk(void)
623 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
624 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
627 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
628 >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
630 switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
631 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
633 freq = decode_pll(PLL_528, MXC_HCLK);
636 freq = mxc_get_pll_pfd(PLL_528, 2);
639 freq = mxc_get_pll_pfd(PLL_528, 0);
642 /* static / 2 divider */
643 freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
646 return freq / (podf + 1);
650 static u32 get_mmdc_ch0_clk(void)
652 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
653 u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
654 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
656 return get_periph_clk() / (mmdc_ch0_podf + 1);
660 #ifdef CONFIG_SOC_MX6SX
661 /* qspi_num can be from 0 - 1 */
662 void enable_qspi_clk(int qspi_num)
665 /* Enable QuadSPI clock */
668 /* disable the clock gate */
669 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
671 /* set 50M : (50 = 396 / 2 / 4) */
672 reg = readl(&imx_ccm->cscmr1);
673 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
674 MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
675 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
676 (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
677 writel(reg, &imx_ccm->cscmr1);
679 /* enable the clock gate */
680 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
684 * disable the clock gate
685 * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
686 * disable both of them.
688 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
689 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
691 /* set 50M : (50 = 396 / 2 / 4) */
692 reg = readl(&imx_ccm->cs2cdr);
693 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
694 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
695 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
696 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
697 MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
698 writel(reg, &imx_ccm->cs2cdr);
700 /*enable the clock gate*/
701 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
702 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
710 #ifdef CONFIG_FEC_MXC
711 int enable_fec_anatop_clock(enum enet_freq freq)
714 s32 timeout = 100000;
716 struct anatop_regs __iomem *anatop =
717 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
719 if (freq < ENET_25MHZ || freq > ENET_125MHZ)
722 reg = readl(&anatop->pll_enet);
723 reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
726 if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
727 (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
728 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
729 writel(reg, &anatop->pll_enet);
731 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
738 /* Enable FEC clock */
739 reg |= BM_ANADIG_PLL_ENET_ENABLE;
740 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
741 writel(reg, &anatop->pll_enet);
743 #ifdef CONFIG_SOC_MX6SX
745 * Set enet ahb clock to 200MHz
746 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
748 reg = readl(&imx_ccm->chsccdr);
749 reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
750 | MXC_CCM_CHSCCDR_ENET_PODF_MASK
751 | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
753 reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
755 reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
756 reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
757 writel(reg, &imx_ccm->chsccdr);
759 /* Enable enet system clock */
760 reg = readl(&imx_ccm->CCGR3);
761 reg |= MXC_CCM_CCGR3_ENET_MASK;
762 writel(reg, &imx_ccm->CCGR3);
768 static u32 get_usdhc_clk(u32 port)
770 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
771 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
772 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
776 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
777 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
778 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
782 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
783 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
784 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
788 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
789 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
790 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
794 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
795 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
796 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
804 root_freq = mxc_get_pll_pfd(PLL_528, 0);
806 root_freq = mxc_get_pll_pfd(PLL_528, 2);
808 return root_freq / (usdhc_podf + 1);
811 u32 imx_get_uartclk(void)
813 return get_uart_clk();
816 u32 imx_get_fecclk(void)
818 return mxc_get_clock(MXC_IPG_CLK);
821 static int enable_enet_pll(uint32_t en)
824 s32 timeout = 100000;
827 reg = readl(&anatop->pll_enet);
828 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
829 writel(reg, &anatop->pll_enet);
830 reg |= BM_ANADIG_PLL_ENET_ENABLE;
832 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
837 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
838 writel(reg, &anatop->pll_enet);
840 writel(reg, &anatop->pll_enet);
844 #ifndef CONFIG_SOC_MX6SX
845 static void ungate_sata_clock(void)
847 struct mxc_ccm_reg *const imx_ccm =
848 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
850 /* Enable SATA clock. */
851 setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
855 static void ungate_pcie_clock(void)
857 struct mxc_ccm_reg *const imx_ccm =
858 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
860 /* Enable PCIe clock. */
861 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
864 #ifndef CONFIG_SOC_MX6SX
865 int enable_sata_clock(void)
868 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
871 void disable_sata_clock(void)
873 struct mxc_ccm_reg *const imx_ccm =
874 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
876 clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
880 int enable_pcie_clock(void)
882 struct anatop_regs *anatop_regs =
883 (struct anatop_regs *)ANATOP_BASE_ADDR;
884 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
890 * The register ANATOP_MISC1 is not documented in the Freescale
891 * MX6RM. The register that is mapped in the ANATOP space and
892 * marked as ANATOP_MISC1 is actually documented in the PMU section
893 * of the datasheet as PMU_MISC1.
895 * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
896 * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
897 * for PCI express link that is clocked from the i.MX6.
899 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
900 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
901 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
902 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
903 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
905 if (is_cpu_type(MXC_CPU_MX6SX))
906 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
908 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
910 clrsetbits_le32(&anatop_regs->ana_misc1,
911 ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
912 ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
913 ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
915 /* PCIe reference clock sourced from AXI. */
916 clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
918 /* Party time! Ungate the clock to the PCIe. */
919 #ifndef CONFIG_SOC_MX6SX
924 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
925 BM_ANADIG_PLL_ENET_ENABLE_PCIE);
928 #ifdef CONFIG_SECURE_BOOT
929 void hab_caam_clock_enable(unsigned char enable)
933 /* CG4 ~ CG6, CAAM clocks */
934 reg = __raw_readl(&imx_ccm->CCGR0);
936 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
937 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
938 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
940 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
941 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
942 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
943 __raw_writel(reg, &imx_ccm->CCGR0);
946 reg = __raw_readl(&imx_ccm->CCGR6);
948 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
950 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
951 __raw_writel(reg, &imx_ccm->CCGR6);
955 static void enable_pll3(void)
957 struct anatop_regs __iomem *anatop =
958 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
960 /* make sure pll3 is enabled */
961 if ((readl(&anatop->usb1_pll_480_ctrl) &
962 BM_ANADIG_USB_PLL_480_CTRL_LOCK) == 0) {
963 /* enable pll's power */
964 writel(BM_ANADIG_USB_PLL_480_CTRL_POWER,
965 &anatop->usb1_pll_480_ctrl_set);
966 writel(0x80, &anatop->ana_misc2_clr);
967 /* wait for pll lock */
968 while ((readl(&anatop->usb1_pll_480_ctrl) &
969 BM_ANADIG_USB_PLL_480_CTRL_LOCK) == 0)
972 writel(BM_ANADIG_USB_PLL_480_CTRL_BYPASS,
973 &anatop->usb1_pll_480_ctrl_clr);
974 /* enable pll output */
975 writel(BM_ANADIG_USB_PLL_480_CTRL_ENABLE,
976 &anatop->usb1_pll_480_ctrl_set);
980 void enable_thermal_clk(void)
985 void ipu_clk_enable(void)
987 u32 reg = readl(&imx_ccm->CCGR3);
988 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
989 writel(reg, &imx_ccm->CCGR3);
992 void ipu_clk_disable(void)
994 u32 reg = readl(&imx_ccm->CCGR3);
995 reg &= ~MXC_CCM_CCGR3_IPU1_IPU_MASK;
996 writel(reg, &imx_ccm->CCGR3);
999 void ipu_di_clk_enable(int di)
1003 setbits_le32(&imx_ccm->CCGR3,
1004 MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1007 setbits_le32(&imx_ccm->CCGR3,
1008 MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1011 printf("%s: Invalid DI index %d\n", __func__, di);
1015 void ipu_di_clk_disable(int di)
1019 clrbits_le32(&imx_ccm->CCGR3,
1020 MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1023 clrbits_le32(&imx_ccm->CCGR3,
1024 MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1027 printf("%s: Invalid DI index %d\n", __func__, di);
1031 void ldb_clk_enable(int ldb)
1035 setbits_le32(&imx_ccm->CCGR3,
1036 MXC_CCM_CCGR3_LDB_DI0_MASK);
1039 setbits_le32(&imx_ccm->CCGR3,
1040 MXC_CCM_CCGR3_LDB_DI1_MASK);
1043 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1047 void ldb_clk_disable(int ldb)
1051 clrbits_le32(&imx_ccm->CCGR3,
1052 MXC_CCM_CCGR3_LDB_DI0_MASK);
1055 clrbits_le32(&imx_ccm->CCGR3,
1056 MXC_CCM_CCGR3_LDB_DI1_MASK);
1059 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1063 void ocotp_clk_enable(void)
1065 u32 reg = readl(&imx_ccm->CCGR2);
1066 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
1067 writel(reg, &imx_ccm->CCGR2);
1070 void ocotp_clk_disable(void)
1072 u32 reg = readl(&imx_ccm->CCGR2);
1073 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
1074 writel(reg, &imx_ccm->CCGR2);
1077 unsigned int mxc_get_clock(enum mxc_clock clk)
1081 return get_mcu_main_clk();
1083 return get_periph_clk();
1085 return get_ahb_clk();
1087 return get_ipg_clk();
1088 case MXC_IPG_PERCLK:
1090 return get_ipg_per_clk();
1092 return get_uart_clk();
1094 return get_cspi_clk();
1096 return get_axi_clk();
1097 case MXC_EMI_SLOW_CLK:
1098 return get_emi_slow_clk();
1100 return get_mmdc_ch0_clk();
1102 return get_usdhc_clk(0);
1103 case MXC_ESDHC2_CLK:
1104 return get_usdhc_clk(1);
1105 case MXC_ESDHC3_CLK:
1106 return get_usdhc_clk(2);
1107 case MXC_ESDHC4_CLK:
1108 return get_usdhc_clk(3);
1110 return get_ahb_clk();
1112 return get_nfc_clk();
1114 printf("Unsupported MXC CLK: %d\n", clk);
1120 static inline int gcd(int m, int n)
1134 /* Config CPU clock */
1135 static int set_arm_clk(u32 ref, u32 freq_khz)
1143 if (freq_khz > ref / 1000 * 108 / 2 || freq_khz < ref / 1000 * 54 / 8 / 2) {
1144 printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03u\n",
1145 freq_khz / 1000, freq_khz % 1000,
1146 54 * ref / 1000000 / 8 / 2, 54 * ref / 1000 / 8 / 2 % 1000,
1147 108 * ref / 1000000 / 2, 108 * ref / 1000 / 2 % 1000);
1151 for (d = DIV_ROUND_UP(648000, freq_khz); d <= 8; d++) {
1152 int m = freq_khz * 2 * d / (ref / 1000);
1157 debug("%s@%d: d=%d m=%d\n", __func__, __LINE__,
1162 f = ref * m / d / 2;
1163 if (f > freq_khz * 1000) {
1164 debug("%s@%d: d=%d m=%d f=%u freq=%u\n", __func__, __LINE__,
1168 f = ref * m / d / 2;
1170 err = freq_khz * 1000 - f;
1171 debug("%s@%d: d=%d m=%d f=%u freq=%u err=%d\n", __func__, __LINE__,
1172 d, m, f, freq_khz, err);
1173 if (err < min_err) {
1183 debug("Setting M=%3u D=%2u for %u.%03uMHz (actual: %u.%03uMHz)\n",
1184 mul, div, freq_khz / 1000, freq_khz % 1000,
1185 ref * mul / 2 / div / 1000000, ref * mul / 2 / div / 1000 % 1000);
1187 reg = readl(&anatop->pll_arm);
1188 debug("anadig_pll_arm=%08x -> %08x\n",
1189 reg, (reg & ~0x7f) | mul);
1192 writel(reg, &anatop->pll_arm); /* bypass PLL */
1194 reg = (reg & ~0x7f) | mul;
1195 writel(reg, &anatop->pll_arm);
1197 writel(div - 1, &imx_ccm->cacrr);
1200 writel(reg, &anatop->pll_arm); /* disable PLL bypass */
1206 * This function assumes the expected core clock has to be changed by
1207 * modifying the PLL. This is NOT true always but for most of the times,
1208 * it is. So it assumes the PLL output freq is the same as the expected
1209 * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
1210 * In the latter case, it will try to increase the presc value until
1211 * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
1212 * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
1213 * on the targeted PLL and reference input clock to the PLL. Lastly,
1214 * it sets the register based on these values along with the dividers.
1215 * Note 1) There is no value checking for the passed-in divider values
1216 * so the caller has to make sure those values are sensible.
1217 * 2) Also adjust the NFC divider such that the NFC clock doesn't
1218 * exceed NFC_CLK_MAX.
1219 * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
1220 * 177MHz for higher voltage, this function fixes the max to 133MHz.
1221 * 4) This function should not have allowed diag_printf() calls since
1222 * the serial driver has been stoped. But leave then here to allow
1223 * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
1225 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
1233 ret = set_arm_clk(ref, freq);
1237 ret = set_nfc_clk(ref, freq);
1241 printf("Warning: Unsupported or invalid clock type: %d\n",
1250 * Dump some core clocks.
1252 #define print_pll(pll) { \
1253 u32 __pll = decode_pll(pll, MXC_HCLK); \
1254 printf("%-12s %4d.%03d MHz\n", #pll, \
1255 __pll / 1000000, __pll / 1000 % 1000); \
1258 #define MXC_IPG_PER_CLK MXC_IPG_PERCLK
1260 #define print_clk(clk) { \
1261 u32 __clk = mxc_get_clock(MXC_##clk##_CLK); \
1262 printf("%-12s %4d.%03d MHz\n", #clk, \
1263 __clk / 1000000, __clk / 1000 % 1000); \
1266 #define print_pfd(pll, pfd) { \
1267 u32 __pfd = readl(&anatop->pfd_##pll); \
1268 if (__pfd & (0x80 << 8 * pfd)) { \
1269 printf("PFD_%s[%d] OFF\n", #pll, pfd); \
1271 __pfd = (__pfd >> 8 * pfd) & 0x3f; \
1272 printf("PFD_%s[%d] %4d.%03d MHz\n", #pll, pfd, \
1274 pll * 18 * 1000 / __pfd % 1000); \
1278 static void do_mx6_showclocks(void)
1282 print_pll(PLL_USBOTG);
1283 print_pll(PLL_AUDIO);
1284 print_pll(PLL_VIDEO);
1285 print_pll(PLL_ENET);
1286 print_pll(PLL_USB2);
1308 print_clk(EMI_SLOW);
1314 static struct clk_lookup {
1317 } mx6_clk_lookup[] = {
1318 { "arm", MXC_ARM_CLK, },
1319 { "nfc", MXC_NFC_CLK, },
1322 int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1326 unsigned long ref = ~0UL;
1329 do_mx6_showclocks();
1330 return CMD_RET_SUCCESS;
1331 } else if (argc == 2 || argc > 4) {
1332 return CMD_RET_USAGE;
1335 freq = simple_strtoul(argv[2], NULL, 0);
1337 printf("Invalid clock frequency %lu\n", freq);
1338 return CMD_RET_FAILURE;
1341 ref = simple_strtoul(argv[3], NULL, 0);
1343 for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1344 if (strcasecmp(argv[1], mx6_clk_lookup[i].name) == 0) {
1345 switch (mx6_clk_lookup[i].index) {
1348 return CMD_RET_USAGE;
1353 if (argc > 3 && ref > 3) {
1354 printf("Invalid clock selector value: %lu\n", ref);
1355 return CMD_RET_FAILURE;
1359 printf("Setting %s clock to %lu MHz\n",
1360 mx6_clk_lookup[i].name, freq);
1361 if (mxc_set_clock(ref, freq, mx6_clk_lookup[i].index))
1363 freq = mxc_get_clock(mx6_clk_lookup[i].index);
1364 printf("%s clock set to %lu.%03lu MHz\n",
1365 mx6_clk_lookup[i].name,
1366 freq / 1000000, freq / 1000 % 1000);
1367 return CMD_RET_SUCCESS;
1370 if (i == ARRAY_SIZE(mx6_clk_lookup)) {
1371 printf("clock %s not found; supported clocks are:\n", argv[1]);
1372 for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1373 printf("\t%s\n", mx6_clk_lookup[i].name);
1376 printf("Failed to set clock %s to %s MHz\n",
1379 return CMD_RET_FAILURE;
1382 #ifndef CONFIG_SOC_MX6SX
1383 void enable_ipu_clock(void)
1385 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1387 reg = readl(&mxc_ccm->CCGR3);
1388 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1389 writel(reg, &mxc_ccm->CCGR3);
1392 /***************************************************/
1395 clocks, 4, 0, do_clocks,
1396 "display/set clocks",
1397 " - display clock settings\n"
1398 "clocks <clkname> <freq> - set clock <clkname> to <freq> MHz"