2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/errno.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
17 PLL_ARM, /* PLL1: ARM PLL */
18 PLL_528, /* PLL2: System Bus PLL*/
19 PLL_USBOTG, /* PLL3: OTG USB PLL */
20 PLL_AUDIO, /* PLL4: Audio PLL */
21 PLL_VIDEO, /* PLL5: Video PLL */
22 PLL_ENET, /* PLL6: ENET PLL */
23 PLL_USB2, /* PLL7: USB2 PLL */
24 PLL_MLB, /* PLL8: MLB PLL */
27 struct mxc_ccm_reg *const imx_ccm = (void *)CCM_BASE_ADDR;
28 struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR;
30 int clk_enable(struct clk *clk)
36 if (clk->usecount == 0) {
37 debug("%s: Enabling %s clock\n", __func__, clk->name);
38 ret = clk->enable(clk);
43 assert(clk->usecount > 0);
47 void clk_disable(struct clk *clk)
52 assert(clk->usecount > 0);
53 if (!(--clk->usecount)) {
55 debug("%s: Disabling %s clock\n", __func__, clk->name);
61 int clk_get_usecount(struct clk *clk)
69 u32 clk_get_rate(struct clk *clk)
77 struct clk *clk_get_parent(struct clk *clk)
85 int clk_set_rate(struct clk *clk, unsigned long rate)
87 if (clk && clk->set_rate)
88 clk->set_rate(clk, rate);
92 long clk_round_rate(struct clk *clk, unsigned long rate)
94 if (clk == NULL || !clk->round_rate)
97 return clk->round_rate(clk, rate);
100 int clk_set_parent(struct clk *clk, struct clk *parent)
102 debug("Setting parent of clk %p to %p (%p)\n", clk, parent,
103 clk ? clk->parent : NULL);
105 if (!clk || clk == parent)
108 if (clk->set_parent) {
111 ret = clk->set_parent(clk, parent);
115 clk->parent = parent;
119 #ifdef CONFIG_MXC_OCOTP
120 void enable_ocotp_clk(unsigned char enable)
124 reg = __raw_readl(&imx_ccm->CCGR2);
126 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
128 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
129 __raw_writel(reg, &imx_ccm->CCGR2);
133 #ifdef CONFIG_NAND_MXS
134 void setup_gpmi_io_clk(u32 cfg)
136 /* Disable clocks per ERR007177 from MX6 errata */
137 clrbits_le32(&imx_ccm->CCGR4,
138 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
139 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
140 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
141 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
142 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
144 clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
146 clrsetbits_le32(&imx_ccm->cs2cdr,
147 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
148 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
149 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
152 setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
153 setbits_le32(&imx_ccm->CCGR4,
154 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
155 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
156 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
157 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
158 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
162 void enable_usboh3_clk(unsigned char enable)
166 reg = __raw_readl(&imx_ccm->CCGR6);
168 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
170 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
171 __raw_writel(reg, &imx_ccm->CCGR6);
175 #if defined(CONFIG_FEC_MXC) && !defined(CONFIG_SOC_MX6SX)
176 void enable_enet_clk(unsigned char enable)
180 if (is_cpu_type(MXC_CPU_MX6UL)) {
181 mask = MXC_CCM_CCGR3_ENET_MASK;
182 addr = &imx_ccm->CCGR3;
184 mask = MXC_CCM_CCGR1_ENET_MASK;
185 addr = &imx_ccm->CCGR1;
189 setbits_le32(addr, mask);
191 clrbits_le32(addr, mask);
195 #ifdef CONFIG_MXC_UART
196 void enable_uart_clk(unsigned char enable)
200 if (is_cpu_type(MXC_CPU_MX6UL))
201 mask = MXC_CCM_CCGR5_UART_MASK;
203 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
206 setbits_le32(&imx_ccm->CCGR5, mask);
208 clrbits_le32(&imx_ccm->CCGR5, mask);
213 int enable_usdhc_clk(unsigned char enable, unsigned bus_num)
220 mask = MXC_CCM_CCGR_CG_MASK << (bus_num * 2 + 2);
222 setbits_le32(&imx_ccm->CCGR6, mask);
224 clrbits_le32(&imx_ccm->CCGR6, mask);
230 #ifdef CONFIG_SYS_I2C_MXC
231 /* i2c_num can be from 0 - 3 */
232 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
241 mask = MXC_CCM_CCGR_CG_MASK
242 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
244 reg = __raw_readl(&imx_ccm->CCGR2);
249 __raw_writel(reg, &imx_ccm->CCGR2);
251 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
252 mask = MXC_CCM_CCGR6_I2C4_MASK;
253 addr = &imx_ccm->CCGR6;
255 mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
256 addr = &imx_ccm->CCGR1;
258 reg = __raw_readl(addr);
263 __raw_writel(reg, addr);
269 /* spi_num can be from 0 - SPI_MAX_NUM */
270 int enable_spi_clk(unsigned char enable, unsigned spi_num)
275 if (spi_num > SPI_MAX_NUM)
278 mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
279 reg = __raw_readl(&imx_ccm->CCGR1);
284 __raw_writel(reg, &imx_ccm->CCGR1);
287 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
293 div = __raw_readl(&anatop->pll_arm);
294 if (div & BM_ANADIG_PLL_ARM_BYPASS)
295 /* Assume the bypass clock is always derived from OSC */
297 div &= BM_ANADIG_PLL_ARM_DIV_SELECT;
299 return infreq * div / 2;
301 div = __raw_readl(&anatop->pll_528);
302 if (div & BM_ANADIG_PLL_528_BYPASS)
304 div &= BM_ANADIG_PLL_528_DIV_SELECT;
306 return infreq * (20 + div * 2);
308 div = __raw_readl(&anatop->usb1_pll_480_ctrl);
309 if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
311 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
313 return infreq * (20 + div * 2);
315 div = __raw_readl(&anatop->pll_audio);
316 if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
318 div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
322 div = __raw_readl(&anatop->pll_video);
323 if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
325 div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
329 div = __raw_readl(&anatop->pll_enet);
330 if (div & BM_ANADIG_PLL_ENET_BYPASS)
332 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
334 return 25000000 * (div + (div >> 1) + 1);
336 div = __raw_readl(&anatop->usb2_pll_480_ctrl);
337 if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS)
339 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
341 return infreq * (20 + div * 2);
343 div = __raw_readl(&anatop->pll_mlb);
344 if (div & BM_ANADIG_PLL_MLB_BYPASS)
346 /* unknown external clock provided on MLB_CLK pin */
351 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
358 if (!is_cpu_type(MXC_CPU_MX6UL)) {
360 /* No PFD3 on PPL2 */
364 div = __raw_readl(&anatop->pfd_528);
365 freq = (u64)decode_pll(PLL_528, MXC_HCLK);
368 div = __raw_readl(&anatop->pfd_480);
369 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
372 /* No PFD on other PLL */
376 return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
377 ANATOP_PFD_FRAC_SHIFT(pfd_num));
380 static u32 get_mcu_main_clk(void)
384 reg = __raw_readl(&imx_ccm->cacrr);
385 reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
386 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
387 freq = decode_pll(PLL_ARM, MXC_HCLK);
389 return freq / (reg + 1);
392 u32 get_periph_clk(void)
394 u32 reg, div = 0, freq = 0;
396 reg = __raw_readl(&imx_ccm->cbcdr);
397 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
398 div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
399 MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
400 reg = __raw_readl(&imx_ccm->cbcmr);
401 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
402 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
406 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
414 reg = __raw_readl(&imx_ccm->cbcmr);
415 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
416 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
420 freq = decode_pll(PLL_528, MXC_HCLK);
423 freq = mxc_get_pll_pfd(PLL_528, 2);
426 freq = mxc_get_pll_pfd(PLL_528, 0);
429 /* static / 2 divider */
430 freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
435 return freq / (div + 1);
438 static u32 get_ipg_clk(void)
442 reg = __raw_readl(&imx_ccm->cbcdr);
443 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
444 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
446 return get_ahb_clk() / (ipg_podf + 1);
449 static u32 get_ipg_per_clk(void)
451 u32 reg, perclk_podf;
453 reg = __raw_readl(&imx_ccm->cscmr1);
454 if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
455 is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
456 if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
457 return MXC_HCLK; /* OSC 24Mhz */
460 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
462 return get_ipg_clk() / (perclk_podf + 1);
465 static u32 get_uart_clk(void)
468 u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
469 reg = __raw_readl(&imx_ccm->cscdr1);
471 if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
472 is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
473 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
477 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
478 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
480 return freq / (uart_podf + 1);
483 static u32 get_cspi_clk(void)
487 reg = __raw_readl(&imx_ccm->cscdr2);
488 cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
489 MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
491 if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
492 is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
493 if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
494 return MXC_HCLK / (cspi_podf + 1);
497 return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
500 static u32 get_axi_clk(void)
502 u32 root_freq, axi_podf;
503 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
505 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
506 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
508 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
509 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
510 root_freq = mxc_get_pll_pfd(PLL_528, 2);
512 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
514 root_freq = get_periph_clk();
516 return root_freq / (axi_podf + 1);
519 static u32 get_emi_slow_clk(void)
521 u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
523 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
524 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
525 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
526 emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
527 emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
529 switch (emi_clk_sel) {
531 root_freq = get_axi_clk();
534 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
537 root_freq = mxc_get_pll_pfd(PLL_528, 2);
540 root_freq = mxc_get_pll_pfd(PLL_528, 0);
544 return root_freq / (emi_slow_podf + 1);
547 static u32 get_nfc_clk(void)
549 u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
550 u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
551 u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
552 int nfc_clk_sel = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >>
553 MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
556 switch (nfc_clk_sel) {
558 root_freq = mxc_get_pll_pfd(PLL_528, 0);
561 root_freq = decode_pll(PLL_528, MXC_HCLK);
564 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
567 root_freq = mxc_get_pll_pfd(PLL_528, 2);
573 return root_freq / (pred + 1) / (podf + 1);
576 #define CS2CDR_ENFC_MASK (MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | \
577 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | \
578 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK)
580 static int set_nfc_clk(u32 ref, u32 freq_khz)
582 u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr);
589 u32 freq = freq_khz * 1000;
591 for (nfc_clk_sel = 0; nfc_clk_sel < 4; nfc_clk_sel++) {
595 if (ref < 4 && ref != nfc_clk_sel)
598 switch (nfc_clk_sel) {
600 root_freq = mxc_get_pll_pfd(PLL_528, 0);
603 root_freq = decode_pll(PLL_528, MXC_HCLK);
606 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
609 root_freq = mxc_get_pll_pfd(PLL_528, 2);
612 if (root_freq < freq)
615 podf = min(DIV_ROUND_UP(root_freq, freq), 1U << 6);
616 pred = min(DIV_ROUND_UP(root_freq / podf, freq), 8U);
617 act_freq = root_freq / pred / podf;
618 err = (freq - act_freq) * 100 / freq;
619 debug("root=%d[%u] freq=%u pred=%u podf=%u act=%u err=%d\n",
620 nfc_clk_sel, root_freq, freq, pred, podf, act_freq, err);
624 nfc_val = (podf - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
625 nfc_val |= (pred - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
626 nfc_val |= nfc_clk_sel << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
633 if (nfc_val == ~0 || min_err > 10)
636 if ((cs2cdr & CS2CDR_ENFC_MASK) != nfc_val) {
637 debug("changing cs2cdr from %08x to %08x\n", cs2cdr,
638 (cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val);
639 __raw_writel((cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val,
642 debug("Leaving cs2cdr unchanged [%08x]\n", cs2cdr);
647 static u32 get_mmdc_ch0_clk(void)
649 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
650 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
652 u32 freq, podf, per2_clk2_podf;
654 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
655 is_cpu_type(MXC_CPU_MX6SL)) {
656 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
657 MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
658 if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
659 per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
660 MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
661 if (is_cpu_type(MXC_CPU_MX6SL)) {
662 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
665 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
667 if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
668 freq = decode_pll(PLL_528, MXC_HCLK);
670 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
675 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
676 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
678 freq = decode_pll(PLL_528, MXC_HCLK);
681 freq = mxc_get_pll_pfd(PLL_528, 2);
684 freq = mxc_get_pll_pfd(PLL_528, 0);
687 /* static / 2 divider */
688 freq = mxc_get_pll_pfd(PLL_528, 2) / 2;
692 return freq / (podf + 1) / (per2_clk2_podf + 1);
694 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
695 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
696 return get_periph_clk() / (podf + 1);
700 #ifdef CONFIG_FSL_QSPI
701 /* qspi_num can be from 0 - 1 */
702 void enable_qspi_clk(int qspi_num)
705 /* Enable QuadSPI clock */
708 /* disable the clock gate */
709 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
711 /* set 50M : (50 = 396 / 2 / 4) */
712 reg = readl(&imx_ccm->cscmr1);
713 reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
714 MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
715 reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
716 (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
717 writel(reg, &imx_ccm->cscmr1);
719 /* enable the clock gate */
720 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
724 * disable the clock gate
725 * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
726 * disable both of them.
728 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
729 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
731 /* set 50M : (50 = 396 / 2 / 4) */
732 reg = readl(&imx_ccm->cs2cdr);
733 reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
734 MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
735 MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
736 reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
737 MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
738 writel(reg, &imx_ccm->cs2cdr);
740 /*enable the clock gate*/
741 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
742 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
750 #ifdef CONFIG_FEC_MXC
751 int enable_fec_anatop_clock(enum enet_freq freq)
754 s32 timeout = 100000;
756 if (freq < ENET_25MHZ || freq > ENET_125MHZ)
759 reg = readl(&anatop->pll_enet);
760 reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
763 if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
764 (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
765 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
766 writel(reg, &anatop->pll_enet);
768 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
775 /* Enable FEC clock */
776 reg |= BM_ANADIG_PLL_ENET_ENABLE;
777 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
778 writel(reg, &anatop->pll_enet);
780 #ifdef CONFIG_SOC_MX6SX
782 * Set enet ahb clock to 200MHz
783 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
785 reg = readl(&imx_ccm->chsccdr);
786 reg &= ~(MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK
787 | MXC_CCM_CHSCCDR_ENET_PODF_MASK
788 | MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK);
790 reg |= (4 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET);
792 reg |= (1 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET);
793 reg |= (0 << MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET);
794 writel(reg, &imx_ccm->chsccdr);
796 /* Enable enet system clock */
797 reg = readl(&imx_ccm->CCGR3);
798 reg |= MXC_CCM_CCGR3_ENET_MASK;
799 writel(reg, &imx_ccm->CCGR3);
805 static u32 get_usdhc_clk(u32 port)
807 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
808 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
809 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
813 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
814 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
815 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
819 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
820 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
821 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
825 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
826 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
827 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
831 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
832 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
833 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
841 root_freq = mxc_get_pll_pfd(PLL_528, 0);
843 root_freq = mxc_get_pll_pfd(PLL_528, 2);
845 return root_freq / (usdhc_podf + 1);
848 u32 imx_get_uartclk(void)
850 return get_uart_clk();
853 u32 imx_get_fecclk(void)
855 return mxc_get_clock(MXC_IPG_CLK);
858 #if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
859 static int enable_enet_pll(uint32_t en)
862 s32 timeout = 100000;
865 reg = readl(&anatop->pll_enet);
866 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
867 writel(reg, &anatop->pll_enet);
868 reg |= BM_ANADIG_PLL_ENET_ENABLE;
870 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
875 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
876 writel(reg, &anatop->pll_enet);
878 writel(reg, &anatop->pll_enet);
883 #ifdef CONFIG_CMD_SATA
884 static void ungate_sata_clock(void)
886 /* Enable SATA clock. */
887 setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
890 int enable_sata_clock(void)
893 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
896 void disable_sata_clock(void)
898 clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
902 #ifdef CONFIG_PCIE_IMX
903 static void ungate_pcie_clock(void)
905 /* Enable PCIe clock. */
906 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
909 int enable_pcie_clock(void)
916 * The register ANATOP_MISC1 is not documented in the Freescale
917 * MX6RM. The register that is mapped in the ANATOP space and
918 * marked as ANATOP_MISC1 is actually documented in the PMU section
919 * of the datasheet as PMU_MISC1.
921 * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on
922 * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important
923 * for PCI express link that is clocked from the i.MX6.
925 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
926 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
927 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
928 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF 0xa
929 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF 0xb
931 if (is_cpu_type(MXC_CPU_MX6SX))
932 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
934 lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
936 clrsetbits_le32(&anatop_regs->ana_misc1,
937 ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
938 ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
939 ANADIG_ANA_MISC1_LVDSCLK1_OBEN | lvds1_clk_sel);
941 /* PCIe reference clock sourced from AXI. */
942 clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
944 /* Party time! Ungate the clock to the PCIe. */
945 #ifdef CONFIG_CMD_SATA
950 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
951 BM_ANADIG_PLL_ENET_ENABLE_PCIE);
955 #ifdef CONFIG_SECURE_BOOT
956 void hab_caam_clock_enable(unsigned char enable)
960 /* CG4 ~ CG6, CAAM clocks */
961 reg = __raw_readl(&imx_ccm->CCGR0);
963 reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
964 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
965 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
967 reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
968 MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
969 MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
970 __raw_writel(reg, &imx_ccm->CCGR0);
973 reg = __raw_readl(&imx_ccm->CCGR6);
975 reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
977 reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
978 __raw_writel(reg, &imx_ccm->CCGR6);
982 static void enable_pll3(void)
984 /* make sure pll3 is enabled */
985 if ((readl(&anatop->usb1_pll_480_ctrl) &
986 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
987 /* enable pll's power */
988 writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
989 &anatop->usb1_pll_480_ctrl_set);
990 writel(0x80, &anatop->ana_misc2_clr);
991 /* wait for pll lock */
992 while ((readl(&anatop->usb1_pll_480_ctrl) &
993 BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
996 writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
997 &anatop->usb1_pll_480_ctrl_clr);
998 /* enable pll output */
999 writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
1000 &anatop->usb1_pll_480_ctrl_set);
1004 void enable_thermal_clk(void)
1009 void ipu_clk_enable(void)
1011 u32 reg = readl(&imx_ccm->CCGR3);
1012 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1013 writel(reg, &imx_ccm->CCGR3);
1016 void ipu_clk_disable(void)
1018 u32 reg = readl(&imx_ccm->CCGR3);
1019 reg &= ~MXC_CCM_CCGR3_IPU1_IPU_MASK;
1020 writel(reg, &imx_ccm->CCGR3);
1023 void ipu_di_clk_enable(int di)
1027 setbits_le32(&imx_ccm->CCGR3,
1028 MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1031 setbits_le32(&imx_ccm->CCGR3,
1032 MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1035 printf("%s: Invalid DI index %d\n", __func__, di);
1039 void ipu_di_clk_disable(int di)
1043 clrbits_le32(&imx_ccm->CCGR3,
1044 MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
1047 clrbits_le32(&imx_ccm->CCGR3,
1048 MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK);
1051 printf("%s: Invalid DI index %d\n", __func__, di);
1055 void ldb_clk_enable(int ldb)
1059 setbits_le32(&imx_ccm->CCGR3,
1060 MXC_CCM_CCGR3_LDB_DI0_MASK);
1063 setbits_le32(&imx_ccm->CCGR3,
1064 MXC_CCM_CCGR3_LDB_DI1_MASK);
1067 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1071 void ldb_clk_disable(int ldb)
1075 clrbits_le32(&imx_ccm->CCGR3,
1076 MXC_CCM_CCGR3_LDB_DI0_MASK);
1079 clrbits_le32(&imx_ccm->CCGR3,
1080 MXC_CCM_CCGR3_LDB_DI1_MASK);
1083 printf("%s: Invalid LDB index %d\n", __func__, ldb);
1087 unsigned int mxc_get_clock(enum mxc_clock clk)
1091 return get_mcu_main_clk();
1093 return get_periph_clk();
1095 return get_ahb_clk();
1097 return get_ipg_clk();
1098 case MXC_IPG_PERCLK:
1100 return get_ipg_per_clk();
1102 return get_uart_clk();
1104 return get_cspi_clk();
1106 return get_axi_clk();
1107 case MXC_EMI_SLOW_CLK:
1108 return get_emi_slow_clk();
1110 return get_mmdc_ch0_clk();
1112 return get_usdhc_clk(0);
1113 case MXC_ESDHC2_CLK:
1114 return get_usdhc_clk(1);
1115 case MXC_ESDHC3_CLK:
1116 return get_usdhc_clk(2);
1117 case MXC_ESDHC4_CLK:
1118 return get_usdhc_clk(3);
1120 return get_ahb_clk();
1122 return get_nfc_clk();
1124 printf("Unsupported MXC CLK: %d\n", clk);
1130 static inline int gcd(int m, int n)
1144 /* Config CPU clock */
1145 static int set_arm_clk(u32 ref, u32 freq_khz)
1153 if (freq_khz > ref / 1000 * 108 / 2 || freq_khz < ref / 1000 * 54 / 8 / 2) {
1154 printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03u\n",
1155 freq_khz / 1000, freq_khz % 1000,
1156 54 * ref / 1000000 / 8 / 2, 54 * ref / 1000 / 8 / 2 % 1000,
1157 108 * ref / 1000000 / 2, 108 * ref / 1000 / 2 % 1000);
1161 for (d = DIV_ROUND_UP(648000, freq_khz); d <= 8; d++) {
1162 int m = freq_khz * 2 * d / (ref / 1000);
1167 debug("%s@%d: d=%d m=%d\n", __func__, __LINE__,
1172 f = ref * m / d / 2;
1173 if (f > freq_khz * 1000) {
1174 debug("%s@%d: d=%d m=%d f=%u freq=%u\n", __func__, __LINE__,
1178 f = ref * m / d / 2;
1180 err = freq_khz * 1000 - f;
1181 debug("%s@%d: d=%d m=%d f=%u freq=%u err=%d\n", __func__, __LINE__,
1182 d, m, f, freq_khz, err);
1183 if (err < min_err) {
1193 debug("Setting M=%3u D=%2u for %u.%03uMHz (actual: %u.%03uMHz)\n",
1194 mul, div, freq_khz / 1000, freq_khz % 1000,
1195 ref * mul / 2 / div / 1000000, ref * mul / 2 / div / 1000 % 1000);
1197 reg = readl(&anatop->pll_arm);
1198 debug("anadig_pll_arm=%08x -> %08x\n",
1199 reg, (reg & ~0x7f) | mul);
1202 writel(reg, &anatop->pll_arm); /* bypass PLL */
1204 reg = (reg & ~0x7f) | mul;
1205 writel(reg, &anatop->pll_arm);
1207 writel(div - 1, &imx_ccm->cacrr);
1210 writel(reg, &anatop->pll_arm); /* disable PLL bypass */
1216 * This function assumes the expected core clock has to be changed by
1217 * modifying the PLL. This is NOT true always but for most of the times,
1218 * it is. So it assumes the PLL output freq is the same as the expected
1219 * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
1220 * In the latter case, it will try to increase the presc value until
1221 * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
1222 * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
1223 * on the targeted PLL and reference input clock to the PLL. Lastly,
1224 * it sets the register based on these values along with the dividers.
1225 * Note 1) There is no value checking for the passed-in divider values
1226 * so the caller has to make sure those values are sensible.
1227 * 2) Also adjust the NFC divider such that the NFC clock doesn't
1228 * exceed NFC_CLK_MAX.
1229 * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
1230 * 177MHz for higher voltage, this function fixes the max to 133MHz.
1231 * 4) This function should not have allowed diag_printf() calls since
1232 * the serial driver has been stoped. But leave then here to allow
1233 * easy debugging by NOT calling the cyg_hal_plf_serial_stop().
1235 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
1243 ret = set_arm_clk(ref, freq);
1247 ret = set_nfc_clk(ref, freq);
1251 printf("Warning: Unsupported or invalid clock type: %d\n",
1260 * Dump some core clocks.
1262 #define print_pll(pll) { \
1263 u32 __pll = decode_pll(pll, MXC_HCLK); \
1264 printf("%-12s %4d.%03d MHz\n", #pll, \
1265 __pll / 1000000, __pll / 1000 % 1000); \
1268 #define MXC_IPG_PER_CLK MXC_IPG_PERCLK
1270 #define print_clk(clk) { \
1271 u32 __clk = mxc_get_clock(MXC_##clk##_CLK); \
1272 printf("%-12s %4d.%03d MHz\n", #clk, \
1273 __clk / 1000000, __clk / 1000 % 1000); \
1276 #define print_pfd(pll, pfd) { \
1277 u32 __pfd = readl(&anatop->pfd_##pll); \
1278 if (__pfd & (0x80 << 8 * pfd)) { \
1279 printf("PFD_%s[%d] OFF\n", #pll, pfd); \
1281 __pfd = (__pfd >> 8 * pfd) & 0x3f; \
1282 printf("PFD_%s[%d] %4d.%03d MHz\n", #pll, pfd, \
1284 pll * 18 * 1000 / __pfd % 1000); \
1288 static void do_mx6_showclocks(void)
1292 print_pll(PLL_USBOTG);
1293 print_pll(PLL_AUDIO);
1294 print_pll(PLL_VIDEO);
1295 print_pll(PLL_ENET);
1296 print_pll(PLL_USB2);
1318 print_clk(EMI_SLOW);
1324 static struct clk_lookup {
1327 } mx6_clk_lookup[] = {
1328 { "arm", MXC_ARM_CLK, },
1329 { "nfc", MXC_NFC_CLK, },
1332 int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
1336 unsigned long ref = ~0UL;
1339 do_mx6_showclocks();
1340 return CMD_RET_SUCCESS;
1341 } else if (argc == 2 || argc > 4) {
1342 return CMD_RET_USAGE;
1345 freq = simple_strtoul(argv[2], NULL, 0);
1347 printf("Invalid clock frequency %lu\n", freq);
1348 return CMD_RET_FAILURE;
1351 ref = simple_strtoul(argv[3], NULL, 0);
1353 for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1354 if (strcasecmp(argv[1], mx6_clk_lookup[i].name) == 0) {
1355 switch (mx6_clk_lookup[i].index) {
1358 return CMD_RET_USAGE;
1363 if (argc > 3 && ref > 3) {
1364 printf("Invalid clock selector value: %lu\n", ref);
1365 return CMD_RET_FAILURE;
1369 printf("Setting %s clock to %lu MHz\n",
1370 mx6_clk_lookup[i].name, freq);
1371 if (mxc_set_clock(ref, freq, mx6_clk_lookup[i].index))
1373 freq = mxc_get_clock(mx6_clk_lookup[i].index);
1374 printf("%s clock set to %lu.%03lu MHz\n",
1375 mx6_clk_lookup[i].name,
1376 freq / 1000000, freq / 1000 % 1000);
1377 return CMD_RET_SUCCESS;
1380 if (i == ARRAY_SIZE(mx6_clk_lookup)) {
1381 printf("clock %s not found; supported clocks are:\n", argv[1]);
1382 for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) {
1383 printf("\t%s\n", mx6_clk_lookup[i].name);
1386 printf("Failed to set clock %s to %s MHz\n",
1389 return CMD_RET_FAILURE;
1392 #ifndef CONFIG_SOC_MX6SX
1393 void enable_ipu_clock(void)
1395 int reg = readl(&imx_ccm->CCGR3);
1396 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
1397 writel(reg, &imx_ccm->CCGR3);
1400 setbits_le32(&imx_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
1401 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
1405 /***************************************************/
1408 clocks, 4, 0, do_clocks,
1409 "display/set clocks",
1410 " - display clock settings\n"
1411 "clocks <clkname> <freq> - set clock <clkname> to <freq> MHz"