arch/arm/cpu/armv7/omap4/sdram_elpida.c

   1 /*
   2  * Timing and Organization details of the Elpida parts used in OMAP4
   3  * SDPs and Panda
   4  *
   5  * (C) Copyright 2010
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Aneesh V <aneesh@ti.com>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #include <asm/emif.h>
  30 #include <asm/arch/sys_proto.h>
  31
  32 /*
  33  * This file provides details of the LPDDR2 SDRAM parts used on OMAP4430
  34  * SDP and Panda. Since the parts used and geometry are identical for
  35  * SDP and Panda for a given OMAP4 revision, this information is kept
  36  * here instead of being in board directory. However the key functions
  37  * exported are weakly linked so that they can be over-ridden in the board
  38  * directory if there is a OMAP4 board in the future that uses a different
  39  * memory device or geometry.
  40  *
  41  * For any new board with different memory devices over-ride one or more
  42  * of the following functions as per the CONFIG flags you intend to enable:
  43  * - emif_get_reg_dump()
  44  * - emif_get_dmm_regs()
  45  * - emif_get_device_details()
  46  * - emif_get_device_timings()
  47  */
  48
  49 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  50
  51 static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
  52         .sdram_config_init              = 0x80000eb9,
  53         .sdram_config                   = 0x80001ab9,
  54         .ref_ctrl                       = 0x0000030c,
  55         .sdram_tim1                     = 0x08648311,
  56         .sdram_tim2                     = 0x101b06ca,
  57         .sdram_tim3                     = 0x0048a19f,
  58         .read_idle_ctrl                 = 0x000501ff,
  59         .zq_config                      = 0x500b3214,
  60         .temp_alert_config              = 0xd8016893,
  61         .emif_ddr_phy_ctlr_1_init       = 0x049ffff5,
  62         .emif_ddr_phy_ctlr_1            = 0x049ff808
  63 };
  64
  65 static const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
  66         .sdram_config_init              = 0x80000eb1,
  67         .sdram_config                   = 0x80001ab1,
  68         .ref_ctrl                       = 0x000005cd,
  69         .sdram_tim1                     = 0x10cb0622,
  70         .sdram_tim2                     = 0x20350d52,
  71         .sdram_tim3                     = 0x00b1431f,
  72         .read_idle_ctrl                 = 0x000501ff,
  73         .zq_config                      = 0x500b3214,
  74         .temp_alert_config              = 0x58016893,
  75         .emif_ddr_phy_ctlr_1_init       = 0x049ffff5,
  76         .emif_ddr_phy_ctlr_1            = 0x049ff418
  77 };
  78
  79 const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
  80         .sdram_config_init              = 0x80000eb9,
  81         .sdram_config                   = 0x80001ab9,
  82         .ref_ctrl                       = 0x00000618,
  83         .sdram_tim1                     = 0x10eb0662,
  84         .sdram_tim2                     = 0x20370dd2,
  85         .sdram_tim3                     = 0x00b1c33f,
  86         .read_idle_ctrl                 = 0x000501ff,
  87         .zq_config                      = 0xd00b3214,
  88         .temp_alert_config              = 0xd8016893,
  89         .emif_ddr_phy_ctlr_1_init       = 0x049ffff5,
  90         .emif_ddr_phy_ctlr_1            = 0x049ff418
  91 };
  92
  93 /* Dummy registers for OMAP44xx */
  94 const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
  95 const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
  96
  97 const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
  98         .dmm_lisa_map_0 = 0xFF020100,
  99         .dmm_lisa_map_1 = 0,
 100         .dmm_lisa_map_2 = 0,
 101         .dmm_lisa_map_3 = 0x80540300
 102 };
 103
 104 const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
 105         .dmm_lisa_map_0 = 0xFF020100,
 106         .dmm_lisa_map_1 = 0,
 107         .dmm_lisa_map_2 = 0,
 108         .dmm_lisa_map_3 = 0x80640300
 109 };
 110
 111 static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 112 {
 113         u32 omap4_rev = omap_revision();
 114
 115         /* Same devices and geometry on both EMIFs */
 116         if (omap4_rev == OMAP4430_ES1_0)
 117                 *regs = &emif_regs_elpida_380_mhz_1cs;
 118         else if (omap4_rev == OMAP4430_ES2_0)
 119                 *regs = &emif_regs_elpida_200_mhz_2cs;
 120         else
 121                 *regs = &emif_regs_elpida_400_mhz_2cs;
 122 }
 123 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 124         __attribute__((weak, alias("emif_get_reg_dump_sdp")));
 125
 126 static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 127                                                 **dmm_lisa_regs)
 128 {
 129         u32 omap_rev = omap_revision();
 130
 131         if (omap_rev == OMAP4430_ES1_0)
 132                 *dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
 133         else
 134                 *dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
 135 }
 136
 137 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 138         __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
 139
 140 #else
 141
 142 static const struct lpddr2_device_details elpida_2G_S4_details = {
 143         .type           = LPDDR2_TYPE_S4,
 144         .density        = LPDDR2_DENSITY_2Gb,
 145         .io_width       = LPDDR2_IO_WIDTH_32,
 146         .manufacturer   = LPDDR2_MANUFACTURER_ELPIDA
 147 };
 148
 149 struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs,
 150                         struct lpddr2_device_details *lpddr2_dev_details)
 151 {
 152         u32 omap_rev = omap_revision();
 153
 154         /* EMIF1 & EMIF2 have identical configuration */
 155         if ((omap_rev == OMAP4430_ES1_0) && (cs == CS1)) {
 156                 /* Nothing connected on CS1 for ES1.0 */
 157                 return NULL;
 158         } else {
 159                 /* In all other cases Elpida 2G device */
 160                 *lpddr2_dev_details = elpida_2G_S4_details;
 161                 return lpddr2_dev_details;
 162         }
 163 }
 164
 165 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
 166                         struct lpddr2_device_details *lpddr2_dev_details)
 167         __attribute__((weak, alias("emif_get_device_details_sdp")));
 168
 169 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 170
 171 #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 172 static const struct lpddr2_ac_timings timings_elpida_400_mhz = {
 173         .max_freq       = 400000000,
 174         .RL             = 6,
 175         .tRPab          = 21,
 176         .tRCD           = 18,
 177         .tWR            = 15,
 178         .tRASmin        = 42,
 179         .tRRD           = 10,
 180         .tWTRx2         = 15,
 181         .tXSR           = 140,
 182         .tXPx2          = 15,
 183         .tRFCab         = 130,
 184         .tRTPx2         = 15,
 185         .tCKE           = 3,
 186         .tCKESR         = 15,
 187         .tZQCS          = 90,
 188         .tZQCL          = 360,
 189         .tZQINIT        = 1000,
 190         .tDQSCKMAXx2    = 11,
 191         .tRASmax        = 70,
 192         .tFAW           = 50
 193 };
 194
 195 static const struct lpddr2_ac_timings timings_elpida_333_mhz = {
 196         .max_freq       = 333000000,
 197         .RL             = 5,
 198         .tRPab          = 21,
 199         .tRCD           = 18,
 200         .tWR            = 15,
 201         .tRASmin        = 42,
 202         .tRRD           = 10,
 203         .tWTRx2         = 15,
 204         .tXSR           = 140,
 205         .tXPx2          = 15,
 206         .tRFCab         = 130,
 207         .tRTPx2         = 15,
 208         .tCKE           = 3,
 209         .tCKESR         = 15,
 210         .tZQCS          = 90,
 211         .tZQCL          = 360,
 212         .tZQINIT        = 1000,
 213         .tDQSCKMAXx2    = 11,
 214         .tRASmax        = 70,
 215         .tFAW           = 50
 216 };
 217
 218 static const struct lpddr2_ac_timings timings_elpida_200_mhz = {
 219         .max_freq       = 200000000,
 220         .RL             = 3,
 221         .tRPab          = 21,
 222         .tRCD           = 18,
 223         .tWR            = 15,
 224         .tRASmin        = 42,
 225         .tRRD           = 10,
 226         .tWTRx2         = 20,
 227         .tXSR           = 140,
 228         .tXPx2          = 15,
 229         .tRFCab         = 130,
 230         .tRTPx2         = 15,
 231         .tCKE           = 3,
 232         .tCKESR         = 15,
 233         .tZQCS          = 90,
 234         .tZQCL          = 360,
 235         .tZQINIT        = 1000,
 236         .tDQSCKMAXx2    = 11,
 237         .tRASmax        = 70,
 238         .tFAW           = 50
 239 };
 240
 241 static const struct lpddr2_min_tck min_tck_elpida = {
 242         .tRL            = 3,
 243         .tRP_AB         = 3,
 244         .tRCD           = 3,
 245         .tWR            = 3,
 246         .tRAS_MIN       = 3,
 247         .tRRD           = 2,
 248         .tWTR           = 2,
 249         .tXP            = 2,
 250         .tRTP           = 2,
 251         .tCKE           = 3,
 252         .tCKESR         = 3,
 253         .tFAW           = 8
 254 };
 255
 256 static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = {
 257                 &timings_elpida_200_mhz,
 258                 &timings_elpida_333_mhz,
 259                 &timings_elpida_400_mhz
 260 };
 261
 262 static const struct lpddr2_device_timings elpida_2G_S4_timings = {
 263         .ac_timings     = elpida_ac_timings,
 264         .min_tck        = &min_tck_elpida,
 265 };
 266
 267 void emif_get_device_timings_sdp(u32 emif_nr,
 268                 const struct lpddr2_device_timings **cs0_device_timings,
 269                 const struct lpddr2_device_timings **cs1_device_timings)
 270 {
 271         u32 omap_rev = omap_revision();
 272
 273         /* Identical devices on EMIF1 & EMIF2 */
 274         *cs0_device_timings = &elpida_2G_S4_timings;
 275
 276         if (omap_rev == OMAP4430_ES1_0)
 277                 *cs1_device_timings = NULL;
 278         else
 279                 *cs1_device_timings = &elpida_2G_S4_timings;
 280 }
 281
 282 void emif_get_device_timings(u32 emif_nr,
 283                 const struct lpddr2_device_timings **cs0_device_timings,
 284                 const struct lpddr2_device_timings **cs1_device_timings)
 285         __attribute__((weak, alias("emif_get_device_timings_sdp")));
 286
 287 #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */