arch/arm/cpu/pxa/pxafb.c

   1 /*
   2  * PXA LCD Controller
   3  *
   4  * (C) Copyright 2001-2002
   5  * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 /************************************************************************/
  27 /* ** HEADER FILES                                                      */
  28 /************************************************************************/
  29
  30 #include <config.h>
  31 #include <common.h>
  32 #include <version.h>
  33 #include <stdarg.h>
  34 #include <linux/types.h>
  35 #include <stdio_dev.h>
  36 #include <lcd.h>
  37 #include <asm/arch/pxa-regs.h>
  38
  39 /* #define DEBUG */
  40
  41 #ifdef CONFIG_LCD
  42
  43 /*----------------------------------------------------------------------*/
  44 /*
  45  * Define panel bpp, LCCR0, LCCR3 and panel_info video struct for
  46  * your display.
  47  */
  48
  49 #ifdef CONFIG_PXA_VGA
  50 /* LCD outputs connected to a video DAC  */
  51 # define LCD_BPP        LCD_COLOR8
  52
  53 /* you have to set lccr0 and lccr3 (including pcd) */
  54 # define REG_LCCR0      0x003008f8
  55 # define REG_LCCR3      0x0300FF01
  56
  57 /* 640x480x16 @ 61 Hz */
  58 vidinfo_t panel_info = {
  59         vl_col:         640,
  60         vl_row:         480,
  61         vl_width:       640,
  62         vl_height:      480,
  63         vl_clkp:        CONFIG_SYS_HIGH,
  64         vl_oep:         CONFIG_SYS_HIGH,
  65         vl_hsp:         CONFIG_SYS_HIGH,
  66         vl_vsp:         CONFIG_SYS_HIGH,
  67         vl_dp:          CONFIG_SYS_HIGH,
  68         vl_bpix:        LCD_BPP,
  69         vl_lbw:         0,
  70         vl_splt:        0,
  71         vl_clor:        0,
  72         vl_tft:         1,
  73         vl_hpw:         40,
  74         vl_blw:         56,
  75         vl_elw:         56,
  76         vl_vpw:         20,
  77         vl_bfw:         8,
  78         vl_efw:         8,
  79 };
  80 #endif /* CONFIG_PXA_VIDEO */
  81
  82 /*----------------------------------------------------------------------*/
  83 #ifdef CONFIG_SHARP_LM8V31
  84
  85 # define LCD_BPP        LCD_COLOR8
  86 # define LCD_INVERT_COLORS      /* Needed for colors to be correct, but why?    */
  87
  88 /* you have to set lccr0 and lccr3 (including pcd) */
  89 # define REG_LCCR0      0x0030087C
  90 # define REG_LCCR3      0x0340FF08
  91
  92 vidinfo_t panel_info = {
  93         vl_col:         640,
  94         vl_row:         480,
  95         vl_width:       157,
  96         vl_height:      118,
  97         vl_clkp:        CONFIG_SYS_HIGH,
  98         vl_oep:         CONFIG_SYS_HIGH,
  99         vl_hsp:         CONFIG_SYS_HIGH,
 100         vl_vsp:         CONFIG_SYS_HIGH,
 101         vl_dp:          CONFIG_SYS_HIGH,
 102         vl_bpix:        LCD_BPP,
 103         vl_lbw:         0,
 104         vl_splt:        1,
 105         vl_clor:        1,
 106         vl_tft:         0,
 107         vl_hpw:         1,
 108         vl_blw:         3,
 109         vl_elw:         3,
 110         vl_vpw:         1,
 111         vl_bfw:         0,
 112         vl_efw:         0,
 113 };
 114 #endif /* CONFIG_SHARP_LM8V31 */
 115 /*----------------------------------------------------------------------*/
 116 #ifdef CONFIG_VOIPAC_LCD
 117
 118 # define LCD_BPP        LCD_COLOR8
 119 # define LCD_INVERT_COLORS
 120
 121 /* you have to set lccr0 and lccr3 (including pcd) */
 122 # define REG_LCCR0      0x043008f8
 123 # define REG_LCCR3      0x0340FF08
 124
 125 vidinfo_t panel_info = {
 126         vl_col:         640,
 127         vl_row:         480,
 128         vl_width:       157,
 129         vl_height:      118,
 130         vl_clkp:        CONFIG_SYS_HIGH,
 131         vl_oep:         CONFIG_SYS_HIGH,
 132         vl_hsp:         CONFIG_SYS_HIGH,
 133         vl_vsp:         CONFIG_SYS_HIGH,
 134         vl_dp:          CONFIG_SYS_HIGH,
 135         vl_bpix:        LCD_BPP,
 136         vl_lbw:         0,
 137         vl_splt:        1,
 138         vl_clor:        1,
 139         vl_tft:         1,
 140         vl_hpw:         32,
 141         vl_blw:         144,
 142         vl_elw:         32,
 143         vl_vpw:         2,
 144         vl_bfw:         13,
 145         vl_efw:         30,
 146 };
 147 #endif /* CONFIG_VOIPAC_LCD */
 148
 149 /*----------------------------------------------------------------------*/
 150 #ifdef CONFIG_HITACHI_SX14
 151 /* Hitachi SX14Q004-ZZA color STN LCD */
 152 #define LCD_BPP         LCD_COLOR8
 153
 154 /* you have to set lccr0 and lccr3 (including pcd) */
 155 #define REG_LCCR0       0x00301079
 156 #define REG_LCCR3       0x0340FF20
 157
 158 vidinfo_t panel_info = {
 159         vl_col:         320,
 160         vl_row:         240,
 161         vl_width:       167,
 162         vl_height:      109,
 163         vl_clkp:        CONFIG_SYS_HIGH,
 164         vl_oep:         CONFIG_SYS_HIGH,
 165         vl_hsp:         CONFIG_SYS_HIGH,
 166         vl_vsp:         CONFIG_SYS_HIGH,
 167         vl_dp:          CONFIG_SYS_HIGH,
 168         vl_bpix:        LCD_BPP,
 169         vl_lbw:         1,
 170         vl_splt:        0,
 171         vl_clor:        1,
 172         vl_tft:         0,
 173         vl_hpw:         1,
 174         vl_blw:         1,
 175         vl_elw:         1,
 176         vl_vpw:         7,
 177         vl_bfw:         0,
 178         vl_efw:         0,
 179 };
 180 #endif /* CONFIG_HITACHI_SX14 */
 181
 182 /*----------------------------------------------------------------------*/
 183 #ifdef CONFIG_LMS283GF05
 184
 185 # define LCD_BPP        LCD_COLOR8
 186 /*# define LCD_INVERT_COLORS*/
 187
 188 /* you have to set lccr0 and lccr3 (including pcd) */
 189 # define REG_LCCR0      0x043008f8
 190 # define REG_LCCR3      0x03b00009
 191
 192 vidinfo_t panel_info = {
 193         vl_col:         240,
 194         vl_row:         320,
 195         vl_width:       240,
 196         vl_height:      320,
 197         vl_clkp:        CONFIG_SYS_HIGH,
 198         vl_oep:         CONFIG_SYS_LOW,
 199         vl_hsp:         CONFIG_SYS_LOW,
 200         vl_vsp:         CONFIG_SYS_LOW,
 201         vl_dp:          CONFIG_SYS_HIGH,
 202         vl_bpix:        LCD_BPP,
 203         vl_lbw:         0,
 204         vl_splt:        1,
 205         vl_clor:        1,
 206         vl_tft:         1,
 207         vl_hpw:         4,
 208         vl_blw:         4,
 209         vl_elw:         8,
 210         vl_vpw:         4,
 211         vl_bfw:         4,
 212         vl_efw:         8,
 213 };
 214 #endif /* CONFIG_LMS283GF05 */
 215
 216 /*----------------------------------------------------------------------*/
 217
 218 #if LCD_BPP == LCD_COLOR8
 219 void lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue);
 220 #endif
 221 #if LCD_BPP == LCD_MONOCHROME
 222 void lcd_initcolregs (void);
 223 #endif
 224
 225 #ifdef NOT_USED_SO_FAR
 226 void lcd_disable (void);
 227 void lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue);
 228 #endif /* NOT_USED_SO_FAR */
 229
 230 void lcd_ctrl_init      (void *lcdbase);
 231 void lcd_enable (void);
 232
 233 int lcd_line_length;
 234 int lcd_color_fg;
 235 int lcd_color_bg;
 236
 237 void *lcd_base;                 /* Start of framebuffer memory  */
 238 void *lcd_console_address;              /* Start of console buffer      */
 239
 240 short console_col;
 241 short console_row;
 242
 243 static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid);
 244 static void pxafb_setup_gpio (vidinfo_t *vid);
 245 static void pxafb_enable_controller (vidinfo_t *vid);
 246 static int pxafb_init (vidinfo_t *vid);
 247 /************************************************************************/
 248
 249 /************************************************************************/
 250 /* ---------------  PXA chipset specific functions  ------------------- */
 251 /************************************************************************/
 252
 253 void lcd_ctrl_init (void *lcdbase)
 254 {
 255         pxafb_init_mem(lcdbase, &panel_info);
 256         pxafb_init(&panel_info);
 257         pxafb_setup_gpio(&panel_info);
 258         pxafb_enable_controller(&panel_info);
 259 }
 260
 261 /*----------------------------------------------------------------------*/
 262 #ifdef NOT_USED_SO_FAR
 263 void
 264 lcd_getcolreg (ushort regno, ushort *red, ushort *green, ushort *blue)
 265 {
 266 }
 267 #endif /* NOT_USED_SO_FAR */
 268
 269 /*----------------------------------------------------------------------*/
 270 #if LCD_BPP == LCD_COLOR8
 271 void
 272 lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
 273 {
 274         struct pxafb_info *fbi = &panel_info.pxa;
 275         unsigned short *palette = (unsigned short *)fbi->palette;
 276         u_int val;
 277
 278         if (regno < fbi->palette_size) {
 279                 val = ((red << 8) & 0xf800);
 280                 val |= ((green << 4) & 0x07e0);
 281                 val |= (blue & 0x001f);
 282
 283 #ifdef LCD_INVERT_COLORS
 284                 palette[regno] = ~val;
 285 #else
 286                 palette[regno] = val;
 287 #endif
 288         }
 289
 290         debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n",
 291                 regno, &palette[regno],
 292                 red, green, blue,
 293                 palette[regno]);
 294 }
 295 #endif /* LCD_COLOR8 */
 296
 297 /*----------------------------------------------------------------------*/
 298 #if LCD_BPP == LCD_MONOCHROME
 299 void lcd_initcolregs (void)
 300 {
 301         struct pxafb_info *fbi = &panel_info.pxa;
 302         cmap = (ushort *)fbi->palette;
 303         ushort regno;
 304
 305         for (regno = 0; regno < 16; regno++) {
 306                 cmap[regno * 2] = 0;
 307                 cmap[(regno * 2) + 1] = regno & 0x0f;
 308         }
 309 }
 310 #endif /* LCD_MONOCHROME */
 311
 312 /*----------------------------------------------------------------------*/
 313 void lcd_enable (void)
 314 {
 315 }
 316
 317 /*----------------------------------------------------------------------*/
 318 #ifdef  NOT_USED_SO_FAR
 319 static void lcd_disable (void)
 320 {
 321 }
 322 #endif /* NOT_USED_SO_FAR */
 323
 324 /*----------------------------------------------------------------------*/
 325
 326 /************************************************************************/
 327 /* ** PXA255 specific routines                                          */
 328 /************************************************************************/
 329
 330 /*
 331  * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb,
 332  * descriptors and palette areas.
 333  */
 334 ulong calc_fbsize (void)
 335 {
 336         ulong size;
 337         int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
 338
 339         size = line_length * panel_info.vl_row;
 340         size += PAGE_SIZE;
 341
 342         return size;
 343 }
 344
 345 static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
 346 {
 347         u_long palette_mem_size;
 348         struct pxafb_info *fbi = &vid->pxa;
 349         int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
 350
 351         fbi->screen = (u_long)lcdbase;
 352
 353         fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
 354         palette_mem_size = fbi->palette_size * sizeof(u16);
 355
 356         debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
 357         /* locate palette and descs at end of page following fb */
 358         fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
 359
 360         return 0;
 361 }
 362 #ifdef  CONFIG_CPU_MONAHANS
 363 static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
 364 #else
 365 static void pxafb_setup_gpio (vidinfo_t *vid)
 366 {
 367         u_long lccr0;
 368
 369         /*
 370          * setup is based on type of panel supported
 371          */
 372
 373         lccr0 = vid->pxa.reg_lccr0;
 374
 375         /* 4 bit interface */
 376         if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD))
 377         {
 378                 debug("Setting GPIO for 4 bit data\n");
 379                 /* bits 58-61 */
 380                 GPDR1 |= (0xf << 26);
 381                 GAFR1_U = (GAFR1_U & ~(0xff << 20)) | (0xaa << 20);
 382
 383                 /* bits 74-77 */
 384                 GPDR2 |= (0xf << 10);
 385                 GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
 386         }
 387
 388         /* 8 bit interface */
 389         else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) ||
 390                 (!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS)))
 391         {
 392                 debug("Setting GPIO for 8 bit data\n");
 393                 /* bits 58-65 */
 394                 GPDR1 |= (0x3f << 26);
 395                 GPDR2 |= (0x3);
 396
 397                 GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
 398                 GAFR2_L = (GAFR2_L & ~0xf) | (0xa);
 399
 400                 /* bits 74-77 */
 401                 GPDR2 |= (0xf << 10);
 402                 GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
 403         }
 404
 405         /* 16 bit interface */
 406         else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS)))
 407         {
 408                 debug("Setting GPIO for 16 bit data\n");
 409                 /* bits 58-77 */
 410                 GPDR1 |= (0x3f << 26);
 411                 GPDR2 |= 0x00003fff;
 412
 413                 GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
 414                 GAFR2_L = (GAFR2_L & 0xf0000000) | 0x0aaaaaaa;
 415         }
 416         else
 417         {
 418                 printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
 419         }
 420 }
 421 #endif
 422
 423 static void pxafb_enable_controller (vidinfo_t *vid)
 424 {
 425         debug("Enabling LCD controller\n");
 426
 427         /* Sequence from 11.7.10 */
 428         LCCR3  = vid->pxa.reg_lccr3;
 429         LCCR2  = vid->pxa.reg_lccr2;
 430         LCCR1  = vid->pxa.reg_lccr1;
 431         LCCR0  = vid->pxa.reg_lccr0 & ~LCCR0_ENB;
 432         FDADR0 = vid->pxa.fdadr0;
 433         FDADR1 = vid->pxa.fdadr1;
 434         LCCR0 |= LCCR0_ENB;
 435
 436 #ifdef  CONFIG_CPU_MONAHANS
 437         CKENA |= CKENA_1_LCD;
 438 #else
 439         CKEN |= CKEN16_LCD;
 440 #endif
 441
 442         debug("FDADR0 = 0x%08x\n", (unsigned int)FDADR0);
 443         debug("FDADR1 = 0x%08x\n", (unsigned int)FDADR1);
 444         debug("LCCR0 = 0x%08x\n", (unsigned int)LCCR0);
 445         debug("LCCR1 = 0x%08x\n", (unsigned int)LCCR1);
 446         debug("LCCR2 = 0x%08x\n", (unsigned int)LCCR2);
 447         debug("LCCR3 = 0x%08x\n", (unsigned int)LCCR3);
 448 }
 449
 450 static int pxafb_init (vidinfo_t *vid)
 451 {
 452         struct pxafb_info *fbi = &vid->pxa;
 453
 454         debug("Configuring PXA LCD\n");
 455
 456         fbi->reg_lccr0 = REG_LCCR0;
 457         fbi->reg_lccr3 = REG_LCCR3;
 458
 459         debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n",
 460                 vid->vl_col, vid->vl_hpw,
 461                 vid->vl_blw, vid->vl_elw);
 462         debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n",
 463                 vid->vl_row, vid->vl_vpw,
 464                 vid->vl_bfw, vid->vl_efw);
 465
 466         fbi->reg_lccr1 =
 467                 LCCR1_DisWdth(vid->vl_col) +
 468                 LCCR1_HorSnchWdth(vid->vl_hpw) +
 469                 LCCR1_BegLnDel(vid->vl_blw) +
 470                 LCCR1_EndLnDel(vid->vl_elw);
 471
 472         fbi->reg_lccr2 =
 473                 LCCR2_DisHght(vid->vl_row) +
 474                 LCCR2_VrtSnchWdth(vid->vl_vpw) +
 475                 LCCR2_BegFrmDel(vid->vl_bfw) +
 476                 LCCR2_EndFrmDel(vid->vl_efw);
 477
 478         fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP);
 479         fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH)
 480                         | (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH);
 481
 482
 483         /* setup dma descriptors */
 484         fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
 485         fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
 486         fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);
 487
 488         #define BYTES_PER_PANEL ((fbi->reg_lccr0 & LCCR0_SDS) ? \
 489                 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \
 490                 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8))
 491
 492         /* populate descriptors */
 493         fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow;
 494         fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL;
 495         fbi->dmadesc_fblow->fidr  = 0;
 496         fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL;
 497
 498         fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */
 499
 500         fbi->dmadesc_fbhigh->fsadr = fbi->screen;
 501         fbi->dmadesc_fbhigh->fidr = 0;
 502         fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL;
 503
 504         fbi->dmadesc_palette->fsadr = fbi->palette;
 505         fbi->dmadesc_palette->fidr  = 0;
 506         fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
 507
 508         if( NBITS(vid->vl_bpix) < 12)
 509         {
 510                 /* assume any mode with <12 bpp is palette driven */
 511                 fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh;
 512                 fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette;
 513                 /* flips back and forth between pal and fbhigh */
 514                 fbi->fdadr0 = (u_long)fbi->dmadesc_palette;
 515         }
 516         else
 517         {
 518                 /* palette shouldn't be loaded in true-color mode */
 519                 fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh;
 520                 fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */
 521         }
 522
 523         debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow);
 524         debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh);
 525         debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette);
 526
 527         debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr);
 528         debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr);
 529         debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr);
 530
 531         debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr);
 532         debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr);
 533         debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr);
 534
 535         debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd);
 536         debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd);
 537         debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd);
 538
 539         return 0;
 540 }
 541
 542 /************************************************************************/
 543 /************************************************************************/
 544
 545 #endif /* CONFIG_LCD */