2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
21 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
28 u32 cacrr; /* 0x0010*/
32 u32 cscmr2; /* 0x0020 */
36 u32 cdcdr; /* 0x0030 */
40 u32 cscdr4; /* 0x0040 */
44 u32 ctor; /* 0x0050 */
48 u32 ccosr; /* 0x0060 */
52 u32 CCGR2; /* 0x0070 */
56 u32 CCGR6; /* 0x0080 */
61 /* Define the bits in register CCR */
62 #define MXC_CCM_CCR_RBC_EN (1 << 27)
63 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << CCR_REG_BYPASS_CNT_OFFSET)
64 #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21
65 #define MXC_CCM_CCR_WB_COUNT_MASK (0x7 << MXC_CCM_CCR_WB_COUNT_OFFSET)
66 #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
67 #define MXC_CCM_CCR_COSC_EN (1 << 12)
68 #define MXC_CCM_CCR_OSCNT_MASK (0xFF << MXC_CCM_CCR_OSCNT_OFFSET)
69 #define MXC_CCM_CCR_OSCNT_OFFSET 0
71 /* Define the bits in register CCDR */
72 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16)
73 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17)
75 /* Define the bits in register CSR */
76 #define MXC_CCM_CSR_COSC_READY (1 << 5)
77 #define MXC_CCM_CSR_REF_EN_B (1 << 0)
79 /* Define the bits in register CCSR */
80 #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15)
81 #define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14)
82 #define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13)
83 #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12)
84 #define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11)
85 #define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10)
86 #define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9)
87 #define MXC_CCM_CCSR_STEP_SEL (1 << 8)
88 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
89 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
90 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
92 /* Define the bits in register CACRR */
93 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
94 #define MXC_CCM_CACRR_ARM_PODF_MASK (0x7 << MXC_CCM_CACRR_ARM_PODF_OFFSET)
96 /* Define the bits in register CBCDR */
97 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET)
98 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
99 #define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26)
100 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
101 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET)
102 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
103 #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << MXC_CCM_CBCDR_AXI_PODF_OFFSET)
104 #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
105 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << MXC_CCM_CBCDR_AHB_PODF_OFFSET)
106 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
107 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << MXC_CCM_CBCDR_IPG_PODF_OFFSET)
108 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
109 #define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7)
110 #define MXC_CCM_CBCDR_AXI_SEL (1 << 6)
111 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET)
112 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3
113 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET)
114 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0
116 /* Define the bits in register CBCMR */
117 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET)
118 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29
119 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET)
120 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26
121 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET)
122 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
123 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET)
124 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
125 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20)
126 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET)
127 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
128 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET)
129 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16
130 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET)
131 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
132 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET)
133 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12
134 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11)
135 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10)
136 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET)
137 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8
138 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET)
139 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4
140 #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1)
141 #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0)
143 /* Define the bits in register CSCMR1 */
144 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET)
145 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
146 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET)
147 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
148 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET)
149 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
150 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET)
151 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
152 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
153 #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
154 #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
155 #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16)
156 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET)
157 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14
158 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET)
159 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
160 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET)
161 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
162 #define MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET 0
163 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK (0x3F << MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET)
165 /* Define the bits in register CSCMR2 */
166 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET)
167 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
168 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
169 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
170 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET)
171 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2
173 /* Define the bits in register CSCDR1 */
174 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET)
175 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
176 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET)
177 #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
178 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET)
179 #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19
180 #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET)
181 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16
182 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET)
183 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11
184 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
185 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET)
186 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
187 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET)
188 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
189 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
191 /* Define the bits in register CS1CDR */
192 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET)
193 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25
194 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET)
195 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16
196 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET)
197 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9
198 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET)
199 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6
200 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET)
201 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
203 /* Define the bits in register CS2CDR */
204 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET)
205 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
206 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET)
207 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
208 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET)
209 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16
210 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)
211 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
212 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
213 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9
214 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET)
215 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6
216 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET)
217 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0
219 /* Define the bits in register CDCDR */
220 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET)
221 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29
222 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28)
223 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET)
224 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25
225 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET)
226 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 19
227 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET)
228 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20
229 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET)
230 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12
231 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET)
232 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9
233 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET)
234 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7
236 /* Define the bits in register CHSCCDR */
237 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_DI1_PRE_CLK_SEL_OFFSET)
238 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15
239 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET)
240 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12
241 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET)
242 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9
243 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_DI0_PRE_CLK_SEL_OFFSET)
244 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6
245 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
246 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3
247 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
248 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
250 /* Define the bits in register CSCDR2 */
251 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET)
252 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
253 #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_DI1_PRE_CLK_SEL_OFFSET)
254 #define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
255 #define MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET)
256 #define MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET 12
257 #define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET)
258 #define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET 9
259 #define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_DI0_PRE_CLK_SEL_OFFSET)
260 #define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
261 #define MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET)
262 #define MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET 3
263 #define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET)
264 #define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET 0
266 /* Define the bits in register CSCDR3 */
267 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET)
268 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16
269 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET)
270 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14
271 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET)
272 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11
273 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET)
274 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9
276 /* Define the bits in register CDHIPR */
277 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
278 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
279 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4)
280 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3)
281 #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2)
282 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1)
283 #define MXC_CCM_CDHIPR_AXI_PODF_BUSY (1 << 0)
285 /* Define the bits in register CLPCR */
286 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27)
287 #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26)
288 #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25)
289 #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24)
290 #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23)
291 #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22)
292 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21)
293 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19)
294 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17)
295 #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 17)
296 #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11)
297 #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET)
298 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9
299 #define MXC_CCM_CLPCR_VSTBY (1 << 8)
300 #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7)
301 #define MXC_CCM_CLPCR_SBYOS (1 << 6)
302 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5)
303 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET)
304 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3
305 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2)
306 #define MXC_CCM_CLPCR_LPM_MASK (0x3 << MXC_CCM_CLPCR_LPM_OFFSET)
307 #define MXC_CCM_CLPCR_LPM_OFFSET 0
309 /* Define the bits in register CISR */
310 #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26)
311 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23)
312 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22)
313 #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21)
314 #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20)
315 #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19)
316 #define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17)
317 #define MXC_CCM_CISR_COSC_READY (1 << 6)
318 #define MXC_CCM_CISR_LRF_PLL (1 << 0)
320 /* Define the bits in register CIMR */
321 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26)
322 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23)
323 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22)
324 #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21)
325 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20)
326 #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 22)
327 #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17)
328 #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6)
329 #define MXC_CCM_CIMR_MASK_LRF_PLL (1 << 0)
331 /* Define the bits in register CCOSR */
332 #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24)
333 #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << MXC_CCM_CCOSR_CKO2_DIV_OFFSET)
334 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21
335 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16
336 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << MXC_CCM_CCOSR_CKO2_SEL_OFFSET)
337 #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
338 #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << MXC_CCM_CCOSR_CKOL_DIV_OFFSET)
339 #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4
340 #define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF << MXC_CCM_CCOSR_CKOL_SEL_OFFSET)
341 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0
343 /* Define the bits in registers CGPR */
344 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
345 #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2)
346 #define MXC_CCM_CGPR_PMIC_DELAY_SCALER (1 << 0)
348 /* Define the bits in registers CCGRx */
349 #define MXC_CCM_CCGR_CG_MASK 3
351 #define MXC_CCM_CCGR0_CG14_OFFSET 28
352 #define MXC_CCM_CCGR0_CG14_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG14_OFFSET)
353 #define MXC_CCM_CCGR0_CG13_OFFSET 26
354 #define MXC_CCM_CCGR0_CG13_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG13_OFFSET)
355 #define MXC_CCM_CCGR0_CG12_OFFSET 24
356 #define MXC_CCM_CCGR0_CG12_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG12_OFFSET)
357 #define MXC_CCM_CCGR0_CG11_OFFSET 22
358 #define MXC_CCM_CCGR0_CG11_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG11_OFFSET)
359 #define MXC_CCM_CCGR0_CG10_OFFSET 20
360 #define MXC_CCM_CCGR0_CG10_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG10_OFFSET)
361 #define MXC_CCM_CCGR0_CG9_OFFSET 18
362 #define MXC_CCM_CCGR0_CG9_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG9_OFFSET)
363 #define MXC_CCM_CCGR0_CG8_OFFSET 16
364 #define MXC_CCM_CCGR0_CG8_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG8_OFFSET)
365 #define MXC_CCM_CCGR0_CG7_OFFSET 14
366 #define MXC_CCM_CCGR0_CG6_OFFSET 12
367 #define MXC_CCM_CCGR0_CG5_OFFSET 10
368 #define MXC_CCM_CCGR0_CG5_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG5_OFFSET)
369 #define MXC_CCM_CCGR0_CG4_OFFSET 8
370 #define MXC_CCM_CCGR0_CG4_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG4_OFFSET)
371 #define MXC_CCM_CCGR0_CG3_OFFSET 6
372 #define MXC_CCM_CCGR0_CG3_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG3_OFFSET)
373 #define MXC_CCM_CCGR0_CG2_OFFSET 4
374 #define MXC_CCM_CCGR0_CG2_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG2_OFFSET)
375 #define MXC_CCM_CCGR0_CG1_OFFSET 2
376 #define MXC_CCM_CCGR0_CG1_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG1_OFFSET)
377 #define MXC_CCM_CCGR0_CG0_OFFSET 0
378 #define MXC_CCM_CCGR0_CG0_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET)
380 #define MXC_CCM_CCGR0_DTCP_OFFSET MXC_CCM_CCGR0_CG14_OFFSET
381 #define MXC_CCM_CCGR0_DCIC2_OFFSET MXC_CCM_CCGR0_CG13_OFFSET
382 #define MXC_CCM_CCGR0_DCIC1_OFFSET MXC_CCM_CCGR0_CG12_OFFSET
383 #define MXC_CCM_CCGR0_ARM_DBG_OFFSET MXC_CCM_CCGR0_CG11_OFFSET
384 #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET MXC_CCM_CCGR0_CG10_OFFSET
385 #define MXC_CCM_CCGR0_CAN2_OFFSET MXC_CCM_CCGR0_CG9_OFFSET
386 #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET MXC_CCM_CCGR0_CG8_OFFSET
387 #define MXC_CCM_CCGR0_CAN1_OFFSET MXC_CCM_CCGR0_CG7_OFFSET
388 #define MXC_CCM_CCGR0_CAAM_IPG_OFFSET MXC_CCM_CCGR0_CG6_OFFSET
389 #define MXC_CCM_CCGR0_CAAM_ACLK_OFFSET MXC_CCM_CCGR0_CG5_OFFSET
390 #define MXC_CCM_CCGR0_CAAM_SEC_MEM_OFFSET MXC_CCM_CCGR0_CG4_OFFSET
391 #define MXC_CCM_CCGR0_ASRC_OFFSET MXC_CCM_CCGR0_CG3_OFFSET
392 #define MXC_CCM_CCGR0_APBHDMA_OFFSET MXC_CCM_CCGR0_CG2_OFFSET
393 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET MXC_CCM_CCGR0_CG1_OFFSET
394 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET MXC_CCM_CCGR0_CG0_OFFSET
396 #define MXC_CCM_CCGR1_CG15_OFFSET 30
397 #define MXC_CCM_CCGR1_CG14_OFFSET 28
398 #define MXC_CCM_CCGR1_CG13_OFFSET 26
399 #define MXC_CCM_CCGR1_CG12_OFFSET 24
400 #define MXC_CCM_CCGR1_CG11_OFFSET 22
401 #define MXC_CCM_CCGR1_CG10_OFFSET 20
402 #define MXC_CCM_CCGR1_CG9_OFFSET 18
403 #define MXC_CCM_CCGR1_CG8_OFFSET 16
404 #define MXC_CCM_CCGR1_CG7_OFFSET 14
405 #define MXC_CCM_CCGR1_CG6_OFFSET 12
406 #define MXC_CCM_CCGR1_CG5_OFFSET 10
407 #define MXC_CCM_CCGR1_CG4_OFFSET 8
408 #define MXC_CCM_CCGR1_CG3_OFFSET 6
409 #define MXC_CCM_CCGR1_CG2_OFFSET 4
410 #define MXC_CCM_CCGR1_CG1_OFFSET 2
411 #define MXC_CCM_CCGR1_CG0_OFFSET 0
413 #define MXC_CCM_CCGR1_GPU3D_OFFSET MXC_CCM_CCGR1_CG13_OFFSET
414 #define MXC_CCM_CCGR1_GPU2D_OFFSET MXC_CCM_CCGR1_CG12_OFFSET
415 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET MXC_CCM_CCGR1_CG11_OFFSET
416 #define MXC_CCM_CCGR1_GPT_OFFSET MXC_CCM_CCGR1_CG10_OFFSET
417 #define MXC_CCM_CCGR1_ESAI_OFFSET MXC_CCM_CCGR1_CG8_OFFSET
418 #define MXC_CCM_CCGR1_EPIT2_OFFSET MXC_CCM_CCGR1_CG7_OFFSET
419 #define MXC_CCM_CCGR1_EPIT1_OFFSET MXC_CCM_CCGR1_CG6_OFFSET
420 #define MXC_CCM_CCGR1_ENET_OFFSET MXC_CCM_CCGR1_CG5_OFFSET
421 #define MXC_CCM_CCGR1_ECSPI5_OFFSET MXC_CCM_CCGR1_CG4_OFFSET
422 #define MXC_CCM_CCGR1_ECSPI4_OFFSET MXC_CCM_CCGR1_CG3_OFFSET
423 #define MXC_CCM_CCGR1_ECSPI3_OFFSET MXC_CCM_CCGR1_CG2_OFFSET
424 #define MXC_CCM_CCGR1_ECSPI2_OFFSET MXC_CCM_CCGR1_CG1_OFFSET
425 #define MXC_CCM_CCGR1_ECSPI1_OFFSET MXC_CCM_CCGR1_CG0_OFFSET
427 #define MXC_CCM_CCGR2_CG13_OFFSET 26
428 #define MXC_CCM_CCGR2_CG12_OFFSET 24
429 #define MXC_CCM_CCGR2_CG11_OFFSET 22
430 #define MXC_CCM_CCGR2_CG10_OFFSET 20
431 #define MXC_CCM_CCGR2_CG9_OFFSET 18
432 #define MXC_CCM_CCGR2_CG8_OFFSET 16
433 #define MXC_CCM_CCGR2_CG7_OFFSET 14
434 #define MXC_CCM_CCGR2_CG6_OFFSET 12
435 #define MXC_CCM_CCGR2_CG6_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR2_CG6_OFFSET)
436 #define MXC_CCM_CCGR2_CG5_OFFSET 10
437 #define MXC_CCM_CCGR2_CG4_OFFSET 8
438 #define MXC_CCM_CCGR2_CG3_OFFSET 6
439 #define MXC_CCM_CCGR2_CG2_OFFSET 4
440 #define MXC_CCM_CCGR2_CG1_OFFSET 2
441 #define MXC_CCM_CCGR2_CG0_OFFSET 0
443 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_OFFSET MXC_CCM_CCGR2_CG13_OFFSET
444 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_TZASC2_OFFSET MXC_CCM_CCGR2_CG12_OFFSET
445 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1__OFFSET MXC_CCM_CCGR2_CG11_OFFSET
446 #define MXC_CCM_CCGR2_IPMUX3_OFFSET MXC_CCM_CCGR2_CG10_OFFSET
447 #define MXC_CCM_CCGR2_IPMUX2_OFFSET MXC_CCM_CCGR2_CG9_OFFSET
448 #define MXC_CCM_CCGR2_IPMUX1_OFFSET MXC_CCM_CCGR2_CG8_OFFSET
449 #define MXC_CCM_CCGR2_IOMUX_IPT_OFFSET MXC_CCM_CCGR2_CG7_OFFSET
450 #define MXC_CCM_CCGR2_OCOTP_OFFSET MXC_CCM_CCGR2_CG6_OFFSET
451 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET MXC_CCM_CCGR2_CG5_OFFSET
452 #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET MXC_CCM_CCGR2_CG4_OFFSET
453 #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET MXC_CCM_CCGR2_CG3_OFFSET
454 #define MXC_CCM_CCGR2_HDMI_TX_ISFR_OFFSET MXC_CCM_CCGR2_CG2_OFFSET
455 #define MXC_CCM_CCGR2_HDMI_TX_IAHB_OFFSET MXC_CCM_CCGR2_CG0_OFFSET
457 #define MXC_CCM_CCGR3_CG15_OFFSET 30
458 #define MXC_CCM_CCGR3_CG14_OFFSET 28
459 #define MXC_CCM_CCGR3_CG13_OFFSET 26
460 #define MXC_CCM_CCGR3_CG12_OFFSET 24
461 #define MXC_CCM_CCGR3_CG11_OFFSET 22
462 #define MXC_CCM_CCGR3_CG10_OFFSET 20
463 #define MXC_CCM_CCGR3_CG9_OFFSET 18
464 #define MXC_CCM_CCGR3_CG8_OFFSET 16
465 #define MXC_CCM_CCGR3_CG7_OFFSET 14
466 #define MXC_CCM_CCGR3_CG6_OFFSET 12
467 #define MXC_CCM_CCGR3_CG5_OFFSET 10
468 #define MXC_CCM_CCGR3_CG4_OFFSET 8
469 #define MXC_CCM_CCGR3_CG3_OFFSET 6
470 #define MXC_CCM_CCGR3_CG2_OFFSET 4
471 #define MXC_CCM_CCGR3_CG1_OFFSET 2
472 #define MXC_CCM_CCGR3_CG0_OFFSET 0
473 #define MXC_CCM_CCGR3_CG0_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR3_CG0_OFFSET)
475 #define MXC_CCM_CCGR3_OPENVGAXI_OFFSET MXC_CCM_CCGR3_CG15_OFFSET
476 #define MXC_CCM_CCGR3_OCRAM_OFFSET MXC_CCM_CCGR3_CG14_OFFSET
477 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_P1_OFFSET MXC_CCM_CCGR3_CG13_OFFSET
478 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_P0_OFFSET MXC_CCM_CCGR3_CG12_OFFSET
479 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_P1_OFFSET MXC_CCM_CCGR3_CG11_OFFSET
480 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_P0_OFFSET MXC_CCM_CCGR3_CG10_OFFSET
481 #define MXC_CCM_CCGR3_MLB_OFFSET MXC_CCM_CCGR3_CG9_OFFSET
482 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET MXC_CCM_CCGR3_CG8_OFFSET
483 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET MXC_CCM_CCGR3_CG7_OFFSET
484 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET MXC_CCM_CCGR3_CG6_OFFSET
485 #define MXC_CCM_CCGR3_IPU2_DI1_OFFSET MXC_CCM_CCGR3_CG5_OFFSET
486 #define MXC_CCM_CCGR3_IPU2_DI0_OFFSET MXC_CCM_CCGR3_CG4_OFFSET
487 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET MXC_CCM_CCGR3_CG3_OFFSET
488 #define MXC_CCM_CCGR3_IPU1_DI1_OFFSET MXC_CCM_CCGR3_CG2_OFFSET
489 #define MXC_CCM_CCGR3_IPU1_DI0_OFFSET MXC_CCM_CCGR3_CG1_OFFSET
490 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET MXC_CCM_CCGR3_CG0_OFFSET
492 #define MXC_CCM_CCGR4_CG15_OFFSET 30
493 #define MXC_CCM_CCGR4_CG14_OFFSET 28
494 #define MXC_CCM_CCGR4_CG13_OFFSET 26
495 #define MXC_CCM_CCGR4_CG12_OFFSET 24
496 #define MXC_CCM_CCGR4_CG11_OFFSET 22
497 #define MXC_CCM_CCGR4_CG10_OFFSET 20
498 #define MXC_CCM_CCGR4_CG9_OFFSET 18
499 #define MXC_CCM_CCGR4_CG8_OFFSET 16
500 #define MXC_CCM_CCGR4_CG7_OFFSET 14
501 #define MXC_CCM_CCGR4_CG6_OFFSET 12
502 #define MXC_CCM_CCGR4_CG5_OFFSET 10
503 #define MXC_CCM_CCGR4_CG4_OFFSET 8
504 #define MXC_CCM_CCGR4_CG3_OFFSET 6
505 #define MXC_CCM_CCGR4_CG2_OFFSET 4
506 #define MXC_CCM_CCGR4_CG1_OFFSET 2
507 #define MXC_CCM_CCGR4_CG0_OFFSET 0
510 #define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG15_OFFSET
511 #define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG14_OFFSET
512 #define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG13_OFFSET
513 #define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG12_OFFSET
514 #define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG11_OFFSET
515 #define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG10_OFFSET
516 #define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG9_OFFSET
517 #define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG8_OFFSET
518 #define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG7_OFFSET
519 #define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG6_OFFSET
520 #define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG5_OFFSET
521 #define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG4_OFFSET
522 #define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG3_OFFSET
523 #define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG2_OFFSET
524 #define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG1_OFFSET
525 #define MXC_CCM_CCGR4__OFFSET MXC_CCM_CCGR4_CG0_OFFSET
528 #define MXC_CCM_CCGR5_CG15_OFFSET 30
529 #define MXC_CCM_CCGR5_CG14_OFFSET 28
530 #define MXC_CCM_CCGR5_CG14_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG14_OFFSET)
531 #define MXC_CCM_CCGR5_CG13_OFFSET 26
532 #define MXC_CCM_CCGR5_CG13_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG13_OFFSET)
533 #define MXC_CCM_CCGR5_CG12_OFFSET 24
534 #define MXC_CCM_CCGR5_CG12_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG12_OFFSET)
535 #define MXC_CCM_CCGR5_CG11_OFFSET 22
536 #define MXC_CCM_CCGR5_CG11_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG11_OFFSET)
537 #define MXC_CCM_CCGR5_CG10_OFFSET 20
538 #define MXC_CCM_CCGR5_CG10_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG10_OFFSET)
539 #define MXC_CCM_CCGR5_CG9_OFFSET 18
540 #define MXC_CCM_CCGR5_CG9_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG9_OFFSET)
541 #define MXC_CCM_CCGR5_CG8_OFFSET 16
542 #define MXC_CCM_CCGR5_CG8_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG8_OFFSET)
543 #define MXC_CCM_CCGR5_CG7_OFFSET 14
544 #define MXC_CCM_CCGR5_CG7_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG7_OFFSET)
545 #define MXC_CCM_CCGR5_CG6_OFFSET 12
546 #define MXC_CCM_CCGR5_CG6_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG6_OFFSET)
547 #define MXC_CCM_CCGR5_CG5_OFFSET 10
548 #define MXC_CCM_CCGR5_CG4_OFFSET 8
549 #define MXC_CCM_CCGR5_CG3_OFFSET 6
550 #define MXC_CCM_CCGR5_CG2_OFFSET 4
551 #define MXC_CCM_CCGR5_CG2_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR5_CG2_OFFSET)
552 #define MXC_CCM_CCGR5_CG1_OFFSET 2
553 #define MXC_CCM_CCGR5_CG0_OFFSET 0
556 #define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG15_OFFSET
557 #define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG14_OFFSET
558 #define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG13_OFFSET
559 #define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG12_OFFSET
560 #define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG11_OFFSET
561 #define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG10_OFFSET
562 #define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG9_OFFSET
563 #define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG8_OFFSET
564 #define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG7_OFFSET
565 #define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG6_OFFSET
566 #define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG5_OFFSET
567 #define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG4_OFFSET
568 #define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG3_OFFSET
569 #define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG1_OFFSET
570 #define MXC_CCM_CCGR5__OFFSET MXC_CCM_CCGR5_CG0_OFFSET
572 #define MXC_CCM_CCGR5_SATA_MASK MXC_CCM_CCGR5_CG2_MASK
574 #define MXC_CCM_CCGR6_CG15_OFFSET 30
575 #define MXC_CCM_CCGR6_CG14_OFFSET 28
576 #define MXC_CCM_CCGR6_CG14_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG14_OFFSET)
577 #define MXC_CCM_CCGR6_CG13_OFFSET 26
578 #define MXC_CCM_CCGR6_CG13_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG13_OFFSET)
579 #define MXC_CCM_CCGR6_CG12_OFFSET 24
580 #define MXC_CCM_CCGR6_CG12_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG12_OFFSET)
581 #define MXC_CCM_CCGR6_CG11_OFFSET 22
582 #define MXC_CCM_CCGR6_CG11_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG11_OFFSET)
583 #define MXC_CCM_CCGR6_CG10_OFFSET 20
584 #define MXC_CCM_CCGR6_CG10_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG10_OFFSET)
585 #define MXC_CCM_CCGR6_CG9_OFFSET 18
586 #define MXC_CCM_CCGR6_CG9_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG9_OFFSET)
587 #define MXC_CCM_CCGR6_CG8_OFFSET 16
588 #define MXC_CCM_CCGR6_CG8_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG8_OFFSET)
589 #define MXC_CCM_CCGR6_CG7_OFFSET 14
590 #define MXC_CCM_CCGR6_CG7_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG7_OFFSET)
591 #define MXC_CCM_CCGR6_CG6_OFFSET 12
592 #define MXC_CCM_CCGR6_CG6_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG6_OFFSET)
593 #define MXC_CCM_CCGR6_CG5_OFFSET 10
594 #define MXC_CCM_CCGR6_CG4_OFFSET 8
595 #define MXC_CCM_CCGR6_CG3_OFFSET 6
596 #define MXC_CCM_CCGR6_CG2_OFFSET 4
597 #define MXC_CCM_CCGR6_CG2_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG2_OFFSET)
598 #define MXC_CCM_CCGR6_CG1_OFFSET 2
599 #define MXC_CCM_CCGR6_CG1_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG1_OFFSET)
600 #define MXC_CCM_CCGR6_CG0_OFFSET 0
601 #define MXC_CCM_CCGR6_CG0_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR6_CG0_OFFSET)
604 #define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG15_OFFSET
605 #define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG14_OFFSET
606 #define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG13_OFFSET
607 #define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG12_OFFSET
608 #define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG11_OFFSET
609 #define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG10_OFFSET
610 #define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG9_OFFSET
611 #define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG8_OFFSET
612 #define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG7_OFFSET
613 #define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG6_OFFSET
614 #define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG5_OFFSET
615 #define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG4_OFFSET
616 #define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG3_OFFSET
617 #define MXC_CCM_CCGR6__OFFSET MXC_CCM_CCGR6_CG2_OFFSET
619 #define MXC_CCM_CCGR6_USDHC1_MASK MXC_CCM_CCGR6_CG1_MASK
620 #define MXC_CCM_CCGR6_USBOH3_MASK MXC_CCM_CCGR6_CG0_MASK
622 #define MXC_CCM_CCGR7_CG15_OFFSET 30
623 #define MXC_CCM_CCGR7_CG14_OFFSET 28
624 #define MXC_CCM_CCGR7_CG14_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG14_OFFSET)
625 #define MXC_CCM_CCGR7_CG13_OFFSET 26
626 #define MXC_CCM_CCGR7_CG13_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG13_OFFSET)
627 #define MXC_CCM_CCGR7_CG12_OFFSET 24
628 #define MXC_CCM_CCGR7_CG12_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG12_OFFSET)
629 #define MXC_CCM_CCGR7_CG11_OFFSET 22
630 #define MXC_CCM_CCGR7_CG11_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG11_OFFSET)
631 #define MXC_CCM_CCGR7_CG10_OFFSET 20
632 #define MXC_CCM_CCGR7_CG10_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG10_OFFSET)
633 #define MXC_CCM_CCGR7_CG9_OFFSET 18
634 #define MXC_CCM_CCGR7_CG9_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG9_OFFSET)
635 #define MXC_CCM_CCGR7_CG8_OFFSET 16
636 #define MXC_CCM_CCGR7_CG8_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG8_OFFSET)
637 #define MXC_CCM_CCGR7_CG7_OFFSET 14
638 #define MXC_CCM_CCGR7_CG7_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG7_OFFSET)
639 #define MXC_CCM_CCGR7_CG6_OFFSET 12
640 #define MXC_CCM_CCGR7_CG6_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG6_OFFSET)
641 #define MXC_CCM_CCGR7_CG5_OFFSET 10
642 #define MXC_CCM_CCGR7_CG4_OFFSET 8
643 #define MXC_CCM_CCGR7_CG3_OFFSET 6
644 #define MXC_CCM_CCGR7_CG2_OFFSET 4
645 #define MXC_CCM_CCGR7_CG2_MASK (MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR7_CG2_OFFSET)
646 #define MXC_CCM_CCGR7_CG1_OFFSET 2
647 #define MXC_CCM_CCGR7_CG0_OFFSET 0
650 #define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG15_OFFSET
651 #define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG14_OFFSET
652 #define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG13_OFFSET
653 #define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG12_OFFSET
654 #define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG11_OFFSET
655 #define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG10_OFFSET
656 #define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG9_OFFSET
657 #define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG8_OFFSET
658 #define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG7_OFFSET
659 #define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG6_OFFSET
660 #define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG5_OFFSET
661 #define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG4_OFFSET
662 #define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG3_OFFSET
663 #define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG2_OFFSET
664 #define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG1_OFFSET
665 #define MXC_CCM_CCGR7__OFFSET MXC_CCM_CCGR7_CG0_OFFSET
669 mx6_reg_32(pll_arm); /* 0x000 */
670 mx6_reg_32(usb1_pll_480_ctrl); /* 0x010 */
671 mx6_reg_32(usb2_pll_480_ctrl); /* 0x020 */
672 mx6_reg_32(pll_528); /* 0x030 */
673 reg_32(pll_528_ss); /* 0x040 */
674 reg_32(pll_528_num); /* 0x050 */
675 reg_32(pll_528_denom); /* 0x060 */
676 mx6_reg_32(pll_audio); /* 0x070 */
677 reg_32(pll_audio_num); /* 0x080 */
678 reg_32(pll_audio_denom); /* 0x090 */
679 mx6_reg_32(pll_video); /* 0x0a0 */
680 reg_32(pll_video_num); /* 0x0b0 */
681 reg_32(pll_video_denom); /* 0x0c0 */
682 mx6_reg_32(pll_mlb); /* 0x0d0 */
683 mx6_reg_32(pll_enet); /* 0x0e0 */
684 mx6_reg_32(pfd_480); /* 0x0f0 */
685 mx6_reg_32(pfd_528); /* 0x100 */
686 mx6_reg_32(reg_1p1); /* 0x110 */
687 mx6_reg_32(reg_3p0); /* 0x120 */
688 mx6_reg_32(reg_2p5); /* 0x130 */
689 mx6_reg_32(reg_core); /* 0x140 */
690 mx6_reg_32(ana_misc0); /* 0x150 */
691 mx6_reg_32(ana_misc1); /* 0x160 */
692 mx6_reg_32(ana_misc2); /* 0x170 */
693 mx6_reg_32(tempsense0); /* 0x180 */
694 mx6_reg_32(tempsense1); /* 0x190 */
695 mx6_reg_32(usb1_vbus_detect); /* 0x1a0 */
696 mx6_reg_32(usb1_chrg_detect); /* 0x1b0 */
697 mx6_reg_32(usb1_vbus_det_stat); /* 0x1c0 */
698 mx6_reg_32(usb1_chrg_det_stat); /* 0x1d0 */
699 mx6_reg_32(usb1_loopback); /* 0x1e0 */
700 mx6_reg_32(usb1_misc); /* 0x1f0 */
701 mx6_reg_32(usb2_vbus_detect); /* 0x200 */
702 mx6_reg_32(usb2_chrg_detect); /* 0x210 */
703 mx6_reg_32(usb2_vbus_det_stat); /* 0x220 */
704 mx6_reg_32(usb2_chrg_det_stat); /* 0x230 */
705 mx6_reg_32(usb2_loopback); /* 0x240 */
706 mx6_reg_32(usb2_misc); /* 0x250 */
707 reg_32(digprog); /* 0x260 */
708 reg_32(rsrvd); /* 0x270 */
709 reg_32(digprog_sololite); /* 0x280 */
712 #define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0
713 #define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f << ANATOP_PFD_480_PFD0_FRAC_SHIFT)
714 #define ANATOP_PFD_480_PFD0_STABLE_SHIFT 6
715 #define ANATOP_PFD_480_PFD0_STABLE_MASK (1 << ANATOP_PFD_480_PFD0_STABLE_SHIFT)
716 #define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT 7
717 #define ANATOP_PFD_480_PFD0_CLKGATE_MASK (1 << ANATOP_PFD_480_PFD0_CLKGATE_SHIFT)
718 #define ANATOP_PFD_480_PFD1_FRAC_SHIFT 8
719 #define ANATOP_PFD_480_PFD1_FRAC_MASK (0x3f << ANATOP_PFD_480_PFD1_FRAC_SHIFT)
720 #define ANATOP_PFD_480_PFD1_STABLE_SHIFT 14
721 #define ANATOP_PFD_480_PFD1_STABLE_MASK (1 << ANATOP_PFD_480_PFD1_STABLE_SHIFT)
722 #define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT 15
723 #define ANATOP_PFD_480_PFD1_CLKGATE_MASK (0x3f << ANATOP_PFD_480_PFD1_CLKGATE_SHIFT)
724 #define ANATOP_PFD_480_PFD2_FRAC_SHIFT 16
725 #define ANATOP_PFD_480_PFD2_FRAC_MASK (1 << ANATOP_PFD_480_PFD2_FRAC_SHIFT)
726 #define ANATOP_PFD_480_PFD2_STABLE_SHIFT 22
727 #define ANATOP_PFD_480_PFD2_STABLE_MASK (1 << ANATOP_PFD_480_PFD2_STABLE_SHIFT)
728 #define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT 23
729 #define ANATOP_PFD_480_PFD2_CLKGATE_MASK (0x3f << ANATOP_PFD_480_PFD2_CLKGATE_SHIFT)
730 #define ANATOP_PFD_480_PFD3_FRAC_SHIFT 24
731 #define ANATOP_PFD_480_PFD3_FRAC_MASK (1 << ANATOP_PFD_480_PFD3_FRAC_SHIFT)
732 #define ANATOP_PFD_480_PFD3_STABLE_SHIFT 30
733 #define ANATOP_PFD_480_PFD3_STABLE_MASK (1 << ANATOP_PFD_480_PFD3_STABLE_SHIFT)
734 #define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT 31
736 #define BM_ANADIG_PLL_ARM_LOCK (1 << 31)
737 #define BM_ANADIG_PLL_ARM_PLL_SEL (1 << 19)
738 #define BM_ANADIG_PLL_ARM_LVDS_24MHZ_SEL (1 << 18)
739 #define BM_ANADIG_PLL_ARM_LVDS_SEL (1 << 17)
740 #define BM_ANADIG_PLL_ARM_BYPASS (1 << 16)
741 #define BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC 14
742 #define BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
743 #define BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(v) \
744 (((v) << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC) & BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC)
745 #define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__OSC_24M BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(0)
746 #define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_1 BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(1)
747 #define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_2 BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(2)
748 #define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__XOR BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(3)
749 #define BM_ANADIG_PLL_ARM_ENABLE (1 << 13)
750 #define BM_ANADIG_PLL_ARM_POWERDOWN (1 << 12)
751 #define BM_ANADIG_PLL_ARM_HOLD_RING_OFF (1 << 11)
752 #define BM_ANADIG_PLL_ARM_DOUBLE_CP (1 << 10)
753 #define BM_ANADIG_PLL_ARM_HALF_CP (1 << 9)
754 #define BM_ANADIG_PLL_ARM_DOUBLE_LF (1 << 8)
755 #define BM_ANADIG_PLL_ARM_HALF_LF (1 << 7)
756 #define BP_ANADIG_PLL_ARM_DIV_SELECT 0
757 #define BM_ANADIG_PLL_ARM_DIV_SELECT (0x7F << BP_ANADIG_PLL_ARM_DIV_SELECT)
758 #define BF_ANADIG_PLL_ARM_DIV_SELECT(v) \
759 (((v) << BP_ANADIG_PLL_ARM_DIV_SELECT) & \
760 BM_ANADIG_PLL_ARM_DIV_SELECT)
762 #define BM_ANADIG_USB1_PLL_480_CTRL_LOCK (1 << 31)
763 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS (1 << 16)
764 #define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14
765 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
766 #define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
767 (((v) << BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) & \
768 BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
769 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(0)
770 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(1)
771 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(2)
772 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(3)
773 #define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE (1 << 13)
774 #define BM_ANADIG_USB1_PLL_480_CTRL_POWER (1 << 12)
775 #define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF (1 << 11)
776 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP (1 << 10)
777 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP (1 << 9)
778 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF (1 << 8)
779 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF (1 << 7)
780 #define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS (1 << 6)
781 #define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2
782 #define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 (0x7 << BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
783 #define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \
784 (((v) << BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0) & \
785 BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
786 #define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0
787 #define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT (0x3 << BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
788 #define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \
789 (((v) << BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) & \
790 BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
792 #define BM_ANADIG_USB2_PLL_480_CTRL_LOCK (1 << 31)
793 #define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS (1 << 16)
794 #define BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC 14
795 #define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC)
796 #define BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
797 (((v) << BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC) & \
798 BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC)
799 #define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(0)
800 #define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(1)
801 #define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(2)
802 #define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__XOR BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(3)
803 #define BM_ANADIG_USB2_PLL_480_CTRL_ENABLE (1 << 13)
804 #define BM_ANADIG_USB2_PLL_480_CTRL_POWER (1 << 12)
805 #define BM_ANADIG_USB2_PLL_480_CTRL_HOLD_RING_OFF (1 << 11)
806 #define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_CP (1 << 10)
807 #define BM_ANADIG_USB2_PLL_480_CTRL_HALF_CP (1 << 9)
808 #define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_LF (1 << 8)
809 #define BM_ANADIG_USB2_PLL_480_CTRL_HALF_LF (1 << 7)
810 #define BM_ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS (1 << 6)
811 #define BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0 2
812 #define BM_ANADIG_USB2_PLL_480_CTRL_CONTROL0 (0x7 << BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0)
813 #define BF_ANADIG_USB2_PLL_480_CTRL_CONTROL0(v) \
814 (((v) << BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0) & \
815 BM_ANADIG_USB2_PLL_480_CTRL_CONTROL0)
816 #define BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT 0
817 #define BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT (0x3 << BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT)
818 #define BF_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT(v) \
819 (((v) << BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT) & \
820 BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT)
822 #define BM_ANADIG_PLL_SYS_LOCK (1 << 31)
823 #define BM_ANADIG_PLL_SYS_PLL_SEL (1 << 19)
824 #define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL (1 << 18)
825 #define BM_ANADIG_PLL_SYS_LVDS_SEL (1 << 17)
826 #define BM_ANADIG_PLL_SYS_BYPASS (1 << 16)
827 #define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14
828 #define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
829 #define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \
830 (((v) << BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
831 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0
832 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
833 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
834 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3
835 #define BM_ANADIG_PLL_SYS_ENABLE (1 << 13)
836 #define BM_ANADIG_PLL_SYS_POWERDOWN (1 << 12)
837 #define BM_ANADIG_PLL_SYS_HOLD_RING_OFF (1 << 11)
838 #define BM_ANADIG_PLL_SYS_DOUBLE_CP (1 << 10)
839 #define BM_ANADIG_PLL_SYS_HALF_CP (1 << 9)
840 #define BM_ANADIG_PLL_SYS_DOUBLE_LF (1 << 8)
841 #define BM_ANADIG_PLL_SYS_HALF_LF (1 << 7)
842 #define BP_ANADIG_PLL_SYS_DIV_SELECT 0
843 #define BM_ANADIG_PLL_SYS_DIV_SELECT (0x7F << BP_ANADIG_PLL_SYS_DIV_SELECT)
844 #define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \
845 (((v) << BP_ANADIG_PLL_SYS_DIV_SELECT) & BM_ANADIG_PLL_SYS_DIV_SELECT)
847 #define BM_ANADIG_PLL_AUDIO_LOCK (1 << 31)
848 #define BM_ANADIG_PLL_AUDIO_SSC_EN (1 << 21)
849 #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
850 #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
851 #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
852 (((v) << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
853 #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN (1 << 18)
854 #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE (1 << 17)
855 #define BM_ANADIG_PLL_AUDIO_BYPASS (1 << 16)
856 #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
857 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
858 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
859 (((v) << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
860 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
861 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
862 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
863 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
864 #define BM_ANADIG_PLL_AUDIO_ENABLE (1 << 13)
865 #define BM_ANADIG_PLL_AUDIO_POWERDOWN (1 << 12)
866 #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF (1 << 11)
867 #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP (1 << 10)
868 #define BM_ANADIG_PLL_AUDIO_HALF_CP (1 << 9)
869 #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF (1 << 8)
870 #define BM_ANADIG_PLL_AUDIO_HALF_LF (1 << 7)
871 #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
872 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT (0x7F << BP_ANADIG_PLL_AUDIO_DIV_SELECT)
873 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
874 (((v) << BP_ANADIG_PLL_AUDIO_DIV_SELECT) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
876 #define BP_ANADIG_PLL_AUDIO_NUM_A 0
877 #define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
878 #define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
879 (((v) << BP_ANADIG_PLL_AUDIO_NUM_A) & BM_ANADIG_PLL_AUDIO_NUM_A)
881 #define BP_ANADIG_PLL_AUDIO_DENOM_B 0
882 #define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
883 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
884 (((v) << BP_ANADIG_PLL_AUDIO_DENOM_B) & BM_ANADIG_PLL_AUDIO_DENOM_B)
886 #define BM_ANADIG_PLL_VIDEO_LOCK (1 << 31)
887 #define BM_ANADIG_PLL_VIDEO_SSC_EN (1 << 21)
888 #define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19
889 #define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
890 #define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \
891 (((v) << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
892 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN (1 << 18)
893 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE (1 << 17)
894 #define BM_ANADIG_PLL_VIDEO_BYPASS (1 << 16)
895 #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
896 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
897 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
898 (((v) << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
899 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
900 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
901 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
902 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
903 #define BM_ANADIG_PLL_VIDEO_ENABLE (1 << 13)
904 #define BM_ANADIG_PLL_VIDEO_POWERDOWN (1 << 12)
905 #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF (1 << 11)
906 #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP (1 << 10)
907 #define BM_ANADIG_PLL_VIDEO_HALF_CP (1 << 9)
908 #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF (1 << 8)
909 #define BM_ANADIG_PLL_VIDEO_HALF_LF (1 << 7)
910 #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
911 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT (0x7F << BP_ANADIG_PLL_VIDEO_DIV_SELECT)
912 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
913 (((v) << BP_ANADIG_PLL_VIDEO_DIV_SELECT) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
915 #define BP_ANADIG_PLL_VIDEO_NUM_A 0
916 #define BM_ANADIG_PLL_VIDEO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_NUM_A)
917 #define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
918 (((v) << BP_ANADIG_PLL_VIDEO_NUM_A) & BM_ANADIG_PLL_VIDEO_NUM_A)
920 #define BP_ANADIG_PLL_VIDEO_DENOM_B 0
921 #define BM_ANADIG_PLL_VIDEO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_DENOM_B)
922 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
923 (((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & BM_ANADIG_PLL_VIDEO_DENOM_B)
925 #define BM_ANADIG_PLL_MLB_LOCK (1 << 31)
926 #define BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG 26
927 #define BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
928 #define BF_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG(v) \
929 (((v) << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG) & BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG)
930 #define BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG 23
931 #define BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
932 #define BF_ANADIG_PLL_MLB_RX_CLK_DLY_CFG(v) \
933 (((v) << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG) & BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG)
934 #define BP_ANADIG_PLL_MLB_VDDD_DLY_CFG 20
935 #define BM_ANADIG_PLL_MLB_VDDD_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG)
936 #define BF_ANADIG_PLL_MLB_VDDD_DLY_CFG(v) \
937 (((v) << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG) & BM_ANADIG_PLL_MLB_VDDD_DLY_CFG)
938 #define BP_ANADIG_PLL_MLB_VDDA_DLY_CFG 17
939 #define BM_ANADIG_PLL_MLB_VDDA_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG)
940 #define BF_ANADIG_PLL_MLB_VDDA_DLY_CFG(v) \
941 (((v) << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG) & BM_ANADIG_PLL_MLB_VDDA_DLY_CFG)
942 #define BM_ANADIG_PLL_MLB_BYPASS (1 << 16)
943 #define BP_ANADIG_PLL_MLB_PHASE_SEL 12
944 #define BM_ANADIG_PLL_MLB_PHASE_SEL (0x7 << BP_ANADIG_PLL_MLB_PHASE_SEL)
945 #define BF_ANADIG_PLL_MLB_PHASE_SEL(v) \
946 (((v) << BP_ANADIG_PLL_MLB_PHASE_SEL) & BM_ANADIG_PLL_MLB_PHASE_SEL)
947 #define BM_ANADIG_PLL_MLB_HOLD_RING_OFF (1 << 11)
949 #define BM_ANADIG_PLL_ENET_LOCK (1 << 31)
950 #define BM_ANADIG_PLL_ENET_ENABLE_SATA (1 << 20)
951 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE (1 << 19)
952 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN (1 << 18)
953 #define BM_ANADIG_PLL_ENET_DITHER_ENABLE (1 << 17)
954 #define BM_ANADIG_PLL_ENET_BYPASS (1 << 16)
955 #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
956 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
957 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
958 (((v) << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
959 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
960 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
961 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
962 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
963 #define BM_ANADIG_PLL_ENET_ENABLE (1 << 13)
964 #define BM_ANADIG_PLL_ENET_POWERDOWN (1 << 12)
965 #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF (1 << 11)
966 #define BM_ANADIG_PLL_ENET_DOUBLE_CP (1 << 10)
967 #define BM_ANADIG_PLL_ENET_HALF_CP (1 << 9)
968 #define BM_ANADIG_PLL_ENET_DOUBLE_LF (1 << 8)
969 #define BM_ANADIG_PLL_ENET_HALF_LF (1 << 7)
970 #define BP_ANADIG_PLL_ENET_DIV_SELECT 0
971 #define BM_ANADIG_PLL_ENET_DIV_SELECT (0x3 << BP_ANADIG_PLL_ENET_DIV_SELECT)
972 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
973 (((v) << BP_ANADIG_PLL_ENET_DIV_SELECT) & BM_ANADIG_PLL_ENET_DIV_SELECT)
975 #define BM_ANADIG_PFD_480_PFD3_CLKGATE (1 << 31)
976 #define BM_ANADIG_PFD_480_PFD3_STABLE (1 << 30)
977 #define BP_ANADIG_PFD_480_PFD3_FRAC 24
978 #define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
979 #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
980 (((v) << BP_ANADIG_PFD_480_PFD3_FRAC) & BM_ANADIG_PFD_480_PFD3_FRAC)
981 #define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000
982 #define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000
983 #define BP_ANADIG_PFD_480_PFD2_FRAC 16
984 #define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000
985 #define BF_ANADIG_PFD_480_PFD2_FRAC(v) \
986 (((v) << BP_ANADIG_PFD_480_PFD2_FRAC) & BM_ANADIG_PFD_480_PFD2_FRAC)
987 #define BM_ANADIG_PFD_480_PFD1_CLKGATE (1 << 15)
988 #define BM_ANADIG_PFD_480_PFD1_STABLE (1 << 14)
989 #define BP_ANADIG_PFD_480_PFD1_FRAC 8
990 #define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00
991 #define BF_ANADIG_PFD_480_PFD1_FRAC(v) \
992 (((v) << BP_ANADIG_PFD_480_PFD1_FRAC) & BM_ANADIG_PFD_480_PFD1_FRAC)
993 #define BM_ANADIG_PFD_480_PFD0_CLKGATE (1 << 7)
994 #define BM_ANADIG_PFD_480_PFD0_STABLE (1 << 6)
995 #define BP_ANADIG_PFD_480_PFD0_FRAC 0
996 #define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F
997 #define BF_ANADIG_PFD_480_PFD0_FRAC(v) \
998 (((v) << BP_ANADIG_PFD_480_PFD0_FRAC) & BM_ANADIG_PFD_480_PFD0_FRAC)
1000 #define BM_ANADIG_PFD_528_PFD3_CLKGATE (1 << 31)
1001 #define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000
1002 #define BP_ANADIG_PFD_528_PFD3_FRAC 24
1003 #define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000
1004 #define BF_ANADIG_PFD_528_PFD3_FRAC(v) \
1005 (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
1006 #define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000
1007 #define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000
1008 #define BP_ANADIG_PFD_528_PFD2_FRAC 16
1009 #define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000
1010 #define BF_ANADIG_PFD_528_PFD2_FRAC(v) \
1011 (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
1012 #define BM_ANADIG_PFD_528_PFD1_CLKGATE (1 << 15)
1013 #define BM_ANADIG_PFD_528_PFD1_STABLE (1 << 14)
1014 #define BP_ANADIG_PFD_528_PFD1_FRAC 8
1015 #define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00
1016 #define BF_ANADIG_PFD_528_PFD1_FRAC(v) \
1017 (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
1018 #define BM_ANADIG_PFD_528_PFD0_CLKGATE (1 << 7)
1019 #define BM_ANADIG_PFD_528_PFD0_STABLE (1 << 6)
1020 #define BP_ANADIG_PFD_528_PFD0_FRAC 0
1021 #define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F
1022 #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
1023 (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
1025 #define BP_ANADIG_ANA_MISC0_CLKGATE_DELAY 26
1026 #define BM_ANADIG_ANA_MISC0_CLKGATE_DELAY (0x7 << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY)
1027 #define BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(v) \
1028 (((v) << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY) & BM_ANADIG_ANA_MISC0_CLKGATE_DELAY)
1029 #define BM_ANADIG_ANA_MISC0_CLKGATE_CTRL (1 << 25)
1030 #define BP_ANADIG_ANA_MISC0_ANAMUX 21
1031 #define BM_ANADIG_ANA_MISC0_ANAMUX (0xf << BP_ANADIG_ANA_MISC0_ANAMUX)
1032 #define BF_ANADIG_ANA_MISC0_ANAMUX(v) \
1033 (((v) << BP_ANADIG_ANA_MISC0_ANAMUX) & BM_ANADIG_ANA_MISC0_ANAMUX)
1034 #define BM_ANADIG_ANA_MISC0_ANAMUX_EN (1 << 20)
1035 #define BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH 18
1036 #define BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH (0x3 << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
1037 #define BF_ANADIG_ANA_MISC0_WBCP_VPW_THRESH(v) \
1038 (((v) << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) & BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH)
1039 #define BM_ANADIG_ANA_MISC0_OSC_XTALOK_EN (1 << 17)
1040 #define BM_ANADIG_ANA_MISC0_OSC_XTALOK (1 << 16)
1041 #define BP_ANADIG_ANA_MISC0_OSC_I 14
1042 #define BM_ANADIG_ANA_MISC0_OSC_I 0x0000C000
1043 #define BF_ANADIG_ANA_MISC0_OSC_I(v) \
1044 (((v) << BP_ANADIG_ANA_MISC0_OSC_I) & BM_ANADIG_ANA_MISC0_OSC_I)
1045 #define BM_ANADIG_ANA_MISC0_RTC_RINGOSC_EN (1 << 13)
1046 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG (1 << 12)
1047 #define BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 8
1048 #define BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 0x00000300
1049 #define BF_ANADIG_ANA_MISC0_REFTOP_BIAS_TST(v) \
1050 (((v) << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST) & BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST)
1051 #define BM_ANADIG_ANA_MISC0_REFTOP_VBGUP (1 << 7)
1052 #define BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ 4
1053 #define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ (0x7 << BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
1054 #define BF_ANADIG_ANA_MISC0_REFTOP_VBGADJ(v) \
1055 (((v) << BM_ANADIG_ANA_MISC0_REFTOP_VBGUP) & BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ)
1056 #define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF (1 << 3)
1057 #define BM_ANADIG_ANA_MISC0_REFTOP_LOWPOWER (1 << 2)
1058 #define BM_ANADIG_ANA_MISC0_REFTOP_PWDVBGUP (1 << 1)
1059 #define BM_ANADIG_ANA_MISC0_REFTOP_PWD (1 << 0)
1061 #define BM_ANADIG_ANA_MISC1_IRQ_DIG_BO (1 << 31)
1062 #define BM_ANADIG_ANA_MISC1_IRQ_ANA_BO 0x40000000
1063 #define BM_ANADIG_ANA_MISC1_IRQ_TEMPSENSE_BO 0x20000000
1064 #define BM_ANADIG_ANA_MISC1_LVDSCLK2_IBEN (1 << 13)
1065 #define BM_ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
1066 #define BM_ANADIG_ANA_MISC1_LVDSCLK2_OBEN (1 << 11)
1067 #define BM_ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
1068 #define BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 5
1069 #define BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 0x000003E0
1070 #define BF_ANADIG_ANA_MISC1_LVDS2_CLK_SEL(v) \
1071 (((v) << BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL) & BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL)
1072 #define BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0
1073 #define BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0x0000001F
1074 #define BF_ANADIG_ANA_MISC1_LVDS1_CLK_SEL(v) \
1075 (((v) << 0) & BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL)
1077 #define BP_ANADIG_ANA_MISC2_CONTROL3 30
1078 #define BM_ANADIG_ANA_MISC2_CONTROL3 0xC0000000
1079 #define BF_ANADIG_ANA_MISC2_CONTROL3(v) \
1080 (((v) << BP_ANADIG_ANA_MISC2_CONTROL3) & BM_ANADIG_ANA_MISC2_CONTROL3)
1081 #define BP_ANADIG_ANA_MISC2_REG2_STEP_TIME 28
1082 #define BM_ANADIG_ANA_MISC2_REG2_STEP_TIME 0x30000000
1083 #define BF_ANADIG_ANA_MISC2_REG2_STEP_TIME(v) \
1084 (((v) << BP_ANADIG_ANA_MISC2_REG2_STEP_TIME) & BM_ANADIG_ANA_MISC2_REG2_STEP_TIME)
1085 #define BP_ANADIG_ANA_MISC2_REG1_STEP_TIME 26
1086 #define BM_ANADIG_ANA_MISC2_REG1_STEP_TIME 0x0C000000
1087 #define BF_ANADIG_ANA_MISC2_REG1_STEP_TIME(v) \
1088 (((v) << BP_ANADIG_ANA_MISC2_REG1_STEP_TIME) & BM_ANADIG_ANA_MISC2_REG1_STEP_TIME)
1089 #define BP_ANADIG_ANA_MISC2_REG0_STEP_TIME 24
1090 #define BM_ANADIG_ANA_MISC2_REG0_STEP_TIME 0x03000000
1091 #define BF_ANADIG_ANA_MISC2_REG0_STEP_TIME(v) \
1092 (((v) << BP_ANADIG_ANA_MISC2_REG0_STEP_TIME) & BM_ANADIG_ANA_MISC2_REG0_STEP_TIME)
1093 #define BM_ANADIG_ANA_MISC2_CONTROL2 0x00800000
1094 #define BM_ANADIG_ANA_MISC2_REG2_OK 0x00400000
1095 #define BM_ANADIG_ANA_MISC2_REG2_ENABLE_BO (1 << 21)
1096 #define BM_ANADIG_ANA_MISC2_REG2_BO_STATUS (1 << 19)
1097 #define BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET 16
1098 #define BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET 0x00070000
1099 #define BF_ANADIG_ANA_MISC2_REG2_BO_OFFSET(v) \
1100 (((v) << BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET) & BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET)
1101 #define BM_ANADIG_ANA_MISC2_CONTROL1 (1 << 15)
1102 #define BM_ANADIG_ANA_MISC2_REG1_OK (1 << 14)
1103 #define BM_ANADIG_ANA_MISC2_REG1_ENABLE_BO (1 << 13)
1104 #define BM_ANADIG_ANA_MISC2_REG1_BO_STATUS (1 << 11)
1105 #define BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET 8
1106 #define BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET 0x00000700
1107 #define BF_ANADIG_ANA_MISC2_REG1_BO_OFFSET(v) \
1108 (((v) << BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET) & BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET)
1109 #define BM_ANADIG_ANA_MISC2_CONTROL0 (1 << 7)
1110 #define BM_ANADIG_ANA_MISC2_REG0_OK (1 << 6)
1111 #define BM_ANADIG_ANA_MISC2_REG0_ENABLE_BO (1 << 5)
1112 #define BM_ANADIG_ANA_MISC2_REG0_BO_STATUS (1 << 3)
1113 #define BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET 0
1114 #define BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET (0x7 << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
1115 #define BF_ANADIG_ANA_MISC2_REG0_BO_OFFSET(v) \
1116 (((v) << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET) & BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET)
1118 #define BP_ANADIG_TEMPSENSE0_ALARM_VALUE 20
1119 #define BM_ANADIG_TEMPSENSE0_ALARM_VALUE (0xFFF << BP_ANADIG_TEMPSENSE0_ALARM_VALUE)
1120 #define BF_ANADIG_TEMPSENSE0_ALARM_VALUE(v) \
1121 (((v) << BP_ANADIG_TEMPSENSE0_ALARM_VALUE) & BM_ANADIG_TEMPSENSE0_ALARM_VALUE)
1122 #define BP_ANADIG_TEMPSENSE0_TEMP_VALUE 8
1123 #define BM_ANADIG_TEMPSENSE0_TEMP_VALUE (0xFFF << BP_ANADIG_TEMPSENSE0_TEMP_VALUE)
1124 #define BF_ANADIG_TEMPSENSE0_TEMP_VALUE(v) \
1125 (((v) << BP_ANADIG_TEMPSENSE0_TEMP_VALUE) & BM_ANADIG_TEMPSENSE0_TEMP_VALUE)
1126 #define BM_ANADIG_TEMPSENSE0_TEST (1 << 6)
1127 #define BP_ANADIG_TEMPSENSE0_VBGADJ 3
1128 #define BM_ANADIG_TEMPSENSE0_VBGADJ (0x7 << BP_ANADIG_TEMPSENSE0_VBGADJ)
1129 #define BF_ANADIG_TEMPSENSE0_VBGADJ(v) \
1130 (((v) << BP_ANADIG_TEMPSENSE0_VBGADJ) & BM_ANADIG_TEMPSENSE0_VBGADJ)
1131 #define BM_ANADIG_TEMPSENSE0_FINISHED (1 << 2)
1132 #define BM_ANADIG_TEMPSENSE0_MEASURE_TEMP (1 << 1)
1133 #define BM_ANADIG_TEMPSENSE0_POWER_DOWN (1 << 0)
1135 #define BP_ANADIG_TEMPSENSE1_MEASURE_FREQ 0
1136 #define BM_ANADIG_TEMPSENSE1_MEASURE_FREQ (0xFFFF << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ)
1137 #define BF_ANADIG_TEMPSENSE1_MEASURE_FREQ(v) \
1138 (((v) << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ) & BM_ANADIG_TEMPSENSE1_MEASURE_FREQ)
1140 #define PLL2_PFD0_FREQ 352000000
1141 #define PLL2_PFD1_FREQ 594000000
1142 #define PLL2_PFD2_FREQ 400000000
1143 #define PLL2_PFD2_DIV_FREQ 200000000
1144 #define PLL3_PFD0_FREQ 720000000
1145 #define PLL3_PFD1_FREQ 540000000
1146 #define PLL3_PFD2_FREQ 508200000
1147 #define PLL3_PFD3_FREQ 454700000
1148 #define PLL3_80M 80000000
1149 #define PLL3_60M 60000000
1151 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */